2 * linux/arch/arm/mach-omap1/pm.c
4 * OMAP Power Management Routines
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/debugfs.h>
41 #include <linux/seq_file.h>
42 #include <linux/interrupt.h>
43 #include <linux/sysfs.h>
44 #include <linux/module.h>
46 #include <linux/atomic.h>
47 #include <linux/cpu.h>
49 #include <asm/fncpy.h>
50 #include <asm/system_misc.h>
52 #include <asm/mach/time.h>
53 #include <asm/mach/irq.h>
55 #include <linux/soc/ti/omap1-io.h>
57 #include <linux/omap-dma.h>
58 #include <clocksource/timer-ti-dm.h>
69 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
70 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
71 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
72 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
73 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
74 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
76 static unsigned short enable_dyn_sleep;
78 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
81 return sprintf(buf, "%hu\n", enable_dyn_sleep);
84 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
85 const char * buf, size_t n)
88 if (sscanf(buf, "%hu", &value) != 1 ||
89 (value != 0 && value != 1) ||
90 (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
91 pr_err("idle_sleep_store: Invalid value\n");
94 enable_dyn_sleep = value;
98 static struct kobj_attribute sleep_while_idle_attr =
99 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
102 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
105 * Let's power down on idle, but only if we are really
106 * idle, because once we start down the path of
107 * going idle we continue to do idle even if we get
108 * a clock tick interrupt . .
110 void omap1_pm_idle(void)
112 extern __u32 arm_idlect1_mask;
113 __u32 use_idlect1 = arm_idlect1_mask;
117 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
118 use_idlect1 = use_idlect1 & ~(1 << 9);
121 #ifdef CONFIG_OMAP_DM_TIMER
122 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
125 if (omap_dma_running())
126 use_idlect1 &= ~(1 << 6);
129 * We should be able to remove the do_sleep variable and multiple
130 * tests above as soon as drivers, timer and DMA code have been fixed.
131 * Even the sleep block count should become obsolete.
133 if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
135 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
136 if (cpu_is_omap15xx())
137 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
139 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
140 omap_writel(use_idlect1, ARM_IDLECT1);
141 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
142 omap_writel(saved_idlect1, ARM_IDLECT1);
147 omap_sram_suspend(omap_readl(ARM_IDLECT1),
148 omap_readl(ARM_IDLECT2));
154 * Configuration of the wakeup event is board specific. For the
155 * moment we put it into this helper function. Later it may move
156 * to board specific files.
158 static void omap_pm_wakeup_setup(void)
161 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
164 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
165 * and the L2 wakeup interrupts: keypad and UART2. Note that the
166 * drivers must still separately call omap_set_gpio_wakeup() to
167 * wake up to a GPIO interrupt.
169 if (cpu_is_omap7xx())
170 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
171 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
172 else if (cpu_is_omap15xx())
173 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
174 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
175 else if (cpu_is_omap16xx())
176 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
177 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
179 omap_writel(~level1_wake, OMAP_IH1_MIR);
181 if (cpu_is_omap7xx()) {
182 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
183 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
184 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
186 } else if (cpu_is_omap15xx()) {
187 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
188 omap_writel(~level2_wake, OMAP_IH2_MIR);
189 } else if (cpu_is_omap16xx()) {
190 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
191 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
193 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
194 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
196 omap_writel(~0x0, OMAP_IH2_2_MIR);
197 omap_writel(~0x0, OMAP_IH2_3_MIR);
200 /* New IRQ agreement, recalculate in cascade order */
201 omap_writel(1, OMAP_IH2_CONTROL);
202 omap_writel(1, OMAP_IH1_CONTROL);
205 #define EN_DSPCK 13 /* ARM_CKCTL */
206 #define EN_APICK 6 /* ARM_IDLECT2 */
207 #define DSP_EN 1 /* ARM_RSTCT1 */
209 void omap1_pm_suspend(void)
211 unsigned long arg0 = 0, arg1 = 0;
213 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
216 omap_serial_wake_trigger(1);
218 if (!cpu_is_omap15xx())
219 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
222 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
229 * Step 2: save registers
231 * The omap is a strange/beautiful device. The caches, memory
232 * and register state are preserved across power saves.
233 * We have to save and restore very little register state to
236 * Save interrupt, MPUI, ARM and UPLD control registers.
239 if (cpu_is_omap7xx()) {
240 MPUI7XX_SAVE(OMAP_IH1_MIR);
241 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
242 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
243 MPUI7XX_SAVE(MPUI_CTRL);
244 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
245 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
246 MPUI7XX_SAVE(EMIFS_CONFIG);
247 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
249 } else if (cpu_is_omap15xx()) {
250 MPUI1510_SAVE(OMAP_IH1_MIR);
251 MPUI1510_SAVE(OMAP_IH2_MIR);
252 MPUI1510_SAVE(MPUI_CTRL);
253 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
254 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
255 MPUI1510_SAVE(EMIFS_CONFIG);
256 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
257 } else if (cpu_is_omap16xx()) {
258 MPUI1610_SAVE(OMAP_IH1_MIR);
259 MPUI1610_SAVE(OMAP_IH2_0_MIR);
260 MPUI1610_SAVE(OMAP_IH2_1_MIR);
261 MPUI1610_SAVE(OMAP_IH2_2_MIR);
262 MPUI1610_SAVE(OMAP_IH2_3_MIR);
263 MPUI1610_SAVE(MPUI_CTRL);
264 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
265 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
266 MPUI1610_SAVE(EMIFS_CONFIG);
267 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
271 ARM_SAVE(ARM_IDLECT1);
272 ARM_SAVE(ARM_IDLECT2);
273 if (!(cpu_is_omap15xx()))
274 ARM_SAVE(ARM_IDLECT3);
275 ARM_SAVE(ARM_EWUPCT);
276 ARM_SAVE(ARM_RSTCT1);
277 ARM_SAVE(ARM_RSTCT2);
279 ULPD_SAVE(ULPD_CLOCK_CTRL);
280 ULPD_SAVE(ULPD_STATUS_REQ);
282 /* (Step 3 removed - we now allow deep sleep by default) */
285 * Step 4: OMAP DSP Shutdown
289 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
291 /* shut down dsp_ck */
292 if (!cpu_is_omap7xx())
293 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
295 /* temporarily enabling api_ck to access DSP registers */
296 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
298 /* save DSP registers */
299 DSP_SAVE(DSP_IDLECT2);
301 /* Stop all DSP domain clocks */
302 __raw_writew(0, DSP_IDLECT2);
305 * Step 5: Wakeup Event Setup
308 omap_pm_wakeup_setup();
311 * Step 6: ARM and Traffic controller shutdown
314 /* disable ARM watchdog */
315 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
316 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
319 * Step 6b: ARM and Traffic controller shutdown
321 * Step 6 continues here. Prepare jump to power management
322 * assembly code in internal SRAM.
324 * Since the omap_cpu_suspend routine has been copied to
325 * SRAM, we'll do an indirect procedure call to it and pass the
326 * contents of arm_idlect1 and arm_idlect2 so it can restore
327 * them when it wakes up and it will return.
330 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
331 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
334 * Step 6c: ARM and Traffic controller shutdown
336 * Jump to assembly code. The processor will stay there
339 omap_sram_suspend(arg0, arg1);
342 * If we are here, processor is woken up!
349 /* again temporarily enabling api_ck to access DSP registers */
350 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
352 /* Restore DSP domain clocks */
353 DSP_RESTORE(DSP_IDLECT2);
356 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
359 if (!(cpu_is_omap15xx()))
360 ARM_RESTORE(ARM_IDLECT3);
361 ARM_RESTORE(ARM_CKCTL);
362 ARM_RESTORE(ARM_EWUPCT);
363 ARM_RESTORE(ARM_RSTCT1);
364 ARM_RESTORE(ARM_RSTCT2);
365 ARM_RESTORE(ARM_SYSST);
366 ULPD_RESTORE(ULPD_CLOCK_CTRL);
367 ULPD_RESTORE(ULPD_STATUS_REQ);
369 if (cpu_is_omap7xx()) {
370 MPUI7XX_RESTORE(EMIFS_CONFIG);
371 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
372 MPUI7XX_RESTORE(OMAP_IH1_MIR);
373 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
374 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
375 } else if (cpu_is_omap15xx()) {
376 MPUI1510_RESTORE(MPUI_CTRL);
377 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
378 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
379 MPUI1510_RESTORE(EMIFS_CONFIG);
380 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
381 MPUI1510_RESTORE(OMAP_IH1_MIR);
382 MPUI1510_RESTORE(OMAP_IH2_MIR);
383 } else if (cpu_is_omap16xx()) {
384 MPUI1610_RESTORE(MPUI_CTRL);
385 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
386 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
387 MPUI1610_RESTORE(EMIFS_CONFIG);
388 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
390 MPUI1610_RESTORE(OMAP_IH1_MIR);
391 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
392 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
393 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
394 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
397 if (!cpu_is_omap15xx())
398 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
401 * Re-enable interrupts
407 omap_serial_wake_trigger(0);
409 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
413 #ifdef CONFIG_DEBUG_FS
415 * Read system PM registers for debugging
417 static int omap_pm_debug_show(struct seq_file *m, void *v)
420 ARM_SAVE(ARM_IDLECT1);
421 ARM_SAVE(ARM_IDLECT2);
422 if (!(cpu_is_omap15xx()))
423 ARM_SAVE(ARM_IDLECT3);
424 ARM_SAVE(ARM_EWUPCT);
425 ARM_SAVE(ARM_RSTCT1);
426 ARM_SAVE(ARM_RSTCT2);
429 ULPD_SAVE(ULPD_IT_STATUS);
430 ULPD_SAVE(ULPD_CLOCK_CTRL);
431 ULPD_SAVE(ULPD_SOFT_REQ);
432 ULPD_SAVE(ULPD_STATUS_REQ);
433 ULPD_SAVE(ULPD_DPLL_CTRL);
434 ULPD_SAVE(ULPD_POWER_CTRL);
436 if (cpu_is_omap7xx()) {
437 MPUI7XX_SAVE(MPUI_CTRL);
438 MPUI7XX_SAVE(MPUI_DSP_STATUS);
439 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
440 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
441 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
442 MPUI7XX_SAVE(EMIFS_CONFIG);
443 } else if (cpu_is_omap15xx()) {
444 MPUI1510_SAVE(MPUI_CTRL);
445 MPUI1510_SAVE(MPUI_DSP_STATUS);
446 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
447 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
448 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
449 MPUI1510_SAVE(EMIFS_CONFIG);
450 } else if (cpu_is_omap16xx()) {
451 MPUI1610_SAVE(MPUI_CTRL);
452 MPUI1610_SAVE(MPUI_DSP_STATUS);
453 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
454 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
455 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
456 MPUI1610_SAVE(EMIFS_CONFIG);
460 "ARM_CKCTL_REG: 0x%-8x \n"
461 "ARM_IDLECT1_REG: 0x%-8x \n"
462 "ARM_IDLECT2_REG: 0x%-8x \n"
463 "ARM_IDLECT3_REG: 0x%-8x \n"
464 "ARM_EWUPCT_REG: 0x%-8x \n"
465 "ARM_RSTCT1_REG: 0x%-8x \n"
466 "ARM_RSTCT2_REG: 0x%-8x \n"
467 "ARM_SYSST_REG: 0x%-8x \n"
468 "ULPD_IT_STATUS_REG: 0x%-4x \n"
469 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
470 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
471 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
472 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
473 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
475 ARM_SHOW(ARM_IDLECT1),
476 ARM_SHOW(ARM_IDLECT2),
477 ARM_SHOW(ARM_IDLECT3),
478 ARM_SHOW(ARM_EWUPCT),
479 ARM_SHOW(ARM_RSTCT1),
480 ARM_SHOW(ARM_RSTCT2),
482 ULPD_SHOW(ULPD_IT_STATUS),
483 ULPD_SHOW(ULPD_CLOCK_CTRL),
484 ULPD_SHOW(ULPD_SOFT_REQ),
485 ULPD_SHOW(ULPD_DPLL_CTRL),
486 ULPD_SHOW(ULPD_STATUS_REQ),
487 ULPD_SHOW(ULPD_POWER_CTRL));
489 if (cpu_is_omap7xx()) {
491 "MPUI7XX_CTRL_REG 0x%-8x \n"
492 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
493 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
494 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
495 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
496 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
497 MPUI7XX_SHOW(MPUI_CTRL),
498 MPUI7XX_SHOW(MPUI_DSP_STATUS),
499 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
500 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
501 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
502 MPUI7XX_SHOW(EMIFS_CONFIG));
503 } else if (cpu_is_omap15xx()) {
505 "MPUI1510_CTRL_REG 0x%-8x \n"
506 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
507 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
508 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
509 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
510 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
511 MPUI1510_SHOW(MPUI_CTRL),
512 MPUI1510_SHOW(MPUI_DSP_STATUS),
513 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
514 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
515 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
516 MPUI1510_SHOW(EMIFS_CONFIG));
517 } else if (cpu_is_omap16xx()) {
519 "MPUI1610_CTRL_REG 0x%-8x \n"
520 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
521 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
522 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
523 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
524 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
525 MPUI1610_SHOW(MPUI_CTRL),
526 MPUI1610_SHOW(MPUI_DSP_STATUS),
527 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
528 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
529 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
530 MPUI1610_SHOW(EMIFS_CONFIG));
536 DEFINE_SHOW_ATTRIBUTE(omap_pm_debug);
538 static void omap_pm_init_debugfs(void)
542 d = debugfs_create_dir("pm_debug", NULL);
543 debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, d, NULL,
544 &omap_pm_debug_fops);
547 #endif /* CONFIG_DEBUG_FS */
550 * omap_pm_prepare - Do preliminary suspend work.
553 static int omap_pm_prepare(void)
555 /* We cannot sleep in idle until we have resumed */
556 cpu_idle_poll_ctrl(true);
562 * omap_pm_enter - Actually enter a sleep state.
563 * @state: State we're entering.
567 static int omap_pm_enter(suspend_state_t state)
583 * omap_pm_finish - Finish up suspend sequence.
585 * This is called after we wake back up (or if entering the sleep state
589 static void omap_pm_finish(void)
591 cpu_idle_poll_ctrl(false);
595 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
602 static const struct platform_suspend_ops omap_pm_ops = {
603 .prepare = omap_pm_prepare,
604 .enter = omap_pm_enter,
605 .finish = omap_pm_finish,
606 .valid = suspend_valid_only_mem,
609 static int __init omap_pm_init(void)
614 if (!cpu_class_is_omap1())
617 pr_info("Power Management for TI OMAP.\n");
619 if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
620 pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
622 if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
623 pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
625 if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
626 IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
628 pr_info("OMAP1 PM: sleep states in idle enabled\n");
629 enable_dyn_sleep = 1;
633 * We copy the assembler sleep/wakeup routines to SRAM.
634 * These routines need to be in SRAM as that's the only
635 * memory the MPU can see when it wakes up.
637 if (cpu_is_omap7xx()) {
638 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
639 omap7xx_cpu_suspend_sz);
640 } else if (cpu_is_omap15xx()) {
641 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
642 omap1510_cpu_suspend_sz);
643 } else if (cpu_is_omap16xx()) {
644 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
645 omap1610_cpu_suspend_sz);
648 if (omap_sram_suspend == NULL) {
649 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
653 arm_pm_idle = omap1_pm_idle;
655 if (cpu_is_omap7xx())
656 irq = INT_7XX_WAKE_UP_REQ;
657 else if (cpu_is_omap16xx())
658 irq = INT_1610_WAKE_UP_REQ;
663 if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
664 pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
667 /* Program new power ramp-up time
668 * (0 for most boards since we don't lower voltage when in deep sleep)
670 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
672 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
673 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
675 /* Configure IDLECT3 */
676 if (cpu_is_omap7xx())
677 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
678 else if (cpu_is_omap16xx())
679 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
681 suspend_set_ops(&omap_pm_ops);
683 #ifdef CONFIG_DEBUG_FS
684 omap_pm_init_debugfs();
687 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
689 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
691 if (cpu_is_omap16xx()) {
692 /* configure LOW_PWR pin */
693 omap_cfg_reg(T20_1610_LOW_PWR);
698 __initcall(omap_pm_init);