1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2012 Linaro Ltd.
8 #include <linux/clk/mxs.h>
9 #include <linux/clkdev.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/gpio.h>
13 #include <linux/init.h>
14 #include <linux/irqchip/mxs.h>
15 #include <linux/reboot.h>
16 #include <linux/micrel_phy.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/phy.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/sys_soc.h>
22 #include <asm/mach/arch.h>
23 #include <asm/mach/map.h>
24 #include <asm/mach/time.h>
25 #include <asm/system_info.h>
26 #include <asm/system_misc.h>
30 /* MXS DIGCTL SAIF CLKMUX */
31 #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
32 #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
33 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
34 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
36 #define HW_DIGCTL_CHIPID 0x310
37 #define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
38 #define HW_DIGCTL_REV_MASK 0xff
39 #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
40 #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
42 #define MXS_CHIP_REVISION_1_0 0x10
43 #define MXS_CHIP_REVISION_1_1 0x11
44 #define MXS_CHIP_REVISION_1_2 0x12
45 #define MXS_CHIP_REVISION_1_3 0x13
46 #define MXS_CHIP_REVISION_1_4 0x14
47 #define MXS_CHIP_REV_UNKNOWN 0xff
49 #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
51 #define MXS_SET_ADDR 0x4
52 #define MXS_CLR_ADDR 0x8
53 #define MXS_TOG_ADDR 0xc
55 #define HW_OCOTP_OPS2 19 /* offset 0x150 */
56 #define HW_OCOTP_OPS3 20 /* offset 0x160 */
61 static void __iomem *reset_addr;
63 static inline void __mxs_setl(u32 mask, void __iomem *reg)
65 __raw_writel(mask, reg + MXS_SET_ADDR);
68 static inline void __mxs_clrl(u32 mask, void __iomem *reg)
70 __raw_writel(mask, reg + MXS_CLR_ADDR);
73 static inline void __mxs_togl(u32 mask, void __iomem *reg)
75 __raw_writel(mask, reg + MXS_TOG_ADDR);
78 #define OCOTP_WORD_OFFSET 0x20
79 #define OCOTP_WORD_COUNT 0x20
81 #define BM_OCOTP_CTRL_BUSY (1 << 8)
82 #define BM_OCOTP_CTRL_ERROR (1 << 9)
83 #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
85 static DEFINE_MUTEX(ocotp_mutex);
86 static u32 ocotp_words[OCOTP_WORD_COUNT];
88 static const u32 *mxs_get_ocotp(void)
90 struct device_node *np;
91 void __iomem *ocotp_base;
99 np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
100 ocotp_base = of_iomap(np, 0);
101 WARN_ON(!ocotp_base);
103 mutex_lock(&ocotp_mutex);
106 * clk_enable(hbus_clk) for ocotp can be skipped
107 * as it must be on when system is running.
110 /* try to clear ERROR bit */
111 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
113 /* check both BUSY and ERROR cleared */
114 while ((__raw_readl(ocotp_base) &
115 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
118 if (unlikely(!timeout))
121 /* open OCOTP banks for read */
122 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
124 /* approximately wait 32 hclk cycles */
127 /* poll BUSY bit becoming cleared */
129 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
132 if (unlikely(!timeout))
135 for (i = 0; i < OCOTP_WORD_COUNT; i++)
136 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
139 /* close banks for power saving */
140 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
144 mutex_unlock(&ocotp_mutex);
149 mutex_unlock(&ocotp_mutex);
150 pr_err("%s: timeout in reading OCOTP\n", __func__);
162 static void __init update_fec_mac_prop(enum mac_oui oui)
164 struct device_node *np, *from = NULL;
165 struct property *newmac;
166 const u32 *ocotp = mxs_get_ocotp();
171 for (i = 0; i < 2; i++) {
172 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
178 if (of_get_property(np, "local-mac-address", NULL))
181 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
184 newmac->value = newmac + 1;
187 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
194 * OCOTP only stores the last 4 octets for each mac address,
195 * so hard-code OUI here.
197 macaddr = newmac->value;
209 case OUI_CRYSTALFONTZ:
226 macaddr[3] = (val >> 16) & 0xff;
227 macaddr[4] = (val >> 8) & 0xff;
228 macaddr[5] = (val >> 0) & 0xff;
230 of_update_property(np, newmac);
234 static inline void enable_clk_enet_out(void)
236 struct clk *clk = clk_get_sys("enet_out", NULL);
239 clk_prepare_enable(clk);
242 static void __init imx28_evk_init(void)
244 update_fec_mac_prop(OUI_FSL);
246 mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
249 static void __init imx28_apf28_init(void)
251 update_fec_mac_prop(OUI_ARMADEUS);
254 static int apx4devkit_phy_fixup(struct phy_device *phy)
256 phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
260 static void __init apx4devkit_init(void)
262 enable_clk_enet_out();
264 if (IS_BUILTIN(CONFIG_PHYLIB))
265 phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
266 apx4devkit_phy_fixup);
269 static void __init crystalfontz_init(void)
271 update_fec_mac_prop(OUI_CRYSTALFONTZ);
274 static void __init duckbill_init(void)
276 update_fec_mac_prop(OUI_I2SE);
279 static void __init m28cu3_init(void)
281 update_fec_mac_prop(OUI_DENX);
284 static const char __init *mxs_get_soc_id(void)
286 struct device_node *np;
287 void __iomem *digctl_base;
289 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
290 digctl_base = of_iomap(np, 0);
291 WARN_ON(!digctl_base);
293 chipid = readl(digctl_base + HW_DIGCTL_CHIPID);
294 socid = chipid & HW_DIGCTL_CHIPID_MASK;
296 iounmap(digctl_base);
300 case HW_DIGCTL_CHIPID_MX23:
302 case HW_DIGCTL_CHIPID_MX28:
309 static u32 __init mxs_get_cpu_rev(void)
311 u32 rev = chipid & HW_DIGCTL_REV_MASK;
314 case HW_DIGCTL_CHIPID_MX23:
317 return MXS_CHIP_REVISION_1_0;
319 return MXS_CHIP_REVISION_1_1;
321 return MXS_CHIP_REVISION_1_2;
323 return MXS_CHIP_REVISION_1_3;
325 return MXS_CHIP_REVISION_1_4;
327 return MXS_CHIP_REV_UNKNOWN;
329 case HW_DIGCTL_CHIPID_MX28:
332 return MXS_CHIP_REVISION_1_1;
334 return MXS_CHIP_REVISION_1_2;
336 return MXS_CHIP_REV_UNKNOWN;
339 return MXS_CHIP_REV_UNKNOWN;
343 static const char __init *mxs_get_revision(void)
345 u32 rev = mxs_get_cpu_rev();
347 if (rev != MXS_CHIP_REV_UNKNOWN)
348 return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf,
351 return kasprintf(GFP_KERNEL, "%s", "Unknown");
354 #define MX23_CLKCTRL_RESET_OFFSET 0x120
355 #define MX28_CLKCTRL_RESET_OFFSET 0x1e0
357 static int __init mxs_restart_init(void)
359 struct device_node *np;
361 np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
362 reset_addr = of_iomap(np, 0);
366 if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
367 reset_addr += MX23_CLKCTRL_RESET_OFFSET;
369 reset_addr += MX28_CLKCTRL_RESET_OFFSET;
375 static void __init eukrea_mbmx283lc_init(void)
377 mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
380 static void __init mxs_machine_init(void)
382 struct device_node *root;
383 struct device *parent;
384 struct soc_device *soc_dev;
385 struct soc_device_attribute *soc_dev_attr;
387 const u32 *ocotp = mxs_get_ocotp();
390 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
394 root = of_find_node_by_path("/");
395 ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
401 soc_dev_attr->family = "Freescale MXS Family";
402 soc_dev_attr->soc_id = mxs_get_soc_id();
403 soc_dev_attr->revision = mxs_get_revision();
405 if (socid == HW_DIGCTL_CHIPID_MX23) {
406 soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3];
407 } else if (socid == HW_DIGCTL_CHIPID_MX28) {
408 soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2];
410 system_serial_low = ocotp[HW_OCOTP_OPS3];
411 soc_uid |= system_serial_low;
415 soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
417 soc_dev = soc_device_register(soc_dev_attr);
418 if (IS_ERR(soc_dev)) {
419 kfree(soc_dev_attr->serial_number);
420 kfree(soc_dev_attr->revision);
425 parent = soc_device_to_device(soc_dev);
427 if (of_machine_is_compatible("fsl,imx28-evk"))
429 if (of_machine_is_compatible("armadeus,imx28-apf28"))
431 else if (of_machine_is_compatible("bluegiga,apx4devkit"))
433 else if (of_machine_is_compatible("crystalfontz,cfa10036"))
435 else if (of_machine_is_compatible("eukrea,mbmx283lc"))
436 eukrea_mbmx283lc_init();
437 else if (of_machine_is_compatible("i2se,duckbill") ||
438 of_machine_is_compatible("i2se,duckbill-2"))
440 else if (of_machine_is_compatible("msr,m28cu3"))
443 of_platform_default_populate(NULL, NULL, parent);
448 #define MXS_CLKCTRL_RESET_CHIP (1 << 1)
451 * Reset the system. It is called by machine_restart().
453 static void mxs_restart(enum reboot_mode mode, const char *cmd)
457 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
459 pr_err("Failed to assert the chip reset\n");
461 /* Delay to allow the serial port to show the message */
465 /* We'll take a jump through zero as a poor second */
469 static const char *const mxs_dt_compat[] __initconst = {
475 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
476 .handle_irq = icoll_handle_irq,
477 .init_machine = mxs_machine_init,
478 .init_late = mxs_pm_init,
479 .dt_compat = mxs_dt_compat,
480 .restart = mxs_restart,