1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Marvell
5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
6 * Gregory Clement <gregory.clement@free-electrons.com>
9 #include <linux/linkage.h>
10 #include <asm/assembler.h>
13 ENTRY(armada_38x_scu_power_up)
14 mrc p15, 4, r1, c15, c0 @ get SCU base address
15 orr r1, r1, #0x8 @ SCU CPU Power Status Register
16 mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
20 strb r0, [r1] @ switch SCU power state to Normal mode
22 ENDPROC(armada_38x_scu_power_up)
25 * This is the entry point through which CPUs exiting cpuidle deep
26 * idle state are going.
28 ENTRY(armada_370_xp_cpu_resume)
29 ARM_BE8(setend be ) @ go BE8 if entered LE
31 * Disable the MMU that might have been enabled in BootROM if
32 * this code is used in the resume path of a suspend/resume
35 mrc p15, 0, r1, c1, c0, 0
37 mcr p15, 0, r1, c1, c0, 0
38 bl ll_add_cpu_to_smp_group
39 bl ll_enable_coherency
41 ENDPROC(armada_370_xp_cpu_resume)
43 ENTRY(armada_38x_cpu_resume)
44 /* do we need it for Armada 38x*/
45 ARM_BE8(setend be ) @ go BE8 if entered LE
47 bl armada_38x_scu_power_up
49 ENDPROC(armada_38x_cpu_resume)
51 .global mvebu_boot_wa_start
52 .global mvebu_boot_wa_end
54 /* The following code will be executed from SRAM */
55 ENTRY(mvebu_boot_wa_start)
58 ldr r0, [r0] @ load the address of the
60 ldr r0, [r0] @ load the value in the
62 ARM_BE8(rev r0, r0) @ the value is stored LE
63 mov pc, r0 @ jump to this value
65 * the last word of this piece of code will be filled by the physical
66 * address of the boot address register just after being copied in SRAM
71 ENDPROC(mvebu_boot_wa_end)