1 // SPDX-License-Identifier: GPL-2.0-only
3 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
6 * Copyright (C) 2012 Marvell
8 * Yehuda Yitschak <yehuday@marvell.com>
9 * Gregory Clement <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
13 * responsible for ensuring hardware coherency between all CPUs and between
14 * CPUs and I/O masters. This file initializes the coherency fabric and
15 * supplies basic routines for configuring and controlling hardware coherency
18 #define pr_fmt(fmt) "mvebu-coherency: " fmt
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/of_address.h>
24 #include <linux/smp.h>
25 #include <linux/dma-map-ops.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/mbus.h>
29 #include <linux/pci.h>
30 #include <asm/smp_plat.h>
31 #include <asm/cacheflush.h>
32 #include <asm/mach/map.h>
33 #include <asm/dma-mapping.h>
34 #include "coherency.h"
35 #include "mvebu-soc-id.h"
37 unsigned long coherency_phys_base;
38 void __iomem *coherency_base;
39 static void __iomem *coherency_cpu_base;
40 static void __iomem *cpu_config_base;
42 /* Coherency fabric registers */
43 #define IO_SYNC_BARRIER_CTL_OFFSET 0x0
46 COHERENCY_FABRIC_TYPE_NONE,
47 COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
48 COHERENCY_FABRIC_TYPE_ARMADA_375,
49 COHERENCY_FABRIC_TYPE_ARMADA_380,
52 static const struct of_device_id of_coherency_table[] = {
53 {.compatible = "marvell,coherency-fabric",
54 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
55 {.compatible = "marvell,armada-375-coherency-fabric",
56 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
57 {.compatible = "marvell,armada-380-coherency-fabric",
58 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
59 { /* end of list */ },
62 /* Functions defined in coherency_ll.S */
63 int ll_enable_coherency(void);
64 void ll_add_cpu_to_smp_group(void);
66 #define CPU_CONFIG_SHARED_L2 BIT(16)
69 * Disable the "Shared L2 Present" bit in CPU Configuration register
72 * The "Shared L2 Present" bit affects the "level of coherence" value
73 * in the clidr CP15 register. Cache operation functions such as
74 * "flush all" and "invalidate all" operate on all the cache levels
75 * that included in the defined level of coherence. When HW I/O
76 * coherency is used, this bit causes unnecessary flushes of the L2
79 static void armada_xp_clear_shared_l2(void)
86 reg = readl(cpu_config_base);
87 reg &= ~CPU_CONFIG_SHARED_L2;
88 writel(reg, cpu_config_base);
91 static int mvebu_hwcc_notifier(struct notifier_block *nb,
92 unsigned long event, void *__dev)
94 struct device *dev = __dev;
96 if (event != BUS_NOTIFY_ADD_DEVICE)
98 dev->dma_coherent = true;
103 static struct notifier_block mvebu_hwcc_nb = {
104 .notifier_call = mvebu_hwcc_notifier,
107 static struct notifier_block mvebu_hwcc_pci_nb __maybe_unused = {
108 .notifier_call = mvebu_hwcc_notifier,
111 static int armada_xp_clear_l2_starting(unsigned int cpu)
113 armada_xp_clear_shared_l2();
117 static void __init armada_370_coherency_init(struct device_node *np)
120 struct device_node *cpu_config_np;
122 of_address_to_resource(np, 0, &res);
123 coherency_phys_base = res.start;
125 * Ensure secondary CPUs will see the updated value,
126 * which they read before they join the coherency
127 * fabric, and therefore before they are coherent with
128 * the boot CPU cache.
130 sync_cache_w(&coherency_phys_base);
131 coherency_base = of_iomap(np, 0);
132 coherency_cpu_base = of_iomap(np, 1);
134 cpu_config_np = of_find_compatible_node(NULL, NULL,
135 "marvell,armada-xp-cpu-config");
139 cpu_config_base = of_iomap(cpu_config_np, 0);
140 if (!cpu_config_base) {
141 of_node_put(cpu_config_np);
145 of_node_put(cpu_config_np);
147 cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY,
148 "arm/mvebu/coherency:starting",
149 armada_xp_clear_l2_starting, NULL);
155 * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
156 * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
157 * needed for the HW I/O coherency mechanism to work properly without
160 static void __iomem *
161 armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
162 unsigned int mtype, void *caller)
165 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
168 static void __init armada_375_380_coherency_init(struct device_node *np)
170 struct device_node *cache_dn;
172 coherency_cpu_base = of_iomap(np, 0);
173 arch_ioremap_caller = armada_wa_ioremap_caller;
174 pci_ioremap_set_mem_type(MT_UNCACHED);
177 * We should switch the PL310 to I/O coherency mode only if
178 * I/O coherency is actually enabled.
180 if (!coherency_available())
184 * Add the PL310 property "arm,io-coherent". This makes sure the
185 * outer sync operation is not used, which allows to
186 * workaround the system erratum that causes deadlocks when
187 * doing PCIe in an SMP situation on Armada 375 and Armada
190 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
193 p = kzalloc(sizeof(*p), GFP_KERNEL);
194 p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
195 of_add_property(cache_dn, p);
199 static int coherency_type(void)
201 struct device_node *np;
202 const struct of_device_id *match;
206 * The coherency fabric is needed:
207 * - For coherency between processors on Armada XP, so only
208 * when SMP is enabled.
209 * - For coherency between the processor and I/O devices, but
210 * this coherency requires many pre-requisites (write
211 * allocate cache policy, shareable pages, SMP bit set) that
212 * are only meant in SMP situations.
214 * Note that this means that on Armada 370, there is currently
215 * no way to use hardware I/O coherency, because even when
216 * CONFIG_SMP is enabled, is_smp() returns false due to the
217 * Armada 370 being a single-core processor. To lift this
218 * limitation, we would have to find a way to make the cache
219 * policy set to write-allocate (on all Armada SoCs), and to
220 * set the shareable attribute in page tables (on all Armada
221 * SoCs except the Armada 370). Unfortunately, such decisions
222 * are taken very early in the kernel boot process, at a point
223 * where we don't know yet on which SoC we are running.
227 return COHERENCY_FABRIC_TYPE_NONE;
229 np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
231 return COHERENCY_FABRIC_TYPE_NONE;
233 type = (int) match->data;
240 int set_cpu_coherent(void)
242 int type = coherency_type();
244 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
245 if (!coherency_base) {
246 pr_warn("Can't make current CPU cache coherent.\n");
247 pr_warn("Coherency fabric is not initialized\n");
251 armada_xp_clear_shared_l2();
252 ll_add_cpu_to_smp_group();
253 return ll_enable_coherency();
259 int coherency_available(void)
261 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
264 int __init coherency_init(void)
266 int type = coherency_type();
267 struct device_node *np;
269 np = of_find_matching_node(NULL, of_coherency_table);
271 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
272 armada_370_coherency_init(np);
273 else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
274 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
275 armada_375_380_coherency_init(np);
282 static int __init coherency_late_init(void)
284 if (coherency_available())
285 bus_register_notifier(&platform_bus_type,
290 postcore_initcall(coherency_late_init);
292 #if IS_ENABLED(CONFIG_PCI)
293 static int __init coherency_pci_init(void)
295 if (coherency_available())
296 bus_register_notifier(&pci_bus_type,
301 arch_initcall(coherency_pci_init);