2 * arch/arm/mach-mv78xx0/common.c
4 * Core functions for Marvell MV78xx0 SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/serial_8250.h>
16 #include <linux/ata_platform.h>
17 #include <linux/clk-provider.h>
18 #include <linux/ethtool.h>
19 #include <asm/hardware/cache-feroceon-l2.h>
20 #include <asm/mach/map.h>
21 #include <asm/mach/time.h>
22 #include <linux/platform_data/usb-ehci-orion.h>
23 #include <linux/platform_data/mtd-orion_nand.h>
24 #include <plat/time.h>
25 #include <plat/common.h>
26 #include <plat/addr-map.h>
28 #include "bridge-regs.h"
31 static int get_tclk(void);
33 /*****************************************************************************
35 ****************************************************************************/
36 int mv78xx0_core_index(void)
41 * Read Extra Features register.
43 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
45 return !!(extra & 0x00004000);
48 static int get_hclk(void)
53 * HCLK tick rate is configured by DEV_D[7:5] pins.
55 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
72 panic("unknown HCLK PLL setting: %.8x\n",
73 readl(SAMPLE_AT_RESET_LOW));
79 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
84 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
85 * PCLK/L2CLK by bits [19:14].
87 if (core_index == 0) {
88 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
90 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
94 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
95 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
97 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
100 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
103 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
106 static int get_tclk(void)
111 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
113 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
115 tclk_freq = 166666667;
118 tclk_freq = 200000000;
121 panic("unknown TCLK PLL setting: %.8x\n",
122 readl(SAMPLE_AT_RESET_HIGH));
129 /*****************************************************************************
130 * I/O Address Mapping
131 ****************************************************************************/
132 static struct map_desc mv78xx0_io_desc[] __initdata = {
134 .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
136 .length = MV78XX0_CORE_REGS_SIZE,
139 .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
140 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
141 .length = MV78XX0_REGS_SIZE,
146 void __init mv78xx0_map_io(void)
151 * Map the right set of per-core registers depending on
152 * which core we are running on.
154 if (mv78xx0_core_index() == 0) {
155 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
157 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
159 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
161 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
165 /*****************************************************************************
167 ****************************************************************************/
168 static struct clk *tclk;
170 static void __init clk_init(void)
172 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk());
174 orion_clkdev_init(tclk);
177 /*****************************************************************************
179 ****************************************************************************/
180 void __init mv78xx0_ehci0_init(void)
182 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
186 /*****************************************************************************
188 ****************************************************************************/
189 void __init mv78xx0_ehci1_init(void)
191 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
195 /*****************************************************************************
197 ****************************************************************************/
198 void __init mv78xx0_ehci2_init(void)
200 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
204 /*****************************************************************************
206 ****************************************************************************/
207 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
209 orion_ge00_init(eth_data,
210 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
212 MV643XX_TX_CSUM_DEFAULT_LIMIT);
216 /*****************************************************************************
218 ****************************************************************************/
219 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
221 orion_ge01_init(eth_data,
222 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
223 MV643XX_TX_CSUM_DEFAULT_LIMIT);
227 /*****************************************************************************
229 ****************************************************************************/
230 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
235 * On the Z0, ge10 and ge11 are internally connected back
236 * to back, and not brought out.
238 mv78xx0_pcie_id(&dev, &rev);
239 if (dev == MV78X00_Z0_DEV_ID) {
240 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
241 eth_data->speed = SPEED_1000;
242 eth_data->duplex = DUPLEX_FULL;
245 orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM);
249 /*****************************************************************************
251 ****************************************************************************/
252 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
257 * On the Z0, ge10 and ge11 are internally connected back
258 * to back, and not brought out.
260 mv78xx0_pcie_id(&dev, &rev);
261 if (dev == MV78X00_Z0_DEV_ID) {
262 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
263 eth_data->speed = SPEED_1000;
264 eth_data->duplex = DUPLEX_FULL;
267 orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM);
270 /*****************************************************************************
272 ****************************************************************************/
273 void __init mv78xx0_i2c_init(void)
275 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
276 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
279 /*****************************************************************************
281 ****************************************************************************/
282 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
284 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
288 /*****************************************************************************
290 ****************************************************************************/
291 void __init mv78xx0_uart0_init(void)
293 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
294 IRQ_MV78XX0_UART_0, tclk);
298 /*****************************************************************************
300 ****************************************************************************/
301 void __init mv78xx0_uart1_init(void)
303 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
304 IRQ_MV78XX0_UART_1, tclk);
308 /*****************************************************************************
310 ****************************************************************************/
311 void __init mv78xx0_uart2_init(void)
313 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
314 IRQ_MV78XX0_UART_2, tclk);
317 /*****************************************************************************
319 ****************************************************************************/
320 void __init mv78xx0_uart3_init(void)
322 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
323 IRQ_MV78XX0_UART_3, tclk);
326 /*****************************************************************************
328 ****************************************************************************/
329 void __init mv78xx0_init_early(void)
331 orion_time_set_base(TIMER_VIRT_BASE);
332 if (mv78xx0_core_index() == 0)
333 mvebu_mbus_init("marvell,mv78xx0-mbus",
334 BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
335 DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
337 mvebu_mbus_init("marvell,mv78xx0-mbus",
338 BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
339 DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
342 void __ref mv78xx0_timer_init(void)
344 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
345 IRQ_MV78XX0_TIMER_1, get_tclk());
349 /*****************************************************************************
351 ****************************************************************************/
352 static char * __init mv78xx0_id(void)
356 mv78xx0_pcie_id(&dev, &rev);
358 if (dev == MV78X00_Z0_DEV_ID) {
359 if (rev == MV78X00_REV_Z0)
362 return "MV78X00-Rev-Unsupported";
363 } else if (dev == MV78100_DEV_ID) {
364 if (rev == MV78100_REV_A0)
366 else if (rev == MV78100_REV_A1)
369 return "MV78100-Rev-Unsupported";
370 } else if (dev == MV78200_DEV_ID) {
371 if (rev == MV78100_REV_A0)
374 return "MV78200-Rev-Unsupported";
376 return "Device-Unknown";
380 static int __init is_l2_writethrough(void)
382 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
385 void __init mv78xx0_init(void)
392 core_index = mv78xx0_core_index();
394 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
396 printk(KERN_INFO "%s ", mv78xx0_id());
397 printk("core #%d, ", core_index);
398 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
399 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
400 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
401 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
403 if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2))
404 feroceon_l2_init(is_l2_writethrough());
406 /* Setup root of clk tree */
410 void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
413 * Enable soft reset to assert RSTOUTn.
415 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
420 writel(SOFT_RESET, SYSTEM_SOFT_RESET);