1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78xx0/common.c
5 * Core functions for Marvell MV78xx0 SoCs
8 #include <linux/kernel.h>
9 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/serial_8250.h>
13 #include <linux/ata_platform.h>
14 #include <linux/clk-provider.h>
15 #include <linux/ethtool.h>
16 #include <asm/hardware/cache-feroceon-l2.h>
17 #include <asm/mach/map.h>
18 #include <asm/mach/time.h>
19 #include <linux/platform_data/usb-ehci-orion.h>
20 #include <linux/platform_data/mtd-orion_nand.h>
21 #include <plat/time.h>
22 #include <plat/common.h>
23 #include <plat/addr-map.h>
25 #include "bridge-regs.h"
28 static int get_tclk(void);
30 /*****************************************************************************
32 ****************************************************************************/
33 int mv78xx0_core_index(void)
38 * Read Extra Features register.
40 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
42 return !!(extra & 0x00004000);
45 static int get_hclk(void)
50 * HCLK tick rate is configured by DEV_D[7:5] pins.
52 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
69 panic("unknown HCLK PLL setting: %.8x\n",
70 readl(SAMPLE_AT_RESET_LOW));
76 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
81 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
82 * PCLK/L2CLK by bits [19:14].
84 if (core_index == 0) {
85 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
91 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
92 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
94 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
97 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
100 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
103 static int get_tclk(void)
108 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
110 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
112 tclk_freq = 166666667;
115 tclk_freq = 200000000;
118 panic("unknown TCLK PLL setting: %.8x\n",
119 readl(SAMPLE_AT_RESET_HIGH));
126 /*****************************************************************************
127 * I/O Address Mapping
128 ****************************************************************************/
129 static struct map_desc mv78xx0_io_desc[] __initdata = {
131 .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
133 .length = MV78XX0_CORE_REGS_SIZE,
136 .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
137 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
138 .length = MV78XX0_REGS_SIZE,
143 void __init mv78xx0_map_io(void)
148 * Map the right set of per-core registers depending on
149 * which core we are running on.
151 if (mv78xx0_core_index() == 0) {
152 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
154 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
156 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
158 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
162 /*****************************************************************************
164 ****************************************************************************/
165 static struct clk *tclk;
167 static void __init clk_init(void)
169 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk());
171 orion_clkdev_init(tclk);
174 /*****************************************************************************
176 ****************************************************************************/
177 void __init mv78xx0_ehci0_init(void)
179 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
183 /*****************************************************************************
185 ****************************************************************************/
186 void __init mv78xx0_ehci1_init(void)
188 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
192 /*****************************************************************************
194 ****************************************************************************/
195 void __init mv78xx0_ehci2_init(void)
197 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
201 /*****************************************************************************
203 ****************************************************************************/
204 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
206 orion_ge00_init(eth_data,
207 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
209 MV643XX_TX_CSUM_DEFAULT_LIMIT);
213 /*****************************************************************************
215 ****************************************************************************/
216 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
218 orion_ge01_init(eth_data,
219 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
220 MV643XX_TX_CSUM_DEFAULT_LIMIT);
224 /*****************************************************************************
226 ****************************************************************************/
227 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
232 * On the Z0, ge10 and ge11 are internally connected back
233 * to back, and not brought out.
235 mv78xx0_pcie_id(&dev, &rev);
236 if (dev == MV78X00_Z0_DEV_ID) {
237 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
238 eth_data->speed = SPEED_1000;
239 eth_data->duplex = DUPLEX_FULL;
242 orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM);
246 /*****************************************************************************
248 ****************************************************************************/
249 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
254 * On the Z0, ge10 and ge11 are internally connected back
255 * to back, and not brought out.
257 mv78xx0_pcie_id(&dev, &rev);
258 if (dev == MV78X00_Z0_DEV_ID) {
259 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
260 eth_data->speed = SPEED_1000;
261 eth_data->duplex = DUPLEX_FULL;
264 orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM);
267 /*****************************************************************************
269 ****************************************************************************/
270 void __init mv78xx0_i2c_init(void)
272 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
273 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
276 /*****************************************************************************
278 ****************************************************************************/
279 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
281 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
285 /*****************************************************************************
287 ****************************************************************************/
288 void __init mv78xx0_uart0_init(void)
290 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
291 IRQ_MV78XX0_UART_0, tclk);
295 /*****************************************************************************
297 ****************************************************************************/
298 void __init mv78xx0_uart1_init(void)
300 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
301 IRQ_MV78XX0_UART_1, tclk);
305 /*****************************************************************************
307 ****************************************************************************/
308 void __init mv78xx0_uart2_init(void)
310 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
311 IRQ_MV78XX0_UART_2, tclk);
314 /*****************************************************************************
316 ****************************************************************************/
317 void __init mv78xx0_uart3_init(void)
319 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
320 IRQ_MV78XX0_UART_3, tclk);
323 /*****************************************************************************
325 ****************************************************************************/
326 void __init mv78xx0_init_early(void)
328 orion_time_set_base(TIMER_VIRT_BASE);
329 if (mv78xx0_core_index() == 0)
330 mvebu_mbus_init("marvell,mv78xx0-mbus",
331 BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
332 DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
334 mvebu_mbus_init("marvell,mv78xx0-mbus",
335 BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
336 DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
339 void __ref mv78xx0_timer_init(void)
341 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
342 IRQ_MV78XX0_TIMER_1, get_tclk());
346 /*****************************************************************************
348 ****************************************************************************/
349 static char * __init mv78xx0_id(void)
353 mv78xx0_pcie_id(&dev, &rev);
355 if (dev == MV78X00_Z0_DEV_ID) {
356 if (rev == MV78X00_REV_Z0)
359 return "MV78X00-Rev-Unsupported";
360 } else if (dev == MV78100_DEV_ID) {
361 if (rev == MV78100_REV_A0)
363 else if (rev == MV78100_REV_A1)
366 return "MV78100-Rev-Unsupported";
367 } else if (dev == MV78200_DEV_ID) {
368 if (rev == MV78100_REV_A0)
371 return "MV78200-Rev-Unsupported";
373 return "Device-Unknown";
377 static int __init is_l2_writethrough(void)
379 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
382 void __init mv78xx0_init(void)
389 core_index = mv78xx0_core_index();
391 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
393 printk(KERN_INFO "%s ", mv78xx0_id());
394 printk("core #%d, ", core_index);
395 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
396 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
397 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
398 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
400 if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2))
401 feroceon_l2_init(is_l2_writethrough());
403 /* Setup root of clk tree */
407 void mv78xx0_restart(enum reboot_mode mode, const char *cmd)
410 * Enable soft reset to assert RSTOUTn.
412 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
417 writel(SOFT_RESET, SYSTEM_SOFT_RESET);