1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/time.c
5 * Support for clocksource and clockevents
7 * Copyright (C) 2008 Marvell International Ltd.
10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
11 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
13 * The timers module actually includes three timers, each timer with up to
14 * three match comparators. Timer #0 is used here in free-running mode as
15 * the clock source, and match comparator #1 used as clock event device.
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/clockchips.h>
22 #include <linux/clk.h>
25 #include <linux/irq.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/sched_clock.h>
30 #include <asm/mach/time.h>
33 #include "regs-timers.h"
34 #include "regs-apbc.h"
39 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
41 #define MAX_DELTA (0xfffffffe)
42 #define MIN_DELTA (16)
44 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
47 * Read the timer through the CVWR register. Delay is required after requesting
48 * a read. The CR register cannot be directly read due to metastability issues
49 * documented in the PXA168 software manual.
51 static inline uint32_t timer_read(void)
56 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
59 val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
64 static u64 notrace mmp_read_sched_clock(void)
69 static irqreturn_t timer_interrupt(int irq, void *dev_id)
71 struct clock_event_device *c = dev_id;
74 * Clear pending interrupt status.
76 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
81 __raw_writel(0x02, mmp_timer_base + TMR_CER);
88 static int timer_set_next_event(unsigned long delta,
89 struct clock_event_device *dev)
93 local_irq_save(flags);
98 __raw_writel(0x02, mmp_timer_base + TMR_CER);
101 * Clear and enable timer match 0 interrupt.
103 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
104 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
107 * Setup new clockevent timer value.
109 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
114 __raw_writel(0x03, mmp_timer_base + TMR_CER);
116 local_irq_restore(flags);
121 static int timer_set_shutdown(struct clock_event_device *evt)
125 local_irq_save(flags);
126 /* disable the matching interrupt */
127 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
128 local_irq_restore(flags);
133 static struct clock_event_device ckevt = {
134 .name = "clockevent",
135 .features = CLOCK_EVT_FEAT_ONESHOT,
137 .set_next_event = timer_set_next_event,
138 .set_state_shutdown = timer_set_shutdown,
139 .set_state_oneshot = timer_set_shutdown,
142 static u64 clksrc_read(struct clocksource *cs)
147 static struct clocksource cksrc = {
148 .name = "clocksource",
151 .mask = CLOCKSOURCE_MASK(32),
152 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
155 static void __init timer_config(void)
157 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
159 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
161 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
162 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
163 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
165 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
166 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
168 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
169 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
170 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
172 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
173 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
174 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
176 /* enable timer 1 counter */
177 __raw_writel(0x2, mmp_timer_base + TMR_CER);
180 static struct irqaction timer_irq = {
182 .flags = IRQF_TIMER | IRQF_IRQPOLL,
183 .handler = timer_interrupt,
187 void __init mmp_timer_init(int irq, unsigned long rate)
191 sched_clock_register(mmp_read_sched_clock, 32, rate);
193 ckevt.cpumask = cpumask_of(0);
195 setup_irq(irq, &timer_irq);
197 clocksource_register_hz(&cksrc, rate);
198 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
202 static const struct of_device_id mmp_timer_dt_ids[] = {
203 { .compatible = "mrvl,mmp-timer", },
207 void __init mmp_dt_init_timer(void)
209 struct device_node *np;
214 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
220 clk = of_clk_get(np, 0);
222 ret = clk_prepare_enable(clk);
225 rate = clk_get_rate(clk) / 2;
226 } else if (cpu_is_pj4()) {
232 irq = irq_of_parse_and_map(np, 0);
237 mmp_timer_base = of_iomap(np, 0);
238 if (!mmp_timer_base) {
242 mmp_timer_init(irq, rate);
245 pr_err("Failed to get timer from device tree with error:%d\n", ret);