2 * linux/arch/arm/mach-mmp/time.c
4 * Support for clocksource and clockevents
6 * Copyright (C) 2008 Marvell International Ltd.
9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
10 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
12 * The timers module actually includes three timers, each timer with up to
13 * three match comparators. Timer #0 is used here in free-running mode as
14 * the clock source, and match comparator #1 used as clock event device.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/interrupt.h>
24 #include <linux/clockchips.h>
27 #include <linux/irq.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/sched_clock.h>
32 #include <asm/mach/time.h>
35 #include "regs-timers.h"
36 #include "regs-apbc.h"
41 #ifdef CONFIG_CPU_MMP2
42 #define MMP_CLOCK_FREQ 6500000
44 #define MMP_CLOCK_FREQ 3250000
47 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
49 #define MAX_DELTA (0xfffffffe)
50 #define MIN_DELTA (16)
52 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
55 * Read the timer through the CVWR register. Delay is required after requesting
56 * a read. The CR register cannot be directly read due to metastability issues
57 * documented in the PXA168 software manual.
59 static inline uint32_t timer_read(void)
64 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
67 val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
72 static u64 notrace mmp_read_sched_clock(void)
77 static irqreturn_t timer_interrupt(int irq, void *dev_id)
79 struct clock_event_device *c = dev_id;
82 * Clear pending interrupt status.
84 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
89 __raw_writel(0x02, mmp_timer_base + TMR_CER);
96 static int timer_set_next_event(unsigned long delta,
97 struct clock_event_device *dev)
101 local_irq_save(flags);
106 __raw_writel(0x02, mmp_timer_base + TMR_CER);
109 * Clear and enable timer match 0 interrupt.
111 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
112 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
115 * Setup new clockevent timer value.
117 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
122 __raw_writel(0x03, mmp_timer_base + TMR_CER);
124 local_irq_restore(flags);
129 static int timer_set_shutdown(struct clock_event_device *evt)
133 local_irq_save(flags);
134 /* disable the matching interrupt */
135 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
136 local_irq_restore(flags);
141 static struct clock_event_device ckevt = {
142 .name = "clockevent",
143 .features = CLOCK_EVT_FEAT_ONESHOT,
145 .set_next_event = timer_set_next_event,
146 .set_state_shutdown = timer_set_shutdown,
147 .set_state_oneshot = timer_set_shutdown,
150 static u64 clksrc_read(struct clocksource *cs)
155 static struct clocksource cksrc = {
156 .name = "clocksource",
159 .mask = CLOCKSOURCE_MASK(32),
160 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
163 static void __init timer_config(void)
165 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
167 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
169 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
170 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
171 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
173 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
174 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
176 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
177 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
178 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
180 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
181 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
182 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
184 /* enable timer 1 counter */
185 __raw_writel(0x2, mmp_timer_base + TMR_CER);
188 static struct irqaction timer_irq = {
190 .flags = IRQF_TIMER | IRQF_IRQPOLL,
191 .handler = timer_interrupt,
195 void __init timer_init(int irq)
199 sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
201 ckevt.cpumask = cpumask_of(0);
203 setup_irq(irq, &timer_irq);
205 clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
206 clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
207 MIN_DELTA, MAX_DELTA);
211 static const struct of_device_id mmp_timer_dt_ids[] = {
212 { .compatible = "mrvl,mmp-timer", },
216 void __init mmp_dt_init_timer(void)
218 struct device_node *np;
221 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
227 irq = irq_of_parse_and_map(np, 0);
232 mmp_timer_base = of_iomap(np, 0);
233 if (!mmp_timer_base) {
240 pr_err("Failed to get timer from device tree with error:%d\n", ret);