1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/time.c
5 * Support for clocksource and clockevents
7 * Copyright (C) 2008 Marvell International Ltd.
10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
11 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
13 * The timers module actually includes three timers, each timer with up to
14 * three match comparators. Timer #0 is used here in free-running mode as
15 * the clock source, and match comparator #1 used as clock event device.
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/clockchips.h>
22 #include <linux/clk.h>
25 #include <linux/irq.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/sched_clock.h>
30 #include <asm/mach/time.h>
33 #include "regs-timers.h"
34 #include "regs-apbc.h"
36 #include <linux/soc/mmp/cputype.h>
38 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
40 #define MAX_DELTA (0xfffffffe)
41 #define MIN_DELTA (16)
43 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
46 * Read the timer through the CVWR register. Delay is required after requesting
47 * a read. The CR register cannot be directly read due to metastability issues
48 * documented in the PXA168 software manual.
50 static inline uint32_t timer_read(void)
55 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
58 val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
63 static u64 notrace mmp_read_sched_clock(void)
68 static irqreturn_t timer_interrupt(int irq, void *dev_id)
70 struct clock_event_device *c = dev_id;
73 * Clear pending interrupt status.
75 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
80 __raw_writel(0x02, mmp_timer_base + TMR_CER);
87 static int timer_set_next_event(unsigned long delta,
88 struct clock_event_device *dev)
92 local_irq_save(flags);
97 __raw_writel(0x02, mmp_timer_base + TMR_CER);
100 * Clear and enable timer match 0 interrupt.
102 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
103 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
106 * Setup new clockevent timer value.
108 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
113 __raw_writel(0x03, mmp_timer_base + TMR_CER);
115 local_irq_restore(flags);
120 static int timer_set_shutdown(struct clock_event_device *evt)
124 local_irq_save(flags);
125 /* disable the matching interrupt */
126 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
127 local_irq_restore(flags);
132 static struct clock_event_device ckevt = {
133 .name = "clockevent",
134 .features = CLOCK_EVT_FEAT_ONESHOT,
136 .set_next_event = timer_set_next_event,
137 .set_state_shutdown = timer_set_shutdown,
138 .set_state_oneshot = timer_set_shutdown,
141 static u64 clksrc_read(struct clocksource *cs)
146 static struct clocksource cksrc = {
147 .name = "clocksource",
150 .mask = CLOCKSOURCE_MASK(32),
151 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
154 static void __init timer_config(void)
156 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
158 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
160 ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
161 (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
162 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
163 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
165 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
166 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
168 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
169 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
170 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
172 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
173 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
174 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
176 /* enable timer 1 counter */
177 __raw_writel(0x2, mmp_timer_base + TMR_CER);
180 void __init mmp_timer_init(int irq, unsigned long rate)
184 sched_clock_register(mmp_read_sched_clock, 32, rate);
186 ckevt.cpumask = cpumask_of(0);
188 if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
190 pr_err("Failed to request irq %d (timer)\n", irq);
192 clocksource_register_hz(&cksrc, rate);
193 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
196 static int __init mmp_dt_init_timer(struct device_node *np)
202 clk = of_clk_get(np, 0);
204 ret = clk_prepare_enable(clk);
207 rate = clk_get_rate(clk);
208 } else if (cpu_is_pj4()) {
214 irq = irq_of_parse_and_map(np, 0);
218 mmp_timer_base = of_iomap(np, 0);
222 mmp_timer_init(irq, rate);
226 TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);