1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
4 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
7 #include <linux/delay.h>
8 #include <linux/init.h>
11 #include <linux/of_address.h>
12 #include <linux/regmap.h>
13 #include <linux/reset.h>
14 #include <linux/smp.h>
15 #include <linux/mfd/syscon.h>
17 #include <asm/cacheflush.h>
19 #include <asm/smp_scu.h>
20 #include <asm/smp_plat.h>
22 #define MESON_SMP_SRAM_CPU_CTRL_REG (0x00)
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
25 #define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00)
26 #define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04)
27 #define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14)
29 #define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16))
30 #define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
32 #define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16))
34 static void __iomem *sram_base;
35 static void __iomem *scu_base;
36 static struct regmap *pmu;
38 static struct reset_control *meson_smp_get_core_reset(int cpu)
40 struct device_node *np = of_get_cpu_node(cpu, 0);
42 return of_reset_control_get_exclusive(np, NULL);
45 static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
47 u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
54 /* keep bit 0 always enabled */
57 writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
60 static void __init meson_smp_prepare_cpus(const char *scu_compatible,
61 const char *pmu_compatible,
62 const char *sram_compatible)
64 static struct device_node *node;
67 node = of_find_compatible_node(NULL, NULL, sram_compatible);
69 pr_err("Missing SRAM node\n");
73 sram_base = of_iomap(node, 0);
76 pr_err("Couldn't map SRAM registers\n");
81 pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
83 pr_err("Couldn't map PMU registers\n");
88 node = of_find_compatible_node(NULL, NULL, scu_compatible);
90 pr_err("Missing SCU node\n");
94 scu_base = of_iomap(node, 0);
97 pr_err("Couldn't map SCU registers\n");
101 scu_enable(scu_base);
104 static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
107 "amlogic,meson8b-smp-sram");
110 static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
113 "amlogic,meson8-smp-sram");
116 static void meson_smp_begin_secondary_boot(unsigned int cpu)
119 * Set the entry point before powering on the CPU through the SCU. This
120 * is needed if the CPU is in "warm" state (= after rebooting the
121 * system without power-cycling, or when taking the CPU offline and
122 * then taking it online again.
124 writel(__pa_symbol(secondary_startup),
125 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
128 * SCU Power on CPU (needs to be done before starting the CPU,
129 * otherwise the secondary CPU will not start).
131 scu_cpu_power_enable(scu_base, cpu);
134 static int meson_smp_finalize_secondary_boot(unsigned int cpu)
136 unsigned long timeout;
138 timeout = jiffies + (10 * HZ);
139 while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
140 if (!time_before(jiffies, timeout)) {
141 pr_err("Timeout while waiting for CPU%d status\n",
147 writel(__pa_symbol(secondary_startup),
148 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
150 meson_smp_set_cpu_ctrl(cpu, true);
155 static int meson8_smp_boot_secondary(unsigned int cpu,
156 struct task_struct *idle)
158 struct reset_control *rstc;
161 rstc = meson_smp_get_core_reset(cpu);
163 pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
164 return PTR_ERR(rstc);
167 meson_smp_begin_secondary_boot(cpu);
170 ret = reset_control_assert(rstc);
172 pr_err("Failed to assert CPU%d reset\n", cpu);
177 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
178 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
180 pr_err("Couldn't wake up CPU%d\n", cpu);
186 /* Isolation disable */
187 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
190 pr_err("Error when disabling isolation of CPU%d\n", cpu);
195 ret = reset_control_deassert(rstc);
197 pr_err("Failed to de-assert CPU%d reset\n", cpu);
201 ret = meson_smp_finalize_secondary_boot(cpu);
206 reset_control_put(rstc);
211 static int meson8b_smp_boot_secondary(unsigned int cpu,
212 struct task_struct *idle)
214 struct reset_control *rstc;
218 rstc = meson_smp_get_core_reset(cpu);
220 pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
221 return PTR_ERR(rstc);
224 meson_smp_begin_secondary_boot(cpu);
227 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
228 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
230 pr_err("Couldn't power up CPU%d\n", cpu);
237 ret = reset_control_assert(rstc);
239 pr_err("Failed to assert CPU%d reset\n", cpu);
243 /* Memory power UP */
244 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
245 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
247 pr_err("Couldn't power up the memory for CPU%d\n", cpu);
252 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
253 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
255 pr_err("Couldn't wake up CPU%d\n", cpu);
261 ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
262 val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
265 pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
269 /* Isolation disable */
270 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
273 pr_err("Error when disabling isolation of CPU%d\n", cpu);
278 ret = reset_control_deassert(rstc);
280 pr_err("Failed to de-assert CPU%d reset\n", cpu);
284 ret = meson_smp_finalize_secondary_boot(cpu);
289 reset_control_put(rstc);
294 #ifdef CONFIG_HOTPLUG_CPU
295 static void meson8_smp_cpu_die(unsigned int cpu)
297 meson_smp_set_cpu_ctrl(cpu, false);
299 v7_exit_coherency_flush(louis);
301 scu_power_mode(scu_base, SCU_PM_POWEROFF);
306 /* we should never get here */
310 static int meson8_smp_cpu_kill(unsigned int cpu)
313 unsigned long timeout;
315 timeout = jiffies + (50 * HZ);
317 power_mode = scu_get_cpu_power_mode(scu_base, cpu);
319 if (power_mode == SCU_PM_POWEROFF)
322 usleep_range(10000, 15000);
323 } while (time_before(jiffies, timeout));
325 if (power_mode != SCU_PM_POWEROFF) {
326 pr_err("Error while waiting for SCU power-off on CPU%d\n",
333 /* Isolation enable */
334 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
337 pr_err("Error when enabling isolation for CPU%d\n", cpu);
344 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
345 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
347 pr_err("Couldn't change sleep status of CPU%d\n", cpu);
354 static int meson8b_smp_cpu_kill(unsigned int cpu)
356 int ret, power_mode, count = 5000;
359 power_mode = scu_get_cpu_power_mode(scu_base, cpu);
361 if (power_mode == SCU_PM_POWEROFF)
367 if (power_mode != SCU_PM_POWEROFF) {
368 pr_err("Error while waiting for SCU power-off on CPU%d\n",
376 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
377 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
379 pr_err("Couldn't power down CPU%d\n", cpu);
383 /* Isolation enable */
384 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
387 pr_err("Error when enabling isolation for CPU%d\n", cpu);
394 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
395 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
397 pr_err("Couldn't change sleep status of CPU%d\n", cpu);
401 /* Memory power DOWN */
402 ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
403 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
405 pr_err("Couldn't power down the memory of CPU%d\n", cpu);
413 static struct smp_operations meson8_smp_ops __initdata = {
414 .smp_prepare_cpus = meson8_smp_prepare_cpus,
415 .smp_boot_secondary = meson8_smp_boot_secondary,
416 #ifdef CONFIG_HOTPLUG_CPU
417 .cpu_die = meson8_smp_cpu_die,
418 .cpu_kill = meson8_smp_cpu_kill,
422 static struct smp_operations meson8b_smp_ops __initdata = {
423 .smp_prepare_cpus = meson8b_smp_prepare_cpus,
424 .smp_boot_secondary = meson8b_smp_boot_secondary,
425 #ifdef CONFIG_HOTPLUG_CPU
426 .cpu_die = meson8_smp_cpu_die,
427 .cpu_kill = meson8b_smp_cpu_kill,
431 CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
432 CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);