arch/arm/mach-meson/platsmp.c

   1 /*
   2  * Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
   3  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset.h>
  24 #include <linux/smp.h>
  25 #include <linux/mfd/syscon.h>
  26
  27 #include <asm/cacheflush.h>
  28 #include <asm/cp15.h>
  29 #include <asm/smp_scu.h>
  30 #include <asm/smp_plat.h>
  31
  32 #define MESON_SMP_SRAM_CPU_CTRL_REG             (0x00)
  33 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c)     (0x04 + ((c - 1) << 2))
  34
  35 #define MESON_CPU_AO_RTI_PWR_A9_CNTL0           (0x00)
  36 #define MESON_CPU_AO_RTI_PWR_A9_CNTL1           (0x04)
  37 #define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0         (0x14)
  38
  39 #define MESON_CPU_PWR_A9_CNTL0_M(c)             (0x03 << ((c * 2) + 16))
  40 #define MESON_CPU_PWR_A9_CNTL1_M(c)             (0x03 << ((c + 1) << 1))
  41 #define MESON_CPU_PWR_A9_MEM_PD0_M(c)           (0x0f << (32 - (c * 4)))
  42 #define MESON_CPU_PWR_A9_CNTL1_ST(c)            (0x01 << (c + 16))
  43
  44 static void __iomem *sram_base;
  45 static void __iomem *scu_base;
  46 static struct regmap *pmu;
  47
  48 static struct reset_control *meson_smp_get_core_reset(int cpu)
  49 {
  50         struct device_node *np = of_get_cpu_node(cpu, 0);
  51
  52         return of_reset_control_get_exclusive(np, NULL);
  53 }
  54
  55 static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
  56 {
  57         u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
  58
  59         if (on_off)
  60                 val |= BIT(cpu);
  61         else
  62                 val &= ~BIT(cpu);
  63
  64         /* keep bit 0 always enabled */
  65         val |= BIT(0);
  66
  67         writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
  68 }
  69
  70 static void __init meson_smp_prepare_cpus(const char *scu_compatible,
  71                                           const char *pmu_compatible,
  72                                           const char *sram_compatible)
  73 {
  74         static struct device_node *node;
  75
  76         /* SMP SRAM */
  77         node = of_find_compatible_node(NULL, NULL, sram_compatible);
  78         if (!node) {
  79                 pr_err("Missing SRAM node\n");
  80                 return;
  81         }
  82
  83         sram_base = of_iomap(node, 0);
  84         of_node_put(node);
  85         if (!sram_base) {
  86                 pr_err("Couldn't map SRAM registers\n");
  87                 return;
  88         }
  89
  90         /* PMU */
  91         pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
  92         if (IS_ERR(pmu)) {
  93                 pr_err("Couldn't map PMU registers\n");
  94                 return;
  95         }
  96
  97         /* SCU */
  98         node = of_find_compatible_node(NULL, NULL, scu_compatible);
  99         if (!node) {
 100                 pr_err("Missing SCU node\n");
 101                 return;
 102         }
 103
 104         scu_base = of_iomap(node, 0);
 105         of_node_put(node);
 106         if (!scu_base) {
 107                 pr_err("Couldn't map SCU registers\n");
 108                 return;
 109         }
 110
 111         scu_enable(scu_base);
 112 }
 113
 114 static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
 115 {
 116         meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
 117                                "amlogic,meson8b-smp-sram");
 118 }
 119
 120 static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
 121 {
 122         meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
 123                                "amlogic,meson8-smp-sram");
 124 }
 125
 126 static void meson_smp_begin_secondary_boot(unsigned int cpu)
 127 {
 128         /*
 129          * Set the entry point before powering on the CPU through the SCU. This
 130          * is needed if the CPU is in "warm" state (= after rebooting the
 131          * system without power-cycling, or when taking the CPU offline and
 132          * then taking it online again.
 133          */
 134         writel(__pa_symbol(secondary_startup),
 135                sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
 136
 137         /*
 138          * SCU Power on CPU (needs to be done before starting the CPU,
 139          * otherwise the secondary CPU will not start).
 140          */
 141         scu_cpu_power_enable(scu_base, cpu);
 142 }
 143
 144 static int meson_smp_finalize_secondary_boot(unsigned int cpu)
 145 {
 146         unsigned long timeout;
 147
 148         timeout = jiffies + (10 * HZ);
 149         while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
 150                 if (!time_before(jiffies, timeout)) {
 151                         pr_err("Timeout while waiting for CPU%d status\n",
 152                                cpu);
 153                         return -ETIMEDOUT;
 154                 }
 155         }
 156
 157         writel(__pa_symbol(secondary_startup),
 158                sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
 159
 160         meson_smp_set_cpu_ctrl(cpu, true);
 161
 162         return 0;
 163 }
 164
 165 static int meson8_smp_boot_secondary(unsigned int cpu,
 166                                      struct task_struct *idle)
 167 {
 168         struct reset_control *rstc;
 169         int ret;
 170
 171         rstc = meson_smp_get_core_reset(cpu);
 172         if (IS_ERR(rstc)) {
 173                 pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
 174                 return PTR_ERR(rstc);
 175         }
 176
 177         meson_smp_begin_secondary_boot(cpu);
 178
 179         /* Reset enable */
 180         ret = reset_control_assert(rstc);
 181         if (ret) {
 182                 pr_err("Failed to assert CPU%d reset\n", cpu);
 183                 goto out;
 184         }
 185
 186         /* CPU power ON */
 187         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
 188                                  MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
 189         if (ret < 0) {
 190                 pr_err("Couldn't wake up CPU%d\n", cpu);
 191                 goto out;
 192         }
 193
 194         udelay(10);
 195
 196         /* Isolation disable */
 197         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
 198                                  0);
 199         if (ret < 0) {
 200                 pr_err("Error when disabling isolation of CPU%d\n", cpu);
 201                 goto out;
 202         }
 203
 204         /* Reset disable */
 205         ret = reset_control_deassert(rstc);
 206         if (ret) {
 207                 pr_err("Failed to de-assert CPU%d reset\n", cpu);
 208                 goto out;
 209         }
 210
 211         ret = meson_smp_finalize_secondary_boot(cpu);
 212         if (ret)
 213                 goto out;
 214
 215 out:
 216         reset_control_put(rstc);
 217
 218         return 0;
 219 }
 220
 221 static int meson8b_smp_boot_secondary(unsigned int cpu,
 222                                      struct task_struct *idle)
 223 {
 224         struct reset_control *rstc;
 225         int ret;
 226         u32 val;
 227
 228         rstc = meson_smp_get_core_reset(cpu);
 229         if (IS_ERR(rstc)) {
 230                 pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
 231                 return PTR_ERR(rstc);
 232         }
 233
 234         meson_smp_begin_secondary_boot(cpu);
 235
 236         /* CPU power UP */
 237         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
 238                                  MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
 239         if (ret < 0) {
 240                 pr_err("Couldn't power up CPU%d\n", cpu);
 241                 goto out;
 242         }
 243
 244         udelay(5);
 245
 246         /* Reset enable */
 247         ret = reset_control_assert(rstc);
 248         if (ret) {
 249                 pr_err("Failed to assert CPU%d reset\n", cpu);
 250                 goto out;
 251         }
 252
 253         /* Memory power UP */
 254         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
 255                                  MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
 256         if (ret < 0) {
 257                 pr_err("Couldn't power up the memory for CPU%d\n", cpu);
 258                 goto out;
 259         }
 260
 261         /* Wake up CPU */
 262         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
 263                                  MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
 264         if (ret < 0) {
 265                 pr_err("Couldn't wake up CPU%d\n", cpu);
 266                 goto out;
 267         }
 268
 269         udelay(10);
 270
 271         ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
 272                                        val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
 273                                        10, 10000);
 274         if (ret) {
 275                 pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
 276                 goto out;
 277         }
 278
 279         /* Isolation disable */
 280         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
 281                                  0);
 282         if (ret < 0) {
 283                 pr_err("Error when disabling isolation of CPU%d\n", cpu);
 284                 goto out;
 285         }
 286
 287         /* Reset disable */
 288         ret = reset_control_deassert(rstc);
 289         if (ret) {
 290                 pr_err("Failed to de-assert CPU%d reset\n", cpu);
 291                 goto out;
 292         }
 293
 294         ret = meson_smp_finalize_secondary_boot(cpu);
 295         if (ret)
 296                 goto out;
 297
 298 out:
 299         reset_control_put(rstc);
 300
 301         return 0;
 302 }
 303
 304 #ifdef CONFIG_HOTPLUG_CPU
 305 static void meson8_smp_cpu_die(unsigned int cpu)
 306 {
 307         meson_smp_set_cpu_ctrl(cpu, false);
 308
 309         v7_exit_coherency_flush(louis);
 310
 311         scu_power_mode(scu_base, SCU_PM_POWEROFF);
 312
 313         dsb();
 314         wfi();
 315
 316         /* we should never get here */
 317         WARN_ON(1);
 318 }
 319
 320 static int meson8_smp_cpu_kill(unsigned int cpu)
 321 {
 322         int ret, power_mode;
 323         unsigned long timeout;
 324
 325         timeout = jiffies + (50 * HZ);
 326         do {
 327                 power_mode = scu_get_cpu_power_mode(scu_base, cpu);
 328
 329                 if (power_mode == SCU_PM_POWEROFF)
 330                         break;
 331
 332                 usleep_range(10000, 15000);
 333         } while (time_before(jiffies, timeout));
 334
 335         if (power_mode != SCU_PM_POWEROFF) {
 336                 pr_err("Error while waiting for SCU power-off on CPU%d\n",
 337                        cpu);
 338                 return -ETIMEDOUT;
 339         }
 340
 341         msleep(30);
 342
 343         /* Isolation enable */
 344         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
 345                                  0x3);
 346         if (ret < 0) {
 347                 pr_err("Error when enabling isolation for CPU%d\n", cpu);
 348                 return ret;
 349         }
 350
 351         udelay(10);
 352
 353         /* CPU power OFF */
 354         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
 355                                  MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
 356         if (ret < 0) {
 357                 pr_err("Couldn't change sleep status of CPU%d\n", cpu);
 358                 return ret;
 359         }
 360
 361         return 1;
 362 }
 363
 364 static int meson8b_smp_cpu_kill(unsigned int cpu)
 365 {
 366         int ret, power_mode, count = 5000;
 367
 368         do {
 369                 power_mode = scu_get_cpu_power_mode(scu_base, cpu);
 370
 371                 if (power_mode == SCU_PM_POWEROFF)
 372                         break;
 373
 374                 udelay(10);
 375         } while (++count);
 376
 377         if (power_mode != SCU_PM_POWEROFF) {
 378                 pr_err("Error while waiting for SCU power-off on CPU%d\n",
 379                        cpu);
 380                 return -ETIMEDOUT;
 381         }
 382
 383         udelay(10);
 384
 385         /* CPU power DOWN */
 386         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
 387                                  MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
 388         if (ret < 0) {
 389                 pr_err("Couldn't power down CPU%d\n", cpu);
 390                 return ret;
 391         }
 392
 393         /* Isolation enable */
 394         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
 395                                  0x3);
 396         if (ret < 0) {
 397                 pr_err("Error when enabling isolation for CPU%d\n", cpu);
 398                 return ret;
 399         }
 400
 401         udelay(10);
 402
 403         /* Sleep status */
 404         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
 405                                  MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
 406         if (ret < 0) {
 407                 pr_err("Couldn't change sleep status of CPU%d\n", cpu);
 408                 return ret;
 409         }
 410
 411         /* Memory power DOWN */
 412         ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
 413                                  MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
 414         if (ret < 0) {
 415                 pr_err("Couldn't power down the memory of CPU%d\n", cpu);
 416                 return ret;
 417         }
 418
 419         return 1;
 420 }
 421 #endif
 422
 423 static struct smp_operations meson8_smp_ops __initdata = {
 424         .smp_prepare_cpus       = meson8_smp_prepare_cpus,
 425         .smp_boot_secondary     = meson8_smp_boot_secondary,
 426 #ifdef CONFIG_HOTPLUG_CPU
 427         .cpu_die                = meson8_smp_cpu_die,
 428         .cpu_kill               = meson8_smp_cpu_kill,
 429 #endif
 430 };
 431
 432 static struct smp_operations meson8b_smp_ops __initdata = {
 433         .smp_prepare_cpus       = meson8b_smp_prepare_cpus,
 434         .smp_boot_secondary     = meson8b_smp_boot_secondary,
 435 #ifdef CONFIG_HOTPLUG_CPU
 436         .cpu_die                = meson8_smp_cpu_die,
 437         .cpu_kill               = meson8b_smp_cpu_kill,
 438 #endif
 439 };
 440
 441 CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
 442 CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);