1 // SPDX-License-Identifier: GPL-2.0-only
3 * platform device definitions for the iop3xx dma/xor engines
4 * Copyright © 2006, Intel Corporation.
6 #include <linux/platform_device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/platform_data/dma-iop32x.h>
13 #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
14 #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
15 #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
17 #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
18 #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
19 #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
21 #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
22 #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
23 #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
25 /* AAU and DMA Channels */
26 static struct resource iop3xx_dma_0_resources[] = {
28 .start = IOP3XX_DMA_PHYS_BASE(0),
29 .end = IOP3XX_DMA_UPPER_PA(0),
30 .flags = IORESOURCE_MEM,
33 .start = IRQ_DMA0_EOT,
35 .flags = IORESOURCE_IRQ
38 .start = IRQ_DMA0_EOC,
40 .flags = IORESOURCE_IRQ
43 .start = IRQ_DMA0_ERR,
45 .flags = IORESOURCE_IRQ
49 static struct resource iop3xx_dma_1_resources[] = {
51 .start = IOP3XX_DMA_PHYS_BASE(1),
52 .end = IOP3XX_DMA_UPPER_PA(1),
53 .flags = IORESOURCE_MEM,
56 .start = IRQ_DMA1_EOT,
58 .flags = IORESOURCE_IRQ
61 .start = IRQ_DMA1_EOC,
63 .flags = IORESOURCE_IRQ
66 .start = IRQ_DMA1_ERR,
68 .flags = IORESOURCE_IRQ
73 static struct resource iop3xx_aau_resources[] = {
75 .start = IOP3XX_AAU_PHYS_BASE,
76 .end = IOP3XX_AAU_UPPER_PA,
77 .flags = IORESOURCE_MEM,
82 .flags = IORESOURCE_IRQ
87 .flags = IORESOURCE_IRQ
92 .flags = IORESOURCE_IRQ
96 static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
98 static struct iop_adma_platform_data iop3xx_dma_0_data = {
100 .pool_size = PAGE_SIZE,
103 static struct iop_adma_platform_data iop3xx_dma_1_data = {
105 .pool_size = PAGE_SIZE,
108 static struct iop_adma_platform_data iop3xx_aau_data = {
110 .pool_size = 3 * PAGE_SIZE,
113 struct platform_device iop3xx_dma_0_channel = {
117 .resource = iop3xx_dma_0_resources,
119 .dma_mask = &iop3xx_adma_dmamask,
120 .coherent_dma_mask = DMA_BIT_MASK(32),
121 .platform_data = (void *) &iop3xx_dma_0_data,
125 struct platform_device iop3xx_dma_1_channel = {
129 .resource = iop3xx_dma_1_resources,
131 .dma_mask = &iop3xx_adma_dmamask,
132 .coherent_dma_mask = DMA_BIT_MASK(32),
133 .platform_data = (void *) &iop3xx_dma_1_data,
137 struct platform_device iop3xx_aau_channel = {
141 .resource = iop3xx_aau_resources,
143 .dma_mask = &iop3xx_adma_dmamask,
144 .coherent_dma_mask = DMA_BIT_MASK(32),
145 .platform_data = (void *) &iop3xx_aau_data,
149 static int __init iop3xx_adma_cap_init(void)
151 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
152 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
154 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
155 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
157 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
158 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
163 arch_initcall(iop3xx_adma_cap_init);