arch/arm/mach-imx/pm-imx6.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2011-2014 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  */
   6
   7 #include <linux/clk/imx.h>
   8 #include <linux/delay.h>
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/genalloc.h>
  13 #include <linux/irqchip/arm-gic.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include <linux/suspend.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/fncpy.h>
  24 #include <asm/proc-fns.h>
  25 #include <asm/suspend.h>
  26 #include <asm/tlb.h>
  27
  28 #include "common.h"
  29 #include "hardware.h"
  30
  31 #define CCR                             0x0
  32 #define BM_CCR_WB_COUNT                 (0x7 << 16)
  33 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
  34 #define BM_CCR_RBC_EN                   (0x1 << 27)
  35
  36 #define CLPCR                           0x54
  37 #define BP_CLPCR_LPM                    0
  38 #define BM_CLPCR_LPM                    (0x3 << 0)
  39 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
  40 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
  41 #define BM_CLPCR_SBYOS                  (0x1 << 6)
  42 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
  43 #define BM_CLPCR_VSTBY                  (0x1 << 8)
  44 #define BP_CLPCR_STBY_COUNT             9
  45 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
  46 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
  47 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
  48 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
  49 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
  50 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
  51 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
  52 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
  53 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
  54 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
  55 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
  56 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
  57
  58 #define CGPR                            0x64
  59 #define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
  60
  61 #define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
  62 #define MX6_MAX_MMDC_IO_NUM             33
  63
  64 static void __iomem *ccm_base;
  65 static void __iomem *suspend_ocram_base;
  66 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
  67
  68 /*
  69  * suspend ocram space layout:
  70  * ======================== high address ======================
  71  *                              .
  72  *                              .
  73  *                              .
  74  *                              ^
  75  *                              ^
  76  *                              ^
  77  *                      imx6_suspend code
  78  *              PM_INFO structure(imx6_cpu_pm_info)
  79  * ======================== low address =======================
  80  */
  81
  82 struct imx6_pm_base {
  83         phys_addr_t pbase;
  84         void __iomem *vbase;
  85 };
  86
  87 struct imx6_pm_socdata {
  88         u32 ddr_type;
  89         const char *mmdc_compat;
  90         const char *src_compat;
  91         const char *iomuxc_compat;
  92         const char *gpc_compat;
  93         const char *pl310_compat;
  94         const u32 mmdc_io_num;
  95         const u32 *mmdc_io_offset;
  96 };
  97
  98 static const u32 imx6q_mmdc_io_offset[] __initconst = {
  99         0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
 100         0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
 101         0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 102         0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
 103         0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
 104         0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
 105         0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 106         0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
 107         0x74c,                      /* GPR_ADDS */
 108 };
 109
 110 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
 111         0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
 112         0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
 113         0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 114         0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
 115         0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
 116         0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
 117         0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 118         0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
 119         0x74c,                      /* GPR_ADDS */
 120 };
 121
 122 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
 123         0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
 124         0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
 125         0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 126         0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
 127         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 128 };
 129
 130 static const u32 imx6sll_mmdc_io_offset[] __initconst = {
 131         0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
 132         0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
 133         0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
 134         0x2a4, 0x2a8,               /* SDCKE0, SDCKE1*/
 135 };
 136
 137 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 138         0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
 139         0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
 140         0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 141         0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
 142         0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
 143 };
 144
 145 static const u32 imx6ul_mmdc_io_offset[] __initconst = {
 146         0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
 147         0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
 148         0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
 149         0x494, 0x4b0,               /* MODE_CTL, MODE, */
 150 };
 151
 152 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 153         .mmdc_compat = "fsl,imx6q-mmdc",
 154         .src_compat = "fsl,imx6q-src",
 155         .iomuxc_compat = "fsl,imx6q-iomuxc",
 156         .gpc_compat = "fsl,imx6q-gpc",
 157         .pl310_compat = "arm,pl310-cache",
 158         .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
 159         .mmdc_io_offset = imx6q_mmdc_io_offset,
 160 };
 161
 162 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 163         .mmdc_compat = "fsl,imx6q-mmdc",
 164         .src_compat = "fsl,imx6q-src",
 165         .iomuxc_compat = "fsl,imx6dl-iomuxc",
 166         .gpc_compat = "fsl,imx6q-gpc",
 167         .pl310_compat = "arm,pl310-cache",
 168         .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
 169         .mmdc_io_offset = imx6dl_mmdc_io_offset,
 170 };
 171
 172 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 173         .mmdc_compat = "fsl,imx6sl-mmdc",
 174         .src_compat = "fsl,imx6sl-src",
 175         .iomuxc_compat = "fsl,imx6sl-iomuxc",
 176         .gpc_compat = "fsl,imx6sl-gpc",
 177         .pl310_compat = "arm,pl310-cache",
 178         .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
 179         .mmdc_io_offset = imx6sl_mmdc_io_offset,
 180 };
 181
 182 static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
 183         .mmdc_compat = "fsl,imx6sll-mmdc",
 184         .src_compat = "fsl,imx6sll-src",
 185         .iomuxc_compat = "fsl,imx6sll-iomuxc",
 186         .gpc_compat = "fsl,imx6sll-gpc",
 187         .pl310_compat = "arm,pl310-cache",
 188         .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
 189         .mmdc_io_offset = imx6sll_mmdc_io_offset,
 190 };
 191
 192 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 193         .mmdc_compat = "fsl,imx6sx-mmdc",
 194         .src_compat = "fsl,imx6sx-src",
 195         .iomuxc_compat = "fsl,imx6sx-iomuxc",
 196         .gpc_compat = "fsl,imx6sx-gpc",
 197         .pl310_compat = "arm,pl310-cache",
 198         .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
 199         .mmdc_io_offset = imx6sx_mmdc_io_offset,
 200 };
 201
 202 static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
 203         .mmdc_compat = "fsl,imx6ul-mmdc",
 204         .src_compat = "fsl,imx6ul-src",
 205         .iomuxc_compat = "fsl,imx6ul-iomuxc",
 206         .gpc_compat = "fsl,imx6ul-gpc",
 207         .pl310_compat = NULL,
 208         .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
 209         .mmdc_io_offset = imx6ul_mmdc_io_offset,
 210 };
 211
 212 /*
 213  * This structure is for passing necessary data for low level ocram
 214  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
 215  * definition is changed, the offset definition in
 216  * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
 217  * otherwise, the suspend to ocram function will be broken!
 218  */
 219 struct imx6_cpu_pm_info {
 220         phys_addr_t pbase; /* The physical address of pm_info. */
 221         phys_addr_t resume_addr; /* The physical resume address for asm code */
 222         u32 ddr_type;
 223         u32 pm_info_size; /* Size of pm_info. */
 224         struct imx6_pm_base mmdc_base;
 225         struct imx6_pm_base src_base;
 226         struct imx6_pm_base iomuxc_base;
 227         struct imx6_pm_base ccm_base;
 228         struct imx6_pm_base gpc_base;
 229         struct imx6_pm_base l2_base;
 230         u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
 231         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 232 } __aligned(8);
 233
 234 void imx6_set_int_mem_clk_lpm(bool enable)
 235 {
 236         u32 val = readl_relaxed(ccm_base + CGPR);
 237
 238         val &= ~BM_CGPR_INT_MEM_CLK_LPM;
 239         if (enable)
 240                 val |= BM_CGPR_INT_MEM_CLK_LPM;
 241         writel_relaxed(val, ccm_base + CGPR);
 242 }
 243
 244 void imx6_enable_rbc(bool enable)
 245 {
 246         u32 val;
 247
 248         /*
 249          * need to mask all interrupts in GPC before
 250          * operating RBC configurations
 251          */
 252         imx_gpc_mask_all();
 253
 254         /* configure RBC enable bit */
 255         val = readl_relaxed(ccm_base + CCR);
 256         val &= ~BM_CCR_RBC_EN;
 257         val |= enable ? BM_CCR_RBC_EN : 0;
 258         writel_relaxed(val, ccm_base + CCR);
 259
 260         /* configure RBC count */
 261         val = readl_relaxed(ccm_base + CCR);
 262         val &= ~BM_CCR_RBC_BYPASS_COUNT;
 263         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
 264         writel(val, ccm_base + CCR);
 265
 266         /*
 267          * need to delay at least 2 cycles of CKIL(32K)
 268          * due to hardware design requirement, which is
 269          * ~61us, here we use 65us for safe
 270          */
 271         udelay(65);
 272
 273         /* restore GPC interrupt mask settings */
 274         imx_gpc_restore_all();
 275 }
 276
 277 static void imx6q_enable_wb(bool enable)
 278 {
 279         u32 val;
 280
 281         /* configure well bias enable bit */
 282         val = readl_relaxed(ccm_base + CLPCR);
 283         val &= ~BM_CLPCR_WB_PER_AT_LPM;
 284         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
 285         writel_relaxed(val, ccm_base + CLPCR);
 286
 287         /* configure well bias count */
 288         val = readl_relaxed(ccm_base + CCR);
 289         val &= ~BM_CCR_WB_COUNT;
 290         val |= enable ? BM_CCR_WB_COUNT : 0;
 291         writel_relaxed(val, ccm_base + CCR);
 292 }
 293
 294 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
 295 {
 296         u32 val = readl_relaxed(ccm_base + CLPCR);
 297
 298         val &= ~BM_CLPCR_LPM;
 299         switch (mode) {
 300         case WAIT_CLOCKED:
 301                 break;
 302         case WAIT_UNCLOCKED:
 303                 val |= 0x1 << BP_CLPCR_LPM;
 304                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
 305                 break;
 306         case STOP_POWER_ON:
 307                 val |= 0x2 << BP_CLPCR_LPM;
 308                 val &= ~BM_CLPCR_VSTBY;
 309                 val &= ~BM_CLPCR_SBYOS;
 310                 if (cpu_is_imx6sl())
 311                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 312                 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
 313                     cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
 314                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 315                 else
 316                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 317                 break;
 318         case WAIT_UNCLOCKED_POWER_OFF:
 319                 val |= 0x1 << BP_CLPCR_LPM;
 320                 val &= ~BM_CLPCR_VSTBY;
 321                 val &= ~BM_CLPCR_SBYOS;
 322                 break;
 323         case STOP_POWER_OFF:
 324                 val |= 0x2 << BP_CLPCR_LPM;
 325                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
 326                 val |= BM_CLPCR_VSTBY;
 327                 val |= BM_CLPCR_SBYOS;
 328                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
 329                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 330                 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
 331                     cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
 332                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 333                 else
 334                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 335                 break;
 336         default:
 337                 return -EINVAL;
 338         }
 339
 340         /*
 341          * ERR007265: CCM: When improper low-power sequence is used,
 342          * the SoC enters low power mode before the ARM core executes WFI.
 343          *
 344          * Software workaround:
 345          * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
 346          *    by setting IOMUX_GPR1_GINT.
 347          * 2) Software should then unmask IRQ #32 in GPC before setting CCM
 348          *    Low-Power mode.
 349          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
 350          *    is set (set bits 0-1 of CCM_CLPCR).
 351          *
 352          * Note that IRQ #32 is GIC SPI #0.
 353          */
 354         if (mode != WAIT_CLOCKED)
 355                 imx_gpc_hwirq_unmask(0);
 356         writel_relaxed(val, ccm_base + CLPCR);
 357         if (mode != WAIT_CLOCKED)
 358                 imx_gpc_hwirq_mask(0);
 359
 360         return 0;
 361 }
 362
 363 static int imx6q_suspend_finish(unsigned long val)
 364 {
 365         if (!imx6_suspend_in_ocram_fn) {
 366                 cpu_do_idle();
 367         } else {
 368                 /*
 369                  * call low level suspend function in ocram,
 370                  * as we need to float DDR IO.
 371                  */
 372                 local_flush_tlb_all();
 373                 /* check if need to flush internal L2 cache */
 374                 if (!((struct imx6_cpu_pm_info *)
 375                         suspend_ocram_base)->l2_base.vbase)
 376                         flush_cache_all();
 377                 imx6_suspend_in_ocram_fn(suspend_ocram_base);
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int imx6q_pm_enter(suspend_state_t state)
 384 {
 385         switch (state) {
 386         case PM_SUSPEND_STANDBY:
 387                 imx6_set_lpm(STOP_POWER_ON);
 388                 imx6_set_int_mem_clk_lpm(true);
 389                 imx_gpc_pre_suspend(false);
 390                 if (cpu_is_imx6sl())
 391                         imx6sl_set_wait_clk(true);
 392                 /* Zzz ... */
 393                 cpu_do_idle();
 394                 if (cpu_is_imx6sl())
 395                         imx6sl_set_wait_clk(false);
 396                 imx_gpc_post_resume();
 397                 imx6_set_lpm(WAIT_CLOCKED);
 398                 break;
 399         case PM_SUSPEND_MEM:
 400                 imx6_set_lpm(STOP_POWER_OFF);
 401                 imx6_set_int_mem_clk_lpm(false);
 402                 imx6q_enable_wb(true);
 403                 /*
 404                  * For suspend into ocram, asm code already take care of
 405                  * RBC setting, so we do NOT need to do that here.
 406                  */
 407                 if (!imx6_suspend_in_ocram_fn)
 408                         imx6_enable_rbc(true);
 409                 imx_gpc_pre_suspend(true);
 410                 imx_anatop_pre_suspend();
 411                 /* Zzz ... */
 412                 cpu_suspend(0, imx6q_suspend_finish);
 413                 if (cpu_is_imx6q() || cpu_is_imx6dl())
 414                         imx_smp_prepare();
 415                 imx_anatop_post_resume();
 416                 imx_gpc_post_resume();
 417                 imx6_enable_rbc(false);
 418                 imx6q_enable_wb(false);
 419                 imx6_set_int_mem_clk_lpm(true);
 420                 imx6_set_lpm(WAIT_CLOCKED);
 421                 break;
 422         default:
 423                 return -EINVAL;
 424         }
 425
 426         return 0;
 427 }
 428
 429 static int imx6q_pm_valid(suspend_state_t state)
 430 {
 431         return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
 432 }
 433
 434 static const struct platform_suspend_ops imx6q_pm_ops = {
 435         .enter = imx6q_pm_enter,
 436         .valid = imx6q_pm_valid,
 437 };
 438
 439 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
 440                                 const char *compat)
 441 {
 442         struct device_node *node;
 443         struct resource res;
 444         int ret = 0;
 445
 446         node = of_find_compatible_node(NULL, NULL, compat);
 447         if (!node)
 448                 return -ENODEV;
 449
 450         ret = of_address_to_resource(node, 0, &res);
 451         if (ret)
 452                 goto put_node;
 453
 454         base->pbase = res.start;
 455         base->vbase = ioremap(res.start, resource_size(&res));
 456         if (!base->vbase)
 457                 ret = -ENOMEM;
 458
 459 put_node:
 460         of_node_put(node);
 461         return ret;
 462 }
 463
 464 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
 465 {
 466         phys_addr_t ocram_pbase;
 467         struct device_node *node;
 468         struct platform_device *pdev;
 469         struct imx6_cpu_pm_info *pm_info;
 470         struct gen_pool *ocram_pool;
 471         unsigned long ocram_base;
 472         int i, ret = 0;
 473         const u32 *mmdc_offset_array;
 474
 475         suspend_set_ops(&imx6q_pm_ops);
 476
 477         if (!socdata) {
 478                 pr_warn("%s: invalid argument!\n", __func__);
 479                 return -EINVAL;
 480         }
 481
 482         node = of_find_compatible_node(NULL, NULL, "mmio-sram");
 483         if (!node) {
 484                 pr_warn("%s: failed to find ocram node!\n", __func__);
 485                 return -ENODEV;
 486         }
 487
 488         pdev = of_find_device_by_node(node);
 489         if (!pdev) {
 490                 pr_warn("%s: failed to find ocram device!\n", __func__);
 491                 ret = -ENODEV;
 492                 goto put_node;
 493         }
 494
 495         ocram_pool = gen_pool_get(&pdev->dev, NULL);
 496         if (!ocram_pool) {
 497                 pr_warn("%s: ocram pool unavailable!\n", __func__);
 498                 ret = -ENODEV;
 499                 goto put_device;
 500         }
 501
 502         ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
 503         if (!ocram_base) {
 504                 pr_warn("%s: unable to alloc ocram!\n", __func__);
 505                 ret = -ENOMEM;
 506                 goto put_device;
 507         }
 508
 509         ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
 510
 511         suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
 512                 MX6Q_SUSPEND_OCRAM_SIZE, false);
 513
 514         memset(suspend_ocram_base, 0, sizeof(*pm_info));
 515         pm_info = suspend_ocram_base;
 516         pm_info->pbase = ocram_pbase;
 517         pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
 518         pm_info->pm_info_size = sizeof(*pm_info);
 519
 520         /*
 521          * ccm physical address is not used by asm code currently,
 522          * so get ccm virtual address directly.
 523          */
 524         pm_info->ccm_base.vbase = ccm_base;
 525
 526         ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
 527         if (ret) {
 528                 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
 529                 goto put_device;
 530         }
 531
 532         ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
 533         if (ret) {
 534                 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
 535                 goto src_map_failed;
 536         }
 537
 538         ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
 539         if (ret) {
 540                 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
 541                 goto iomuxc_map_failed;
 542         }
 543
 544         ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
 545         if (ret) {
 546                 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
 547                 goto gpc_map_failed;
 548         }
 549
 550         if (socdata->pl310_compat) {
 551                 ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
 552                 if (ret) {
 553                         pr_warn("%s: failed to get pl310-cache base %d!\n",
 554                                 __func__, ret);
 555                         goto pl310_cache_map_failed;
 556                 }
 557         }
 558
 559         pm_info->ddr_type = imx_mmdc_get_ddr_type();
 560         pm_info->mmdc_io_num = socdata->mmdc_io_num;
 561         mmdc_offset_array = socdata->mmdc_io_offset;
 562
 563         for (i = 0; i < pm_info->mmdc_io_num; i++) {
 564                 pm_info->mmdc_io_val[i][0] =
 565                         mmdc_offset_array[i];
 566                 pm_info->mmdc_io_val[i][1] =
 567                         readl_relaxed(pm_info->iomuxc_base.vbase +
 568                         mmdc_offset_array[i]);
 569         }
 570
 571         imx6_suspend_in_ocram_fn = fncpy(
 572                 suspend_ocram_base + sizeof(*pm_info),
 573                 &imx6_suspend,
 574                 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
 575
 576         __arm_iomem_set_ro(suspend_ocram_base, MX6Q_SUSPEND_OCRAM_SIZE);
 577
 578         goto put_device;
 579
 580 pl310_cache_map_failed:
 581         iounmap(pm_info->gpc_base.vbase);
 582 gpc_map_failed:
 583         iounmap(pm_info->iomuxc_base.vbase);
 584 iomuxc_map_failed:
 585         iounmap(pm_info->src_base.vbase);
 586 src_map_failed:
 587         iounmap(pm_info->mmdc_base.vbase);
 588 put_device:
 589         put_device(&pdev->dev);
 590 put_node:
 591         of_node_put(node);
 592
 593         return ret;
 594 }
 595
 596 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
 597                                         *socdata)
 598 {
 599         struct regmap *gpr;
 600         int ret;
 601
 602         WARN_ON(!ccm_base);
 603
 604         if (IS_ENABLED(CONFIG_SUSPEND)) {
 605                 ret = imx6q_suspend_init(socdata);
 606                 if (ret)
 607                         pr_warn("%s: No DDR LPM support with suspend %d!\n",
 608                                 __func__, ret);
 609         }
 610
 611         /*
 612          * This is for SW workaround step #1 of ERR007265, see comments
 613          * in imx6_set_lpm for details of this errata.
 614          * Force IOMUXC irq pending, so that the interrupt to GPC can be
 615          * used to deassert dsm_request signal when the signal gets
 616          * asserted unexpectedly.
 617          */
 618         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 619         if (!IS_ERR(gpr))
 620                 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
 621                                    IMX6Q_GPR1_GINT);
 622 }
 623
 624 static void imx6_pm_stby_poweroff(void)
 625 {
 626         gic_cpu_if_down(0);
 627         imx6_set_lpm(STOP_POWER_OFF);
 628         imx6q_suspend_finish(0);
 629
 630         mdelay(1000);
 631
 632         pr_emerg("Unable to poweroff system\n");
 633 }
 634
 635 static int imx6_pm_stby_poweroff_probe(void)
 636 {
 637         if (pm_power_off) {
 638                 pr_warn("%s: pm_power_off already claimed  %p %ps!\n",
 639                         __func__, pm_power_off, pm_power_off);
 640                 return -EBUSY;
 641         }
 642
 643         pm_power_off = imx6_pm_stby_poweroff;
 644         return 0;
 645 }
 646
 647 void __init imx6_pm_ccm_init(const char *ccm_compat)
 648 {
 649         struct device_node *np;
 650         u32 val;
 651
 652         np = of_find_compatible_node(NULL, NULL, ccm_compat);
 653         ccm_base = of_iomap(np, 0);
 654         BUG_ON(!ccm_base);
 655
 656         /*
 657          * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
 658          * clock being shut down unexpectedly by WAIT mode.
 659          */
 660         val = readl_relaxed(ccm_base + CLPCR);
 661         val &= ~BM_CLPCR_LPM;
 662         writel_relaxed(val, ccm_base + CLPCR);
 663
 664         if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
 665                 imx6_pm_stby_poweroff_probe();
 666
 667         of_node_put(np);
 668 }
 669
 670 void __init imx6q_pm_init(void)
 671 {
 672         imx6_pm_common_init(&imx6q_pm_data);
 673 }
 674
 675 void __init imx6dl_pm_init(void)
 676 {
 677         imx6_pm_common_init(&imx6dl_pm_data);
 678 }
 679
 680 void __init imx6sl_pm_init(void)
 681 {
 682         struct regmap *gpr;
 683
 684         if (cpu_is_imx6sl()) {
 685                 imx6_pm_common_init(&imx6sl_pm_data);
 686         } else {
 687                 imx6_pm_common_init(&imx6sll_pm_data);
 688                 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 689                 if (!IS_ERR(gpr))
 690                         regmap_update_bits(gpr, IOMUXC_GPR5,
 691                                 IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);
 692         }
 693 }
 694
 695 void __init imx6sx_pm_init(void)
 696 {
 697         imx6_pm_common_init(&imx6sx_pm_data);
 698 }
 699
 700 void __init imx6ul_pm_init(void)
 701 {
 702         imx6_pm_common_init(&imx6ul_pm_data);
 703 }