arch/arm/mach-imx/pm-imx6.c

   1 /*
   2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17 #include <linux/genalloc.h>
  18 #include <linux/irqchip/arm-gic.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/regmap.h>
  25 #include <linux/suspend.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/fncpy.h>
  28 #include <asm/proc-fns.h>
  29 #include <asm/suspend.h>
  30 #include <asm/tlb.h>
  31
  32 #include "common.h"
  33 #include "hardware.h"
  34
  35 #define CCR                             0x0
  36 #define BM_CCR_WB_COUNT                 (0x7 << 16)
  37 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
  38 #define BM_CCR_RBC_EN                   (0x1 << 27)
  39
  40 #define CLPCR                           0x54
  41 #define BP_CLPCR_LPM                    0
  42 #define BM_CLPCR_LPM                    (0x3 << 0)
  43 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
  44 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
  45 #define BM_CLPCR_SBYOS                  (0x1 << 6)
  46 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
  47 #define BM_CLPCR_VSTBY                  (0x1 << 8)
  48 #define BP_CLPCR_STBY_COUNT             9
  49 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
  50 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
  51 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
  52 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
  53 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
  54 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
  55 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
  56 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
  57 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
  58 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
  59 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
  60 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
  61
  62 #define CGPR                            0x64
  63 #define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
  64
  65 #define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
  66 #define MX6_MAX_MMDC_IO_NUM             33
  67
  68 static void __iomem *ccm_base;
  69 static void __iomem *suspend_ocram_base;
  70 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
  71
  72 /*
  73  * suspend ocram space layout:
  74  * ======================== high address ======================
  75  *                              .
  76  *                              .
  77  *                              .
  78  *                              ^
  79  *                              ^
  80  *                              ^
  81  *                      imx6_suspend code
  82  *              PM_INFO structure(imx6_cpu_pm_info)
  83  * ======================== low address =======================
  84  */
  85
  86 struct imx6_pm_base {
  87         phys_addr_t pbase;
  88         void __iomem *vbase;
  89 };
  90
  91 struct imx6_pm_socdata {
  92         u32 ddr_type;
  93         const char *mmdc_compat;
  94         const char *src_compat;
  95         const char *iomuxc_compat;
  96         const char *gpc_compat;
  97         const char *pl310_compat;
  98         const u32 mmdc_io_num;
  99         const u32 *mmdc_io_offset;
 100 };
 101
 102 static const u32 imx6q_mmdc_io_offset[] __initconst = {
 103         0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
 104         0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
 105         0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 106         0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
 107         0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
 108         0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
 109         0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 110         0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
 111         0x74c,                      /* GPR_ADDS */
 112 };
 113
 114 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
 115         0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
 116         0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
 117         0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
 118         0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
 119         0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
 120         0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
 121         0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
 122         0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
 123         0x74c,                      /* GPR_ADDS */
 124 };
 125
 126 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
 127         0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
 128         0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
 129         0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 130         0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
 131         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
 132 };
 133
 134 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 135         0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
 136         0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
 137         0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
 138         0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
 139         0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
 140 };
 141
 142 static const u32 imx6ul_mmdc_io_offset[] __initconst = {
 143         0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
 144         0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
 145         0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
 146         0x494, 0x4b0,               /* MODE_CTL, MODE, */
 147 };
 148
 149 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 150         .mmdc_compat = "fsl,imx6q-mmdc",
 151         .src_compat = "fsl,imx6q-src",
 152         .iomuxc_compat = "fsl,imx6q-iomuxc",
 153         .gpc_compat = "fsl,imx6q-gpc",
 154         .pl310_compat = "arm,pl310-cache",
 155         .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
 156         .mmdc_io_offset = imx6q_mmdc_io_offset,
 157 };
 158
 159 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 160         .mmdc_compat = "fsl,imx6q-mmdc",
 161         .src_compat = "fsl,imx6q-src",
 162         .iomuxc_compat = "fsl,imx6dl-iomuxc",
 163         .gpc_compat = "fsl,imx6q-gpc",
 164         .pl310_compat = "arm,pl310-cache",
 165         .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
 166         .mmdc_io_offset = imx6dl_mmdc_io_offset,
 167 };
 168
 169 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 170         .mmdc_compat = "fsl,imx6sl-mmdc",
 171         .src_compat = "fsl,imx6sl-src",
 172         .iomuxc_compat = "fsl,imx6sl-iomuxc",
 173         .gpc_compat = "fsl,imx6sl-gpc",
 174         .pl310_compat = "arm,pl310-cache",
 175         .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
 176         .mmdc_io_offset = imx6sl_mmdc_io_offset,
 177 };
 178
 179 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 180         .mmdc_compat = "fsl,imx6sx-mmdc",
 181         .src_compat = "fsl,imx6sx-src",
 182         .iomuxc_compat = "fsl,imx6sx-iomuxc",
 183         .gpc_compat = "fsl,imx6sx-gpc",
 184         .pl310_compat = "arm,pl310-cache",
 185         .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
 186         .mmdc_io_offset = imx6sx_mmdc_io_offset,
 187 };
 188
 189 static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
 190         .mmdc_compat = "fsl,imx6ul-mmdc",
 191         .src_compat = "fsl,imx6ul-src",
 192         .iomuxc_compat = "fsl,imx6ul-iomuxc",
 193         .gpc_compat = "fsl,imx6ul-gpc",
 194         .pl310_compat = NULL,
 195         .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
 196         .mmdc_io_offset = imx6ul_mmdc_io_offset,
 197 };
 198
 199 /*
 200  * This structure is for passing necessary data for low level ocram
 201  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
 202  * definition is changed, the offset definition in
 203  * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
 204  * otherwise, the suspend to ocram function will be broken!
 205  */
 206 struct imx6_cpu_pm_info {
 207         phys_addr_t pbase; /* The physical address of pm_info. */
 208         phys_addr_t resume_addr; /* The physical resume address for asm code */
 209         u32 ddr_type;
 210         u32 pm_info_size; /* Size of pm_info. */
 211         struct imx6_pm_base mmdc_base;
 212         struct imx6_pm_base src_base;
 213         struct imx6_pm_base iomuxc_base;
 214         struct imx6_pm_base ccm_base;
 215         struct imx6_pm_base gpc_base;
 216         struct imx6_pm_base l2_base;
 217         u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
 218         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
 219 } __aligned(8);
 220
 221 void imx6_set_int_mem_clk_lpm(bool enable)
 222 {
 223         u32 val = readl_relaxed(ccm_base + CGPR);
 224
 225         val &= ~BM_CGPR_INT_MEM_CLK_LPM;
 226         if (enable)
 227                 val |= BM_CGPR_INT_MEM_CLK_LPM;
 228         writel_relaxed(val, ccm_base + CGPR);
 229 }
 230
 231 void imx6_enable_rbc(bool enable)
 232 {
 233         u32 val;
 234
 235         /*
 236          * need to mask all interrupts in GPC before
 237          * operating RBC configurations
 238          */
 239         imx_gpc_mask_all();
 240
 241         /* configure RBC enable bit */
 242         val = readl_relaxed(ccm_base + CCR);
 243         val &= ~BM_CCR_RBC_EN;
 244         val |= enable ? BM_CCR_RBC_EN : 0;
 245         writel_relaxed(val, ccm_base + CCR);
 246
 247         /* configure RBC count */
 248         val = readl_relaxed(ccm_base + CCR);
 249         val &= ~BM_CCR_RBC_BYPASS_COUNT;
 250         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
 251         writel(val, ccm_base + CCR);
 252
 253         /*
 254          * need to delay at least 2 cycles of CKIL(32K)
 255          * due to hardware design requirement, which is
 256          * ~61us, here we use 65us for safe
 257          */
 258         udelay(65);
 259
 260         /* restore GPC interrupt mask settings */
 261         imx_gpc_restore_all();
 262 }
 263
 264 static void imx6q_enable_wb(bool enable)
 265 {
 266         u32 val;
 267
 268         /* configure well bias enable bit */
 269         val = readl_relaxed(ccm_base + CLPCR);
 270         val &= ~BM_CLPCR_WB_PER_AT_LPM;
 271         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
 272         writel_relaxed(val, ccm_base + CLPCR);
 273
 274         /* configure well bias count */
 275         val = readl_relaxed(ccm_base + CCR);
 276         val &= ~BM_CCR_WB_COUNT;
 277         val |= enable ? BM_CCR_WB_COUNT : 0;
 278         writel_relaxed(val, ccm_base + CCR);
 279 }
 280
 281 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
 282 {
 283         u32 val = readl_relaxed(ccm_base + CLPCR);
 284
 285         val &= ~BM_CLPCR_LPM;
 286         switch (mode) {
 287         case WAIT_CLOCKED:
 288                 break;
 289         case WAIT_UNCLOCKED:
 290                 val |= 0x1 << BP_CLPCR_LPM;
 291                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
 292                 break;
 293         case STOP_POWER_ON:
 294                 val |= 0x2 << BP_CLPCR_LPM;
 295                 val &= ~BM_CLPCR_VSTBY;
 296                 val &= ~BM_CLPCR_SBYOS;
 297                 if (cpu_is_imx6sl())
 298                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 299                 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
 300                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 301                 else
 302                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 303                 break;
 304         case WAIT_UNCLOCKED_POWER_OFF:
 305                 val |= 0x1 << BP_CLPCR_LPM;
 306                 val &= ~BM_CLPCR_VSTBY;
 307                 val &= ~BM_CLPCR_SBYOS;
 308                 break;
 309         case STOP_POWER_OFF:
 310                 val |= 0x2 << BP_CLPCR_LPM;
 311                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
 312                 val |= BM_CLPCR_VSTBY;
 313                 val |= BM_CLPCR_SBYOS;
 314                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
 315                         val |= BM_CLPCR_BYPASS_PMIC_READY;
 316                 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
 317                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
 318                 else
 319                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
 320                 break;
 321         default:
 322                 return -EINVAL;
 323         }
 324
 325         /*
 326          * ERR007265: CCM: When improper low-power sequence is used,
 327          * the SoC enters low power mode before the ARM core executes WFI.
 328          *
 329          * Software workaround:
 330          * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
 331          *    by setting IOMUX_GPR1_GINT.
 332          * 2) Software should then unmask IRQ #32 in GPC before setting CCM
 333          *    Low-Power mode.
 334          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
 335          *    is set (set bits 0-1 of CCM_CLPCR).
 336          *
 337          * Note that IRQ #32 is GIC SPI #0.
 338          */
 339         imx_gpc_hwirq_unmask(0);
 340         writel_relaxed(val, ccm_base + CLPCR);
 341         imx_gpc_hwirq_mask(0);
 342
 343         return 0;
 344 }
 345
 346 static int imx6q_suspend_finish(unsigned long val)
 347 {
 348         if (!imx6_suspend_in_ocram_fn) {
 349                 cpu_do_idle();
 350         } else {
 351                 /*
 352                  * call low level suspend function in ocram,
 353                  * as we need to float DDR IO.
 354                  */
 355                 local_flush_tlb_all();
 356                 /* check if need to flush internal L2 cache */
 357                 if (!((struct imx6_cpu_pm_info *)
 358                         suspend_ocram_base)->l2_base.vbase)
 359                         flush_cache_all();
 360                 imx6_suspend_in_ocram_fn(suspend_ocram_base);
 361         }
 362
 363         return 0;
 364 }
 365
 366 static int imx6q_pm_enter(suspend_state_t state)
 367 {
 368         switch (state) {
 369         case PM_SUSPEND_STANDBY:
 370                 imx6_set_lpm(STOP_POWER_ON);
 371                 imx6_set_int_mem_clk_lpm(true);
 372                 imx_gpc_pre_suspend(false);
 373                 if (cpu_is_imx6sl())
 374                         imx6sl_set_wait_clk(true);
 375                 /* Zzz ... */
 376                 cpu_do_idle();
 377                 if (cpu_is_imx6sl())
 378                         imx6sl_set_wait_clk(false);
 379                 imx_gpc_post_resume();
 380                 imx6_set_lpm(WAIT_CLOCKED);
 381                 break;
 382         case PM_SUSPEND_MEM:
 383                 imx6_set_lpm(STOP_POWER_OFF);
 384                 imx6_set_int_mem_clk_lpm(false);
 385                 imx6q_enable_wb(true);
 386                 /*
 387                  * For suspend into ocram, asm code already take care of
 388                  * RBC setting, so we do NOT need to do that here.
 389                  */
 390                 if (!imx6_suspend_in_ocram_fn)
 391                         imx6_enable_rbc(true);
 392                 imx_gpc_pre_suspend(true);
 393                 imx_anatop_pre_suspend();
 394                 /* Zzz ... */
 395                 cpu_suspend(0, imx6q_suspend_finish);
 396                 if (cpu_is_imx6q() || cpu_is_imx6dl())
 397                         imx_smp_prepare();
 398                 imx_anatop_post_resume();
 399                 imx_gpc_post_resume();
 400                 imx6_enable_rbc(false);
 401                 imx6q_enable_wb(false);
 402                 imx6_set_int_mem_clk_lpm(true);
 403                 imx6_set_lpm(WAIT_CLOCKED);
 404                 break;
 405         default:
 406                 return -EINVAL;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int imx6q_pm_valid(suspend_state_t state)
 413 {
 414         return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
 415 }
 416
 417 static const struct platform_suspend_ops imx6q_pm_ops = {
 418         .enter = imx6q_pm_enter,
 419         .valid = imx6q_pm_valid,
 420 };
 421
 422 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
 423                                 const char *compat)
 424 {
 425         struct device_node *node;
 426         struct resource res;
 427         int ret = 0;
 428
 429         node = of_find_compatible_node(NULL, NULL, compat);
 430         if (!node) {
 431                 ret = -ENODEV;
 432                 goto out;
 433         }
 434
 435         ret = of_address_to_resource(node, 0, &res);
 436         if (ret)
 437                 goto put_node;
 438
 439         base->pbase = res.start;
 440         base->vbase = ioremap(res.start, resource_size(&res));
 441         if (!base->vbase)
 442                 ret = -ENOMEM;
 443
 444 put_node:
 445         of_node_put(node);
 446 out:
 447         return ret;
 448 }
 449
 450 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
 451 {
 452         phys_addr_t ocram_pbase;
 453         struct device_node *node;
 454         struct platform_device *pdev;
 455         struct imx6_cpu_pm_info *pm_info;
 456         struct gen_pool *ocram_pool;
 457         unsigned long ocram_base;
 458         int i, ret = 0;
 459         const u32 *mmdc_offset_array;
 460
 461         suspend_set_ops(&imx6q_pm_ops);
 462
 463         if (!socdata) {
 464                 pr_warn("%s: invalid argument!\n", __func__);
 465                 return -EINVAL;
 466         }
 467
 468         node = of_find_compatible_node(NULL, NULL, "mmio-sram");
 469         if (!node) {
 470                 pr_warn("%s: failed to find ocram node!\n", __func__);
 471                 return -ENODEV;
 472         }
 473
 474         pdev = of_find_device_by_node(node);
 475         if (!pdev) {
 476                 pr_warn("%s: failed to find ocram device!\n", __func__);
 477                 ret = -ENODEV;
 478                 goto put_node;
 479         }
 480
 481         ocram_pool = gen_pool_get(&pdev->dev, NULL);
 482         if (!ocram_pool) {
 483                 pr_warn("%s: ocram pool unavailable!\n", __func__);
 484                 ret = -ENODEV;
 485                 goto put_device;
 486         }
 487
 488         ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
 489         if (!ocram_base) {
 490                 pr_warn("%s: unable to alloc ocram!\n", __func__);
 491                 ret = -ENOMEM;
 492                 goto put_device;
 493         }
 494
 495         ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
 496
 497         suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
 498                 MX6Q_SUSPEND_OCRAM_SIZE, false);
 499
 500         memset(suspend_ocram_base, 0, sizeof(*pm_info));
 501         pm_info = suspend_ocram_base;
 502         pm_info->pbase = ocram_pbase;
 503         pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
 504         pm_info->pm_info_size = sizeof(*pm_info);
 505
 506         /*
 507          * ccm physical address is not used by asm code currently,
 508          * so get ccm virtual address directly.
 509          */
 510         pm_info->ccm_base.vbase = ccm_base;
 511
 512         ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
 513         if (ret) {
 514                 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
 515                 goto put_device;
 516         }
 517
 518         ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
 519         if (ret) {
 520                 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
 521                 goto src_map_failed;
 522         }
 523
 524         ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
 525         if (ret) {
 526                 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
 527                 goto iomuxc_map_failed;
 528         }
 529
 530         ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
 531         if (ret) {
 532                 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
 533                 goto gpc_map_failed;
 534         }
 535
 536         if (socdata->pl310_compat) {
 537                 ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
 538                 if (ret) {
 539                         pr_warn("%s: failed to get pl310-cache base %d!\n",
 540                                 __func__, ret);
 541                         goto pl310_cache_map_failed;
 542                 }
 543         }
 544
 545         pm_info->ddr_type = imx_mmdc_get_ddr_type();
 546         pm_info->mmdc_io_num = socdata->mmdc_io_num;
 547         mmdc_offset_array = socdata->mmdc_io_offset;
 548
 549         for (i = 0; i < pm_info->mmdc_io_num; i++) {
 550                 pm_info->mmdc_io_val[i][0] =
 551                         mmdc_offset_array[i];
 552                 pm_info->mmdc_io_val[i][1] =
 553                         readl_relaxed(pm_info->iomuxc_base.vbase +
 554                         mmdc_offset_array[i]);
 555         }
 556
 557         imx6_suspend_in_ocram_fn = fncpy(
 558                 suspend_ocram_base + sizeof(*pm_info),
 559                 &imx6_suspend,
 560                 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
 561
 562         goto put_device;
 563
 564 pl310_cache_map_failed:
 565         iounmap(pm_info->gpc_base.vbase);
 566 gpc_map_failed:
 567         iounmap(pm_info->iomuxc_base.vbase);
 568 iomuxc_map_failed:
 569         iounmap(pm_info->src_base.vbase);
 570 src_map_failed:
 571         iounmap(pm_info->mmdc_base.vbase);
 572 put_device:
 573         put_device(&pdev->dev);
 574 put_node:
 575         of_node_put(node);
 576
 577         return ret;
 578 }
 579
 580 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
 581                                         *socdata)
 582 {
 583         struct regmap *gpr;
 584         int ret;
 585
 586         WARN_ON(!ccm_base);
 587
 588         if (IS_ENABLED(CONFIG_SUSPEND)) {
 589                 ret = imx6q_suspend_init(socdata);
 590                 if (ret)
 591                         pr_warn("%s: No DDR LPM support with suspend %d!\n",
 592                                 __func__, ret);
 593         }
 594
 595         /*
 596          * This is for SW workaround step #1 of ERR007265, see comments
 597          * in imx6_set_lpm for details of this errata.
 598          * Force IOMUXC irq pending, so that the interrupt to GPC can be
 599          * used to deassert dsm_request signal when the signal gets
 600          * asserted unexpectedly.
 601          */
 602         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 603         if (!IS_ERR(gpr))
 604                 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
 605                                    IMX6Q_GPR1_GINT);
 606 }
 607
 608 static void imx6_pm_stby_poweroff(void)
 609 {
 610         gic_cpu_if_down(0);
 611         imx6_set_lpm(STOP_POWER_OFF);
 612         imx6q_suspend_finish(0);
 613
 614         mdelay(1000);
 615
 616         pr_emerg("Unable to poweroff system\n");
 617 }
 618
 619 static int imx6_pm_stby_poweroff_probe(void)
 620 {
 621         if (pm_power_off) {
 622                 pr_warn("%s: pm_power_off already claimed  %p %pf!\n",
 623                         __func__, pm_power_off, pm_power_off);
 624                 return -EBUSY;
 625         }
 626
 627         pm_power_off = imx6_pm_stby_poweroff;
 628         return 0;
 629 }
 630
 631 void __init imx6_pm_ccm_init(const char *ccm_compat)
 632 {
 633         struct device_node *np;
 634         u32 val;
 635
 636         np = of_find_compatible_node(NULL, NULL, ccm_compat);
 637         ccm_base = of_iomap(np, 0);
 638         BUG_ON(!ccm_base);
 639
 640         /*
 641          * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
 642          * clock being shut down unexpectedly by WAIT mode.
 643          */
 644         val = readl_relaxed(ccm_base + CLPCR);
 645         val &= ~BM_CLPCR_LPM;
 646         writel_relaxed(val, ccm_base + CLPCR);
 647
 648         if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
 649                 imx6_pm_stby_poweroff_probe();
 650 }
 651
 652 void __init imx6q_pm_init(void)
 653 {
 654         imx6_pm_common_init(&imx6q_pm_data);
 655 }
 656
 657 void __init imx6dl_pm_init(void)
 658 {
 659         imx6_pm_common_init(&imx6dl_pm_data);
 660 }
 661
 662 void __init imx6sl_pm_init(void)
 663 {
 664         imx6_pm_common_init(&imx6sl_pm_data);
 665 }
 666
 667 void __init imx6sx_pm_init(void)
 668 {
 669         imx6_pm_common_init(&imx6sx_pm_data);
 670 }
 671
 672 void __init imx6ul_pm_init(void)
 673 {
 674         imx6_pm_common_init(&imx6ul_pm_data);
 675 }