arch/arm/mach-imx/mmdc.c

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright 2011,2016 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_device.h>
  23 #include <linux/perf_event.h>
  24 #include <linux/slab.h>
  25
  26 #include "common.h"
  27
  28 #define MMDC_MAPSR              0x404
  29 #define BP_MMDC_MAPSR_PSD       0
  30 #define BP_MMDC_MAPSR_PSS       4
  31
  32 #define MMDC_MDMISC             0x18
  33 #define BM_MMDC_MDMISC_DDR_TYPE 0x18
  34 #define BP_MMDC_MDMISC_DDR_TYPE 0x3
  35
  36 #define TOTAL_CYCLES            0x0
  37 #define BUSY_CYCLES             0x1
  38 #define READ_ACCESSES           0x2
  39 #define WRITE_ACCESSES          0x3
  40 #define READ_BYTES              0x4
  41 #define WRITE_BYTES             0x5
  42
  43 /* Enables, resets, freezes, overflow profiling*/
  44 #define DBG_DIS                 0x0
  45 #define DBG_EN                  0x1
  46 #define DBG_RST                 0x2
  47 #define PRF_FRZ                 0x4
  48 #define CYC_OVF                 0x8
  49 #define PROFILE_SEL             0x10
  50
  51 #define MMDC_MADPCR0    0x410
  52 #define MMDC_MADPCR1    0x414
  53 #define MMDC_MADPSR0    0x418
  54 #define MMDC_MADPSR1    0x41C
  55 #define MMDC_MADPSR2    0x420
  56 #define MMDC_MADPSR3    0x424
  57 #define MMDC_MADPSR4    0x428
  58 #define MMDC_MADPSR5    0x42C
  59
  60 #define MMDC_NUM_COUNTERS       6
  61
  62 #define MMDC_FLAG_PROFILE_SEL   0x1
  63 #define MMDC_PRF_AXI_ID_CLEAR   0x0
  64
  65 #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
  66
  67 static int ddr_type;
  68
  69 struct fsl_mmdc_devtype_data {
  70         unsigned int flags;
  71 };
  72
  73 static const struct fsl_mmdc_devtype_data imx6q_data = {
  74 };
  75
  76 static const struct fsl_mmdc_devtype_data imx6qp_data = {
  77         .flags = MMDC_FLAG_PROFILE_SEL,
  78 };
  79
  80 static const struct of_device_id imx_mmdc_dt_ids[] = {
  81         { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
  82         { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
  83         { /* sentinel */ }
  84 };
  85
  86 #ifdef CONFIG_PERF_EVENTS
  87
  88 static enum cpuhp_state cpuhp_mmdc_state;
  89 static DEFINE_IDA(mmdc_ida);
  90
  91 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
  92 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
  93 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
  94 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
  95 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
  96 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
  97 PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
  98 PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05")
  99 PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB");
 100 PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001");
 101
 102 struct mmdc_pmu {
 103         struct pmu pmu;
 104         void __iomem *mmdc_base;
 105         cpumask_t cpu;
 106         struct hrtimer hrtimer;
 107         unsigned int active_events;
 108         struct device *dev;
 109         struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
 110         struct hlist_node node;
 111         struct fsl_mmdc_devtype_data *devtype_data;
 112         struct clk *mmdc_ipg_clk;
 113 };
 114
 115 /*
 116  * Polling period is set to one second, overflow of total-cycles (the fastest
 117  * increasing counter) takes ten seconds so one second is safe
 118  */
 119 static unsigned int mmdc_pmu_poll_period_us = 1000000;
 120
 121 module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint,
 122                 S_IRUGO | S_IWUSR);
 123
 124 static ktime_t mmdc_pmu_timer_period(void)
 125 {
 126         return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000);
 127 }
 128
 129 static ssize_t mmdc_pmu_cpumask_show(struct device *dev,
 130                 struct device_attribute *attr, char *buf)
 131 {
 132         struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev);
 133
 134         return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu);
 135 }
 136
 137 static struct device_attribute mmdc_pmu_cpumask_attr =
 138         __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL);
 139
 140 static struct attribute *mmdc_pmu_cpumask_attrs[] = {
 141         &mmdc_pmu_cpumask_attr.attr,
 142         NULL,
 143 };
 144
 145 static struct attribute_group mmdc_pmu_cpumask_attr_group = {
 146         .attrs = mmdc_pmu_cpumask_attrs,
 147 };
 148
 149 static struct attribute *mmdc_pmu_events_attrs[] = {
 150         &mmdc_pmu_total_cycles.attr.attr,
 151         &mmdc_pmu_busy_cycles.attr.attr,
 152         &mmdc_pmu_read_accesses.attr.attr,
 153         &mmdc_pmu_write_accesses.attr.attr,
 154         &mmdc_pmu_read_bytes.attr.attr,
 155         &mmdc_pmu_read_bytes_unit.attr.attr,
 156         &mmdc_pmu_read_bytes_scale.attr.attr,
 157         &mmdc_pmu_write_bytes.attr.attr,
 158         &mmdc_pmu_write_bytes_unit.attr.attr,
 159         &mmdc_pmu_write_bytes_scale.attr.attr,
 160         NULL,
 161 };
 162
 163 static struct attribute_group mmdc_pmu_events_attr_group = {
 164         .name = "events",
 165         .attrs = mmdc_pmu_events_attrs,
 166 };
 167
 168 PMU_FORMAT_ATTR(event, "config:0-63");
 169 PMU_FORMAT_ATTR(axi_id, "config1:0-63");
 170
 171 static struct attribute *mmdc_pmu_format_attrs[] = {
 172         &format_attr_event.attr,
 173         &format_attr_axi_id.attr,
 174         NULL,
 175 };
 176
 177 static struct attribute_group mmdc_pmu_format_attr_group = {
 178         .name = "format",
 179         .attrs = mmdc_pmu_format_attrs,
 180 };
 181
 182 static const struct attribute_group *attr_groups[] = {
 183         &mmdc_pmu_events_attr_group,
 184         &mmdc_pmu_format_attr_group,
 185         &mmdc_pmu_cpumask_attr_group,
 186         NULL,
 187 };
 188
 189 static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg)
 190 {
 191         void __iomem *mmdc_base, *reg;
 192
 193         mmdc_base = pmu_mmdc->mmdc_base;
 194
 195         switch (cfg) {
 196         case TOTAL_CYCLES:
 197                 reg = mmdc_base + MMDC_MADPSR0;
 198                 break;
 199         case BUSY_CYCLES:
 200                 reg = mmdc_base + MMDC_MADPSR1;
 201                 break;
 202         case READ_ACCESSES:
 203                 reg = mmdc_base + MMDC_MADPSR2;
 204                 break;
 205         case WRITE_ACCESSES:
 206                 reg = mmdc_base + MMDC_MADPSR3;
 207                 break;
 208         case READ_BYTES:
 209                 reg = mmdc_base + MMDC_MADPSR4;
 210                 break;
 211         case WRITE_BYTES:
 212                 reg = mmdc_base + MMDC_MADPSR5;
 213                 break;
 214         default:
 215                 return WARN_ONCE(1,
 216                         "invalid configuration %d for mmdc counter", cfg);
 217         }
 218         return readl(reg);
 219 }
 220
 221 static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
 222 {
 223         struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node);
 224         int target;
 225
 226         if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu))
 227                 return 0;
 228
 229         target = cpumask_any_but(cpu_online_mask, cpu);
 230         if (target >= nr_cpu_ids)
 231                 return 0;
 232
 233         perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target);
 234         cpumask_set_cpu(target, &pmu_mmdc->cpu);
 235
 236         return 0;
 237 }
 238
 239 static bool mmdc_pmu_group_event_is_valid(struct perf_event *event,
 240                                           struct pmu *pmu,
 241                                           unsigned long *used_counters)
 242 {
 243         int cfg = event->attr.config;
 244
 245         if (is_software_event(event))
 246                 return true;
 247
 248         if (event->pmu != pmu)
 249                 return false;
 250
 251         return !test_and_set_bit(cfg, used_counters);
 252 }
 253
 254 /*
 255  * Each event has a single fixed-purpose counter, so we can only have a
 256  * single active event for each at any point in time. Here we just check
 257  * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW
 258  * event numbers are valid.
 259  */
 260 static bool mmdc_pmu_group_is_valid(struct perf_event *event)
 261 {
 262         struct pmu *pmu = event->pmu;
 263         struct perf_event *leader = event->group_leader;
 264         struct perf_event *sibling;
 265         unsigned long counter_mask = 0;
 266
 267         set_bit(leader->attr.config, &counter_mask);
 268
 269         if (event != leader) {
 270                 if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask))
 271                         return false;
 272         }
 273
 274         for_each_sibling_event(sibling, leader) {
 275                 if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
 276                         return false;
 277         }
 278
 279         return true;
 280 }
 281
 282 static int mmdc_pmu_event_init(struct perf_event *event)
 283 {
 284         struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
 285         int cfg = event->attr.config;
 286
 287         if (event->attr.type != event->pmu->type)
 288                 return -ENOENT;
 289
 290         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
 291                 return -EOPNOTSUPP;
 292
 293         if (event->cpu < 0) {
 294                 dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n");
 295                 return -EOPNOTSUPP;
 296         }
 297
 298         if (event->attr.exclude_user            ||
 299                         event->attr.exclude_kernel      ||
 300                         event->attr.exclude_hv          ||
 301                         event->attr.exclude_idle        ||
 302                         event->attr.exclude_host        ||
 303                         event->attr.exclude_guest       ||
 304                         event->attr.sample_period)
 305                 return -EINVAL;
 306
 307         if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS)
 308                 return -EINVAL;
 309
 310         if (!mmdc_pmu_group_is_valid(event))
 311                 return -EINVAL;
 312
 313         event->cpu = cpumask_first(&pmu_mmdc->cpu);
 314         return 0;
 315 }
 316
 317 static void mmdc_pmu_event_update(struct perf_event *event)
 318 {
 319         struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
 320         struct hw_perf_event *hwc = &event->hw;
 321         u64 delta, prev_raw_count, new_raw_count;
 322
 323         do {
 324                 prev_raw_count = local64_read(&hwc->prev_count);
 325                 new_raw_count = mmdc_pmu_read_counter(pmu_mmdc,
 326                                                       event->attr.config);
 327         } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 328                 new_raw_count) != prev_raw_count);
 329
 330         delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
 331
 332         local64_add(delta, &event->count);
 333 }
 334
 335 static void mmdc_pmu_event_start(struct perf_event *event, int flags)
 336 {
 337         struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
 338         struct hw_perf_event *hwc = &event->hw;
 339         void __iomem *mmdc_base, *reg;
 340         u32 val;
 341
 342         mmdc_base = pmu_mmdc->mmdc_base;
 343         reg = mmdc_base + MMDC_MADPCR0;
 344
 345         /*
 346          * hrtimer is required because mmdc does not provide an interrupt so
 347          * polling is necessary
 348          */
 349         hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(),
 350                         HRTIMER_MODE_REL_PINNED);
 351
 352         local64_set(&hwc->prev_count, 0);
 353
 354         writel(DBG_RST, reg);
 355
 356         /*
 357          * Write the AXI id parameter to MADPCR1.
 358          */
 359         val = event->attr.config1;
 360         reg = mmdc_base + MMDC_MADPCR1;
 361         writel(val, reg);
 362
 363         reg = mmdc_base + MMDC_MADPCR0;
 364         val = DBG_EN;
 365         if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
 366                 val |= PROFILE_SEL;
 367
 368         writel(val, reg);
 369 }
 370
 371 static int mmdc_pmu_event_add(struct perf_event *event, int flags)
 372 {
 373         struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
 374         struct hw_perf_event *hwc = &event->hw;
 375
 376         int cfg = event->attr.config;
 377
 378         if (flags & PERF_EF_START)
 379                 mmdc_pmu_event_start(event, flags);
 380
 381         if (pmu_mmdc->mmdc_events[cfg] != NULL)
 382                 return -EAGAIN;
 383
 384         pmu_mmdc->mmdc_events[cfg] = event;
 385         pmu_mmdc->active_events++;
 386
 387         local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg));
 388
 389         return 0;
 390 }
 391
 392 static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
 393 {
 394         struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
 395         void __iomem *mmdc_base, *reg;
 396
 397         mmdc_base = pmu_mmdc->mmdc_base;
 398         reg = mmdc_base + MMDC_MADPCR0;
 399
 400         writel(PRF_FRZ, reg);
 401
 402         reg = mmdc_base + MMDC_MADPCR1;
 403         writel(MMDC_PRF_AXI_ID_CLEAR, reg);
 404
 405         mmdc_pmu_event_update(event);
 406 }
 407
 408 static void mmdc_pmu_event_del(struct perf_event *event, int flags)
 409 {
 410         struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
 411         int cfg = event->attr.config;
 412
 413         pmu_mmdc->mmdc_events[cfg] = NULL;
 414         pmu_mmdc->active_events--;
 415
 416         if (pmu_mmdc->active_events == 0)
 417                 hrtimer_cancel(&pmu_mmdc->hrtimer);
 418
 419         mmdc_pmu_event_stop(event, PERF_EF_UPDATE);
 420 }
 421
 422 static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc)
 423 {
 424         int i;
 425
 426         for (i = 0; i < MMDC_NUM_COUNTERS; i++) {
 427                 struct perf_event *event = pmu_mmdc->mmdc_events[i];
 428
 429                 if (event)
 430                         mmdc_pmu_event_update(event);
 431         }
 432 }
 433
 434 static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
 435 {
 436         struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu,
 437                         hrtimer);
 438
 439         mmdc_pmu_overflow_handler(pmu_mmdc);
 440         hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period());
 441
 442         return HRTIMER_RESTART;
 443 }
 444
 445 static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
 446                 void __iomem *mmdc_base, struct device *dev)
 447 {
 448         int mmdc_num;
 449
 450         *pmu_mmdc = (struct mmdc_pmu) {
 451                 .pmu = (struct pmu) {
 452                         .task_ctx_nr    = perf_invalid_context,
 453                         .attr_groups    = attr_groups,
 454                         .event_init     = mmdc_pmu_event_init,
 455                         .add            = mmdc_pmu_event_add,
 456                         .del            = mmdc_pmu_event_del,
 457                         .start          = mmdc_pmu_event_start,
 458                         .stop           = mmdc_pmu_event_stop,
 459                         .read           = mmdc_pmu_event_update,
 460                 },
 461                 .mmdc_base = mmdc_base,
 462                 .dev = dev,
 463                 .active_events = 0,
 464         };
 465
 466         mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
 467
 468         return mmdc_num;
 469 }
 470
 471 static int imx_mmdc_remove(struct platform_device *pdev)
 472 {
 473         struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
 474
 475         cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
 476         perf_pmu_unregister(&pmu_mmdc->pmu);
 477         iounmap(pmu_mmdc->mmdc_base);
 478         clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk);
 479         kfree(pmu_mmdc);
 480         return 0;
 481 }
 482
 483 static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base,
 484                               struct clk *mmdc_ipg_clk)
 485 {
 486         struct mmdc_pmu *pmu_mmdc;
 487         char *name;
 488         int mmdc_num;
 489         int ret;
 490         const struct of_device_id *of_id =
 491                 of_match_device(imx_mmdc_dt_ids, &pdev->dev);
 492
 493         pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
 494         if (!pmu_mmdc) {
 495                 pr_err("failed to allocate PMU device!\n");
 496                 return -ENOMEM;
 497         }
 498
 499         /* The first instance registers the hotplug state */
 500         if (!cpuhp_mmdc_state) {
 501                 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
 502                                               "perf/arm/mmdc:online", NULL,
 503                                               mmdc_pmu_offline_cpu);
 504                 if (ret < 0) {
 505                         pr_err("cpuhp_setup_state_multi failed\n");
 506                         goto pmu_free;
 507                 }
 508                 cpuhp_mmdc_state = ret;
 509         }
 510
 511         mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
 512         pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
 513         if (mmdc_num == 0)
 514                 name = "mmdc";
 515         else
 516                 name = devm_kasprintf(&pdev->dev,
 517                                 GFP_KERNEL, "mmdc%d", mmdc_num);
 518
 519         pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
 520
 521         hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
 522                         HRTIMER_MODE_REL);
 523         pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler;
 524
 525         cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu);
 526
 527         /* Register the pmu instance for cpu hotplug */
 528         cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
 529
 530         ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1);
 531         if (ret)
 532                 goto pmu_register_err;
 533
 534         platform_set_drvdata(pdev, pmu_mmdc);
 535         return 0;
 536
 537 pmu_register_err:
 538         pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
 539         cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
 540         hrtimer_cancel(&pmu_mmdc->hrtimer);
 541 pmu_free:
 542         kfree(pmu_mmdc);
 543         return ret;
 544 }
 545
 546 #else
 547 #define imx_mmdc_remove NULL
 548 #define imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk) 0
 549 #endif
 550
 551 static int imx_mmdc_probe(struct platform_device *pdev)
 552 {
 553         struct device_node *np = pdev->dev.of_node;
 554         void __iomem *mmdc_base, *reg;
 555         struct clk *mmdc_ipg_clk;
 556         u32 val;
 557         int err;
 558
 559         /* the ipg clock is optional */
 560         mmdc_ipg_clk = devm_clk_get(&pdev->dev, NULL);
 561         if (IS_ERR(mmdc_ipg_clk))
 562                 mmdc_ipg_clk = NULL;
 563
 564         err = clk_prepare_enable(mmdc_ipg_clk);
 565         if (err) {
 566                 dev_err(&pdev->dev, "Unable to enable mmdc ipg clock.\n");
 567                 return err;
 568         }
 569
 570         mmdc_base = of_iomap(np, 0);
 571         WARN_ON(!mmdc_base);
 572
 573         reg = mmdc_base + MMDC_MDMISC;
 574         /* Get ddr type */
 575         val = readl_relaxed(reg);
 576         ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
 577                  BP_MMDC_MDMISC_DDR_TYPE;
 578
 579         reg = mmdc_base + MMDC_MAPSR;
 580
 581         /* Enable automatic power saving */
 582         val = readl_relaxed(reg);
 583         val &= ~(1 << BP_MMDC_MAPSR_PSD);
 584         writel_relaxed(val, reg);
 585
 586         err = imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk);
 587         if (err) {
 588                 iounmap(mmdc_base);
 589                 clk_disable_unprepare(mmdc_ipg_clk);
 590         }
 591
 592         return err;
 593 }
 594
 595 int imx_mmdc_get_ddr_type(void)
 596 {
 597         return ddr_type;
 598 }
 599
 600 static struct platform_driver imx_mmdc_driver = {
 601         .driver         = {
 602                 .name   = "imx-mmdc",
 603                 .of_match_table = imx_mmdc_dt_ids,
 604         },
 605         .probe          = imx_mmdc_probe,
 606         .remove         = imx_mmdc_remove,
 607 };
 608
 609 static int __init imx_mmdc_init(void)
 610 {
 611         return platform_driver_register(&imx_mmdc_driver);
 612 }
 613 postcore_initcall(imx_mmdc_init);