GNU Linux-libre 4.19.314-gnu1
[releases.git] / arch / arm / mach-imx / mach-mx27ads.c
1 /*
2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 #include <linux/gpio/driver.h>
17 /* Needed for gpio_to_irq() */
18 #include <linux/gpio.h>
19 #include <linux/platform_device.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/map.h>
22 #include <linux/mtd/partitions.h>
23 #include <linux/mtd/physmap.h>
24 #include <linux/i2c.h>
25 #include <linux/irq.h>
26
27 #include <linux/regulator/fixed.h>
28 #include <linux/regulator/machine.h>
29
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/time.h>
33 #include <asm/mach/map.h>
34
35 #include "common.h"
36 #include "devices-imx27.h"
37 #include "hardware.h"
38 #include "iomux-mx27.h"
39
40 /*
41  * Base address of PBC controller, CS4
42  */
43 #define PBC_BASE_ADDRESS        0xf4300000
44 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
45                 (PBC_BASE_ADDRESS + (offset))
46
47 /* When the PBC address connection is fixed in h/w, defined as 1 */
48 #define PBC_ADDR_SH             0
49
50 /* Offsets for the PBC Controller register */
51 /*
52  * PBC Board version register offset
53  */
54 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
55 /*
56  * PBC Board control register 1 set address.
57  */
58 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
59 /*
60  * PBC Board control register 1 clear address.
61  */
62 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
63
64 /* PBC Board Control Register 1 bit definitions */
65 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
66
67 /* to determine the correct external crystal reference */
68 #define CKIH_27MHZ_BIT_SET      (1 << 3)
69
70 static const int mx27ads_pins[] __initconst = {
71         /* UART0 */
72         PE12_PF_UART1_TXD,
73         PE13_PF_UART1_RXD,
74         PE14_PF_UART1_CTS,
75         PE15_PF_UART1_RTS,
76         /* UART1 */
77         PE3_PF_UART2_CTS,
78         PE4_PF_UART2_RTS,
79         PE6_PF_UART2_TXD,
80         PE7_PF_UART2_RXD,
81         /* UART2 */
82         PE8_PF_UART3_TXD,
83         PE9_PF_UART3_RXD,
84         PE10_PF_UART3_CTS,
85         PE11_PF_UART3_RTS,
86         /* UART3 */
87         PB26_AF_UART4_RTS,
88         PB28_AF_UART4_TXD,
89         PB29_AF_UART4_CTS,
90         PB31_AF_UART4_RXD,
91         /* UART4 */
92         PB18_AF_UART5_TXD,
93         PB19_AF_UART5_RXD,
94         PB20_AF_UART5_CTS,
95         PB21_AF_UART5_RTS,
96         /* UART5 */
97         PB10_AF_UART6_TXD,
98         PB12_AF_UART6_CTS,
99         PB11_AF_UART6_RXD,
100         PB13_AF_UART6_RTS,
101         /* FEC */
102         PD0_AIN_FEC_TXD0,
103         PD1_AIN_FEC_TXD1,
104         PD2_AIN_FEC_TXD2,
105         PD3_AIN_FEC_TXD3,
106         PD4_AOUT_FEC_RX_ER,
107         PD5_AOUT_FEC_RXD1,
108         PD6_AOUT_FEC_RXD2,
109         PD7_AOUT_FEC_RXD3,
110         PD8_AF_FEC_MDIO,
111         PD9_AIN_FEC_MDC,
112         PD10_AOUT_FEC_CRS,
113         PD11_AOUT_FEC_TX_CLK,
114         PD12_AOUT_FEC_RXD0,
115         PD13_AOUT_FEC_RX_DV,
116         PD14_AOUT_FEC_RX_CLK,
117         PD15_AOUT_FEC_COL,
118         PD16_AIN_FEC_TX_ER,
119         PF23_AIN_FEC_TX_EN,
120         /* I2C2 */
121         PC5_PF_I2C2_SDA,
122         PC6_PF_I2C2_SCL,
123         /* FB */
124         PA5_PF_LSCLK,
125         PA6_PF_LD0,
126         PA7_PF_LD1,
127         PA8_PF_LD2,
128         PA9_PF_LD3,
129         PA10_PF_LD4,
130         PA11_PF_LD5,
131         PA12_PF_LD6,
132         PA13_PF_LD7,
133         PA14_PF_LD8,
134         PA15_PF_LD9,
135         PA16_PF_LD10,
136         PA17_PF_LD11,
137         PA18_PF_LD12,
138         PA19_PF_LD13,
139         PA20_PF_LD14,
140         PA21_PF_LD15,
141         PA22_PF_LD16,
142         PA23_PF_LD17,
143         PA24_PF_REV,
144         PA25_PF_CLS,
145         PA26_PF_PS,
146         PA27_PF_SPL_SPR,
147         PA28_PF_HSYNC,
148         PA29_PF_VSYNC,
149         PA30_PF_CONTRAST,
150         PA31_PF_OE_ACD,
151         /* OWIRE */
152         PE16_AF_OWIRE,
153         /* SDHC1*/
154         PE18_PF_SD1_D0,
155         PE19_PF_SD1_D1,
156         PE20_PF_SD1_D2,
157         PE21_PF_SD1_D3,
158         PE22_PF_SD1_CMD,
159         PE23_PF_SD1_CLK,
160         /* SDHC2*/
161         PB4_PF_SD2_D0,
162         PB5_PF_SD2_D1,
163         PB6_PF_SD2_D2,
164         PB7_PF_SD2_D3,
165         PB8_PF_SD2_CMD,
166         PB9_PF_SD2_CLK,
167 };
168
169 static const struct mxc_nand_platform_data
170 mx27ads_nand_board_info __initconst = {
171         .width = 1,
172         .hw_ecc = 1,
173 };
174
175 /* ADS's NOR flash */
176 static struct physmap_flash_data mx27ads_flash_data = {
177         .width = 2,
178 };
179
180 static struct resource mx27ads_flash_resource = {
181         .start = 0xc0000000,
182         .end = 0xc0000000 + 0x02000000 - 1,
183         .flags = IORESOURCE_MEM,
184
185 };
186
187 static struct platform_device mx27ads_nor_mtd_device = {
188         .name = "physmap-flash",
189         .id = 0,
190         .dev = {
191                 .platform_data = &mx27ads_flash_data,
192         },
193         .num_resources = 1,
194         .resource = &mx27ads_flash_resource,
195 };
196
197 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
198         .bitrate = 100000,
199 };
200
201 static struct i2c_board_info mx27ads_i2c_devices[] = {
202 };
203
204 static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
205 {
206         if (value)
207                 imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
208         else
209                 imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
210 }
211
212 static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
213 {
214         return 0;
215 }
216
217 #define MX27ADS_LCD_GPIO        (6 * 32)
218
219 static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
220         REGULATOR_SUPPLY("lcd", "imx-fb.0");
221
222 static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
223         .constraints    = {
224                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
225 },
226         .consumer_supplies      = &mx27ads_lcd_regulator_consumer,
227         .num_consumer_supplies  = 1,
228 };
229
230 static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
231         .supply_name    = "LCD",
232         .microvolts     = 3300000,
233         .gpio           = MX27ADS_LCD_GPIO,
234         .init_data      = &mx27ads_lcd_regulator_init_data,
235 };
236
237 static void __init mx27ads_regulator_init(void)
238 {
239         struct gpio_chip *vchip;
240
241         vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
242         vchip->owner            = THIS_MODULE;
243         vchip->label            = "LCD";
244         vchip->base             = MX27ADS_LCD_GPIO;
245         vchip->ngpio            = 1;
246         vchip->direction_output = vgpio_dir_out;
247         vchip->set              = vgpio_set;
248         gpiochip_add_data(vchip, NULL);
249
250         platform_device_register_data(NULL, "reg-fixed-voltage",
251                                       PLATFORM_DEVID_AUTO,
252                                       &mx27ads_lcd_regulator_pdata,
253                                       sizeof(mx27ads_lcd_regulator_pdata));
254 }
255
256 static struct imx_fb_videomode mx27ads_modes[] = {
257         {
258                 .mode = {
259                         .name           = "Sharp-LQ035Q7",
260                         .refresh        = 60,
261                         .xres           = 240,
262                         .yres           = 320,
263                         .pixclock       = 188679, /* in ps (5.3MHz) */
264                         .hsync_len      = 1,
265                         .left_margin    = 9,
266                         .right_margin   = 16,
267                         .vsync_len      = 1,
268                         .upper_margin   = 7,
269                         .lower_margin   = 9,
270                 },
271                 .bpp            = 16,
272                 .pcr            = 0xFB008BC0,
273         },
274 };
275
276 static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
277         .mode = mx27ads_modes,
278         .num_modes = ARRAY_SIZE(mx27ads_modes),
279
280         /*
281          * - HSYNC active high
282          * - VSYNC active high
283          * - clk notenabled while idle
284          * - clock inverted
285          * - data not inverted
286          * - data enable low active
287          * - enable sharp mode
288          */
289         .pwmr           = 0x00A903FF,
290         .lscr1          = 0x00120300,
291         .dmacr          = 0x00020010,
292 };
293
294 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
295                               void *data)
296 {
297         return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
298                            IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
299 }
300
301 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
302                               void *data)
303 {
304         return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
305                            IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
306 }
307
308 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
309 {
310         free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
311 }
312
313 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
314 {
315         free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
316 }
317
318 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
319         .init = mx27ads_sdhc1_init,
320         .exit = mx27ads_sdhc1_exit,
321 };
322
323 static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
324         .init = mx27ads_sdhc2_init,
325         .exit = mx27ads_sdhc2_exit,
326 };
327
328 static struct platform_device *platform_devices[] __initdata = {
329         &mx27ads_nor_mtd_device,
330 };
331
332 static const struct imxuart_platform_data uart_pdata __initconst = {
333         .flags = IMXUART_HAVE_RTSCTS,
334 };
335
336 static void __init mx27ads_board_init(void)
337 {
338         imx27_soc_init();
339
340         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
341                         "mx27ads");
342
343         imx27_add_imx_uart0(&uart_pdata);
344         imx27_add_imx_uart1(&uart_pdata);
345         imx27_add_imx_uart2(&uart_pdata);
346         imx27_add_imx_uart3(&uart_pdata);
347         imx27_add_imx_uart4(&uart_pdata);
348         imx27_add_imx_uart5(&uart_pdata);
349         imx27_add_mxc_nand(&mx27ads_nand_board_info);
350
351         /* only the i2c master 1 is used on this CPU card */
352         i2c_register_board_info(1, mx27ads_i2c_devices,
353                                 ARRAY_SIZE(mx27ads_i2c_devices));
354         imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
355         imx27_add_imx_fb(&mx27ads_fb_data);
356
357         imx27_add_fec(NULL);
358         imx27_add_mxc_w1();
359 }
360
361 static void __init mx27ads_late_init(void)
362 {
363         mx27ads_regulator_init();
364
365         imx27_add_mxc_mmc(0, &sdhc1_pdata);
366         imx27_add_mxc_mmc(1, &sdhc2_pdata);
367
368         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
369 }
370
371 static void __init mx27ads_timer_init(void)
372 {
373         unsigned long fref = 26000000;
374
375         if ((imx_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
376                 fref = 27000000;
377
378         mx27_clocks_init(fref);
379 }
380
381 static struct map_desc mx27ads_io_desc[] __initdata = {
382         {
383                 .virtual = PBC_BASE_ADDRESS,
384                 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
385                 .length = SZ_1M,
386                 .type = MT_DEVICE,
387         },
388 };
389
390 static void __init mx27ads_map_io(void)
391 {
392         mx27_map_io();
393         iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
394 }
395
396 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
397         /* maintainer: Freescale Semiconductor, Inc. */
398         .atag_offset = 0x100,
399         .map_io = mx27ads_map_io,
400         .init_early = imx27_init_early,
401         .init_irq = mx27_init_irq,
402         .init_time      = mx27ads_timer_init,
403         .init_machine = mx27ads_board_init,
404         .init_late      = mx27ads_late_init,
405         .restart        = mxc_restart,
406 MACHINE_END