GNU Linux-libre 4.19.314-gnu1
[releases.git] / arch / arm / mach-highbank / sysregs.h
1 /*
2  * Copyright 2011 Calxeda, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 #ifndef _MACH_HIGHBANK__SYSREGS_H_
17 #define _MACH_HIGHBANK__SYSREGS_H_
18
19 #include <linux/io.h>
20 #include <linux/smp.h>
21 #include <asm/smp_plat.h>
22 #include <asm/smp_scu.h>
23 #include "core.h"
24
25 extern void __iomem *sregs_base;
26
27 #define HB_SREG_A9_PWR_REQ              0xf00
28 #define HB_SREG_A9_BOOT_STAT            0xf04
29 #define HB_SREG_A9_BOOT_DATA            0xf08
30
31 #define HB_PWR_SUSPEND                  0
32 #define HB_PWR_SOFT_RESET               1
33 #define HB_PWR_HARD_RESET               2
34 #define HB_PWR_SHUTDOWN                 3
35
36 #define SREG_CPU_PWR_CTRL(c)            (0x200 + ((c) * 4))
37
38 static inline void highbank_set_core_pwr(void)
39 {
40         int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
41         if (scu_base_addr)
42                 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
43         else
44                 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
45 }
46
47 static inline void highbank_clear_core_pwr(void)
48 {
49         int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
50         if (scu_base_addr)
51                 scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
52         else
53                 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
54 }
55
56 static inline void highbank_set_pwr_suspend(void)
57 {
58         writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
59         highbank_set_core_pwr();
60 }
61
62 static inline void highbank_set_pwr_shutdown(void)
63 {
64         writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
65         highbank_set_core_pwr();
66 }
67
68 static inline void highbank_set_pwr_soft_reset(void)
69 {
70         writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
71         highbank_set_core_pwr();
72 }
73
74 static inline void highbank_set_pwr_hard_reset(void)
75 {
76         writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
77         highbank_set_core_pwr();
78 }
79
80 static inline void highbank_clear_pwr_request(void)
81 {
82         writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
83         highbank_clear_core_pwr();
84 }
85
86 #endif