arch/arm/mach-exynos/suspend.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Suspend support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25 #include <linux/err.h>
  26 #include <linux/regulator/machine.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/hardware/cache-l2x0.h>
  30 #include <asm/firmware.h>
  31 #include <asm/mcpm.h>
  32 #include <asm/smp_scu.h>
  33 #include <asm/suspend.h>
  34
  35 #include <plat/pm-common.h>
  36
  37 #include "common.h"
  38 #include "exynos-pmu.h"
  39 #include "regs-pmu.h"
  40 #include "regs-srom.h"
  41
  42 #define REG_TABLE_END (-1U)
  43
  44 #define EXYNOS5420_CPU_STATE    0x28
  45
  46 /**
  47  * struct exynos_wkup_irq - PMU IRQ to mask mapping
  48  * @hwirq: Hardware IRQ signal of the PMU
  49  * @mask: Mask in PMU wake-up mask register
  50  */
  51 struct exynos_wkup_irq {
  52         unsigned int hwirq;
  53         u32 mask;
  54 };
  55
  56 static struct sleep_save exynos_core_save[] = {
  57         /* SROM side */
  58         SAVE_ITEM(S5P_SROM_BW),
  59         SAVE_ITEM(S5P_SROM_BC0),
  60         SAVE_ITEM(S5P_SROM_BC1),
  61         SAVE_ITEM(S5P_SROM_BC2),
  62         SAVE_ITEM(S5P_SROM_BC3),
  63 };
  64
  65 struct exynos_pm_data {
  66         const struct exynos_wkup_irq *wkup_irq;
  67         unsigned int wake_disable_mask;
  68         unsigned int *release_ret_regs;
  69
  70         void (*pm_prepare)(void);
  71         void (*pm_resume_prepare)(void);
  72         void (*pm_resume)(void);
  73         int (*pm_suspend)(void);
  74         int (*cpu_suspend)(unsigned long);
  75 };
  76
  77 static const struct exynos_pm_data *pm_data;
  78
  79 static int exynos5420_cpu_state;
  80 static unsigned int exynos_pmu_spare3;
  81
  82 /*
  83  * GIC wake-up support
  84  */
  85
  86 static u32 exynos_irqwake_intmask = 0xffffffff;
  87
  88 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
  89         { 73, BIT(1) }, /* RTC alarm */
  90         { 74, BIT(2) }, /* RTC tick */
  91         { /* sentinel */ },
  92 };
  93
  94 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  95         { 44, BIT(1) }, /* RTC alarm */
  96         { 45, BIT(2) }, /* RTC tick */
  97         { /* sentinel */ },
  98 };
  99
 100 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
 101         { 43, BIT(1) }, /* RTC alarm */
 102         { 44, BIT(2) }, /* RTC tick */
 103         { /* sentinel */ },
 104 };
 105
 106 static unsigned int exynos_release_ret_regs[] = {
 107         S5P_PAD_RET_MAUDIO_OPTION,
 108         S5P_PAD_RET_GPIO_OPTION,
 109         S5P_PAD_RET_UART_OPTION,
 110         S5P_PAD_RET_MMCA_OPTION,
 111         S5P_PAD_RET_MMCB_OPTION,
 112         S5P_PAD_RET_EBIA_OPTION,
 113         S5P_PAD_RET_EBIB_OPTION,
 114         REG_TABLE_END,
 115 };
 116
 117 static unsigned int exynos3250_release_ret_regs[] = {
 118         S5P_PAD_RET_MAUDIO_OPTION,
 119         S5P_PAD_RET_GPIO_OPTION,
 120         S5P_PAD_RET_UART_OPTION,
 121         S5P_PAD_RET_MMCA_OPTION,
 122         S5P_PAD_RET_MMCB_OPTION,
 123         S5P_PAD_RET_EBIA_OPTION,
 124         S5P_PAD_RET_EBIB_OPTION,
 125         S5P_PAD_RET_MMC2_OPTION,
 126         S5P_PAD_RET_SPI_OPTION,
 127         REG_TABLE_END,
 128 };
 129
 130 static unsigned int exynos5420_release_ret_regs[] = {
 131         EXYNOS_PAD_RET_DRAM_OPTION,
 132         EXYNOS_PAD_RET_MAUDIO_OPTION,
 133         EXYNOS_PAD_RET_JTAG_OPTION,
 134         EXYNOS5420_PAD_RET_GPIO_OPTION,
 135         EXYNOS5420_PAD_RET_UART_OPTION,
 136         EXYNOS5420_PAD_RET_MMCA_OPTION,
 137         EXYNOS5420_PAD_RET_MMCB_OPTION,
 138         EXYNOS5420_PAD_RET_MMCC_OPTION,
 139         EXYNOS5420_PAD_RET_HSI_OPTION,
 140         EXYNOS_PAD_RET_EBIA_OPTION,
 141         EXYNOS_PAD_RET_EBIB_OPTION,
 142         EXYNOS5420_PAD_RET_SPI_OPTION,
 143         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
 144         REG_TABLE_END,
 145 };
 146
 147 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 148 {
 149         const struct exynos_wkup_irq *wkup_irq;
 150
 151         if (!pm_data->wkup_irq)
 152                 return -ENOENT;
 153         wkup_irq = pm_data->wkup_irq;
 154
 155         while (wkup_irq->mask) {
 156                 if (wkup_irq->hwirq == data->hwirq) {
 157                         if (!state)
 158                                 exynos_irqwake_intmask |= wkup_irq->mask;
 159                         else
 160                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
 161                         return 0;
 162                 }
 163                 ++wkup_irq;
 164         }
 165
 166         return -ENOENT;
 167 }
 168
 169 static struct irq_chip exynos_pmu_chip = {
 170         .name                   = "PMU",
 171         .irq_eoi                = irq_chip_eoi_parent,
 172         .irq_mask               = irq_chip_mask_parent,
 173         .irq_unmask             = irq_chip_unmask_parent,
 174         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 175         .irq_set_wake           = exynos_irq_set_wake,
 176 #ifdef CONFIG_SMP
 177         .irq_set_affinity       = irq_chip_set_affinity_parent,
 178 #endif
 179 };
 180
 181 static int exynos_pmu_domain_translate(struct irq_domain *d,
 182                                        struct irq_fwspec *fwspec,
 183                                        unsigned long *hwirq,
 184                                        unsigned int *type)
 185 {
 186         if (is_of_node(fwspec->fwnode)) {
 187                 if (fwspec->param_count != 3)
 188                         return -EINVAL;
 189
 190                 /* No PPI should point to this domain */
 191                 if (fwspec->param[0] != 0)
 192                         return -EINVAL;
 193
 194                 *hwirq = fwspec->param[1];
 195                 *type = fwspec->param[2];
 196                 return 0;
 197         }
 198
 199         return -EINVAL;
 200 }
 201
 202 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
 203                                    unsigned int virq,
 204                                    unsigned int nr_irqs, void *data)
 205 {
 206         struct irq_fwspec *fwspec = data;
 207         struct irq_fwspec parent_fwspec;
 208         irq_hw_number_t hwirq;
 209         int i;
 210
 211         if (fwspec->param_count != 3)
 212                 return -EINVAL; /* Not GIC compliant */
 213         if (fwspec->param[0] != 0)
 214                 return -EINVAL; /* No PPI should point to this domain */
 215
 216         hwirq = fwspec->param[1];
 217
 218         for (i = 0; i < nr_irqs; i++)
 219                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 220                                               &exynos_pmu_chip, NULL);
 221
 222         parent_fwspec = *fwspec;
 223         parent_fwspec.fwnode = domain->parent->fwnode;
 224         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 225                                             &parent_fwspec);
 226 }
 227
 228 static const struct irq_domain_ops exynos_pmu_domain_ops = {
 229         .translate      = exynos_pmu_domain_translate,
 230         .alloc          = exynos_pmu_domain_alloc,
 231         .free           = irq_domain_free_irqs_common,
 232 };
 233
 234 static int __init exynos_pmu_irq_init(struct device_node *node,
 235                                       struct device_node *parent)
 236 {
 237         struct irq_domain *parent_domain, *domain;
 238
 239         if (!parent) {
 240                 pr_err("%s: no parent, giving up\n", node->full_name);
 241                 return -ENODEV;
 242         }
 243
 244         parent_domain = irq_find_host(parent);
 245         if (!parent_domain) {
 246                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
 247                 return -ENXIO;
 248         }
 249
 250         pmu_base_addr = of_iomap(node, 0);
 251
 252         if (!pmu_base_addr) {
 253                 pr_err("%s: failed to find exynos pmu register\n",
 254                        node->full_name);
 255                 return -ENOMEM;
 256         }
 257
 258         domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
 259                                           node, &exynos_pmu_domain_ops,
 260                                           NULL);
 261         if (!domain) {
 262                 iounmap(pmu_base_addr);
 263                 pmu_base_addr = NULL;
 264                 return -ENOMEM;
 265         }
 266
 267         return 0;
 268 }
 269
 270 #define EXYNOS_PMU_IRQ(symbol, name)    IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
 271
 272 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
 273 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
 274 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
 275 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
 276 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
 277 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
 278 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
 279
 280 static int exynos_cpu_do_idle(void)
 281 {
 282         /* issue the standby signal into the pm unit. */
 283         cpu_do_idle();
 284
 285         pr_info("Failed to suspend the system\n");
 286         return 1; /* Aborting suspend */
 287 }
 288 static void exynos_flush_cache_all(void)
 289 {
 290         flush_cache_all();
 291         outer_flush_all();
 292 }
 293
 294 static int exynos_cpu_suspend(unsigned long arg)
 295 {
 296         exynos_flush_cache_all();
 297         return exynos_cpu_do_idle();
 298 }
 299
 300 static int exynos3250_cpu_suspend(unsigned long arg)
 301 {
 302         flush_cache_all();
 303         return exynos_cpu_do_idle();
 304 }
 305
 306 static int exynos5420_cpu_suspend(unsigned long arg)
 307 {
 308         /* MCPM works with HW CPU identifiers */
 309         unsigned int mpidr = read_cpuid_mpidr();
 310         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 311         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 312
 313         __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 314
 315         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 316                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
 317                 mcpm_cpu_suspend();
 318         }
 319
 320         pr_info("Failed to suspend the system\n");
 321
 322         /* return value != 0 means failure */
 323         return 1;
 324 }
 325
 326 static void exynos_pm_set_wakeup_mask(void)
 327 {
 328         /* Set wake-up mask registers */
 329         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 330         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 331 }
 332
 333 static void exynos_pm_enter_sleep_mode(void)
 334 {
 335         /* Set value of power down register for sleep mode */
 336         exynos_sys_powerdown_conf(SYS_SLEEP);
 337         pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
 338 }
 339
 340 static void exynos_pm_prepare(void)
 341 {
 342         exynos_set_delayed_reset_assertion(false);
 343
 344         /* Set wake-up mask registers */
 345         exynos_pm_set_wakeup_mask();
 346
 347         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 348
 349         exynos_pm_enter_sleep_mode();
 350
 351         /* ensure at least INFORM0 has the resume address */
 352         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 353 }
 354
 355 static void exynos3250_pm_prepare(void)
 356 {
 357         unsigned int tmp;
 358
 359         /* Set wake-up mask registers */
 360         exynos_pm_set_wakeup_mask();
 361
 362         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
 363         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 364         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
 365
 366         exynos_pm_enter_sleep_mode();
 367
 368         /* ensure at least INFORM0 has the resume address */
 369         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 370 }
 371
 372 static void exynos5420_pm_prepare(void)
 373 {
 374         unsigned int tmp;
 375
 376         /* Set wake-up mask registers */
 377         exynos_pm_set_wakeup_mask();
 378
 379         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 380
 381         exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
 382         /*
 383          * The cpu state needs to be saved and restored so that the
 384          * secondary CPUs will enter low power start. Though the U-Boot
 385          * is setting the cpu state with low power flag, the kernel
 386          * needs to restore it back in case, the primary cpu fails to
 387          * suspend for any reason.
 388          */
 389         exynos5420_cpu_state = __raw_readl(sysram_base_addr +
 390                                                 EXYNOS5420_CPU_STATE);
 391
 392         exynos_pm_enter_sleep_mode();
 393
 394         /* ensure at least INFORM0 has the resume address */
 395         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 396                 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
 397
 398         tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
 399         tmp &= ~EXYNOS5_USE_RETENTION;
 400         pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
 401
 402         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 403         tmp |= EXYNOS5420_UFS;
 404         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 405
 406         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 407         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
 408         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
 409
 410         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 411         tmp |= EXYNOS5420_EMULATION;
 412         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 413
 414         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 415         tmp |= EXYNOS5420_EMULATION;
 416         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 417 }
 418
 419
 420 static int exynos_pm_suspend(void)
 421 {
 422         exynos_pm_central_suspend();
 423
 424         /* Setting SEQ_OPTION register */
 425         pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
 426                        S5P_CENTRAL_SEQ_OPTION);
 427
 428         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 429                 exynos_cpu_save_register();
 430
 431         return 0;
 432 }
 433
 434 static int exynos5420_pm_suspend(void)
 435 {
 436         u32 this_cluster;
 437
 438         exynos_pm_central_suspend();
 439
 440         /* Setting SEQ_OPTION register */
 441
 442         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 443         if (!this_cluster)
 444                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
 445                                 S5P_CENTRAL_SEQ_OPTION);
 446         else
 447                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
 448                                 S5P_CENTRAL_SEQ_OPTION);
 449         return 0;
 450 }
 451
 452 static void exynos_pm_release_retention(void)
 453 {
 454         unsigned int i;
 455
 456         for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
 457                 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
 458                                 pm_data->release_ret_regs[i]);
 459 }
 460
 461 static void exynos_pm_resume(void)
 462 {
 463         u32 cpuid = read_cpuid_part();
 464
 465         if (exynos_pm_central_resume())
 466                 goto early_wakeup;
 467
 468         /* For release retention */
 469         exynos_pm_release_retention();
 470
 471         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 472
 473         if (cpuid == ARM_CPU_PART_CORTEX_A9)
 474                 scu_enable(S5P_VA_SCU);
 475
 476         if (call_firmware_op(resume) == -ENOSYS
 477             && cpuid == ARM_CPU_PART_CORTEX_A9)
 478                 exynos_cpu_restore_register();
 479
 480 early_wakeup:
 481
 482         /* Clear SLEEP mode set in INFORM1 */
 483         pmu_raw_writel(0x0, S5P_INFORM1);
 484         exynos_set_delayed_reset_assertion(true);
 485 }
 486
 487 static void exynos3250_pm_resume(void)
 488 {
 489         u32 cpuid = read_cpuid_part();
 490
 491         if (exynos_pm_central_resume())
 492                 goto early_wakeup;
 493
 494         /* For release retention */
 495         exynos_pm_release_retention();
 496
 497         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 498
 499         if (call_firmware_op(resume) == -ENOSYS
 500             && cpuid == ARM_CPU_PART_CORTEX_A9)
 501                 exynos_cpu_restore_register();
 502
 503 early_wakeup:
 504
 505         /* Clear SLEEP mode set in INFORM1 */
 506         pmu_raw_writel(0x0, S5P_INFORM1);
 507 }
 508
 509 static void exynos5420_prepare_pm_resume(void)
 510 {
 511         unsigned int mpidr, cluster;
 512
 513         mpidr = read_cpuid_mpidr();
 514         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 515
 516         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 517                 WARN_ON(mcpm_cpu_powered_up());
 518
 519         if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
 520                 /*
 521                  * When system is resumed on the LITTLE/KFC core (cluster 1),
 522                  * the DSCR is not properly updated until the power is turned
 523                  * on also for the cluster 0. Enable it for a while to
 524                  * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
 525                  * block and avoid undefined instruction issue on CP14 reset.
 526                  */
 527                 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 528                                 EXYNOS_COMMON_CONFIGURATION(0));
 529                 pmu_raw_writel(0,
 530                                 EXYNOS_COMMON_CONFIGURATION(0));
 531         }
 532 }
 533
 534 static void exynos5420_pm_resume(void)
 535 {
 536         unsigned long tmp;
 537
 538         /* Restore the CPU0 low power state register */
 539         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 540         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
 541                 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 542
 543         /* Restore the sysram cpu state register */
 544         __raw_writel(exynos5420_cpu_state,
 545                 sysram_base_addr + EXYNOS5420_CPU_STATE);
 546
 547         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 548                         S5P_CENTRAL_SEQ_OPTION);
 549
 550         if (exynos_pm_central_resume())
 551                 goto early_wakeup;
 552
 553         /* For release retention */
 554         exynos_pm_release_retention();
 555
 556         pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
 557
 558         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 559
 560 early_wakeup:
 561
 562         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 563         tmp &= ~EXYNOS5420_UFS;
 564         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 565
 566         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 567         tmp &= ~EXYNOS5420_EMULATION;
 568         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 569
 570         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 571         tmp &= ~EXYNOS5420_EMULATION;
 572         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 573
 574         /* Clear SLEEP mode set in INFORM1 */
 575         pmu_raw_writel(0x0, S5P_INFORM1);
 576 }
 577
 578 /*
 579  * Suspend Ops
 580  */
 581
 582 static int exynos_suspend_enter(suspend_state_t state)
 583 {
 584         int ret;
 585
 586         s3c_pm_debug_init();
 587
 588         S3C_PMDBG("%s: suspending the system...\n", __func__);
 589
 590         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 591                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 592
 593         if (exynos_irqwake_intmask == -1U
 594             && exynos_get_eint_wake_mask() == -1U) {
 595                 pr_err("%s: No wake-up sources!\n", __func__);
 596                 pr_err("%s: Aborting sleep\n", __func__);
 597                 return -EINVAL;
 598         }
 599
 600         s3c_pm_save_uarts();
 601         if (pm_data->pm_prepare)
 602                 pm_data->pm_prepare();
 603         flush_cache_all();
 604         s3c_pm_check_store();
 605
 606         ret = call_firmware_op(suspend);
 607         if (ret == -ENOSYS)
 608                 ret = cpu_suspend(0, pm_data->cpu_suspend);
 609         if (ret)
 610                 return ret;
 611
 612         if (pm_data->pm_resume_prepare)
 613                 pm_data->pm_resume_prepare();
 614         s3c_pm_restore_uarts();
 615
 616         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 617                         pmu_raw_readl(S5P_WAKEUP_STAT));
 618
 619         s3c_pm_check_restore();
 620
 621         S3C_PMDBG("%s: resuming the system...\n", __func__);
 622
 623         return 0;
 624 }
 625
 626 static int exynos_suspend_prepare(void)
 627 {
 628         int ret;
 629
 630         /*
 631          * REVISIT: It would be better if struct platform_suspend_ops
 632          * .prepare handler get the suspend_state_t as a parameter to
 633          * avoid hard-coding the suspend to mem state. It's safe to do
 634          * it now only because the suspend_valid_only_mem function is
 635          * used as the .valid callback used to check if a given state
 636          * is supported by the platform anyways.
 637          */
 638         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
 639         if (ret) {
 640                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
 641                 return ret;
 642         }
 643
 644         s3c_pm_check_prepare();
 645
 646         return 0;
 647 }
 648
 649 static void exynos_suspend_finish(void)
 650 {
 651         int ret;
 652
 653         s3c_pm_check_cleanup();
 654
 655         ret = regulator_suspend_finish();
 656         if (ret)
 657                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
 658 }
 659
 660 static const struct platform_suspend_ops exynos_suspend_ops = {
 661         .enter          = exynos_suspend_enter,
 662         .prepare        = exynos_suspend_prepare,
 663         .finish         = exynos_suspend_finish,
 664         .valid          = suspend_valid_only_mem,
 665 };
 666
 667 static const struct exynos_pm_data exynos3250_pm_data = {
 668         .wkup_irq       = exynos3250_wkup_irq,
 669         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 670         .release_ret_regs = exynos3250_release_ret_regs,
 671         .pm_suspend     = exynos_pm_suspend,
 672         .pm_resume      = exynos3250_pm_resume,
 673         .pm_prepare     = exynos3250_pm_prepare,
 674         .cpu_suspend    = exynos3250_cpu_suspend,
 675 };
 676
 677 static const struct exynos_pm_data exynos4_pm_data = {
 678         .wkup_irq       = exynos4_wkup_irq,
 679         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 680         .release_ret_regs = exynos_release_ret_regs,
 681         .pm_suspend     = exynos_pm_suspend,
 682         .pm_resume      = exynos_pm_resume,
 683         .pm_prepare     = exynos_pm_prepare,
 684         .cpu_suspend    = exynos_cpu_suspend,
 685 };
 686
 687 static const struct exynos_pm_data exynos5250_pm_data = {
 688         .wkup_irq       = exynos5250_wkup_irq,
 689         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 690         .release_ret_regs = exynos_release_ret_regs,
 691         .pm_suspend     = exynos_pm_suspend,
 692         .pm_resume      = exynos_pm_resume,
 693         .pm_prepare     = exynos_pm_prepare,
 694         .cpu_suspend    = exynos_cpu_suspend,
 695 };
 696
 697 static const struct exynos_pm_data exynos5420_pm_data = {
 698         .wkup_irq       = exynos5250_wkup_irq,
 699         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
 700         .release_ret_regs = exynos5420_release_ret_regs,
 701         .pm_resume_prepare = exynos5420_prepare_pm_resume,
 702         .pm_resume      = exynos5420_pm_resume,
 703         .pm_suspend     = exynos5420_pm_suspend,
 704         .pm_prepare     = exynos5420_pm_prepare,
 705         .cpu_suspend    = exynos5420_cpu_suspend,
 706 };
 707
 708 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
 709         {
 710                 .compatible = "samsung,exynos3250-pmu",
 711                 .data = &exynos3250_pm_data,
 712         }, {
 713                 .compatible = "samsung,exynos4210-pmu",
 714                 .data = &exynos4_pm_data,
 715         }, {
 716                 .compatible = "samsung,exynos4212-pmu",
 717                 .data = &exynos4_pm_data,
 718         }, {
 719                 .compatible = "samsung,exynos4412-pmu",
 720                 .data = &exynos4_pm_data,
 721         }, {
 722                 .compatible = "samsung,exynos5250-pmu",
 723                 .data = &exynos5250_pm_data,
 724         }, {
 725                 .compatible = "samsung,exynos5420-pmu",
 726                 .data = &exynos5420_pm_data,
 727         },
 728         { /*sentinel*/ },
 729 };
 730
 731 static struct syscore_ops exynos_pm_syscore_ops;
 732
 733 void __init exynos_pm_init(void)
 734 {
 735         const struct of_device_id *match;
 736         struct device_node *np;
 737         u32 tmp;
 738
 739         np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
 740         if (!np) {
 741                 pr_err("Failed to find PMU node\n");
 742                 return;
 743         }
 744
 745         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
 746                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
 747                 of_node_put(np);
 748                 return;
 749         }
 750         of_node_put(np);
 751
 752         pm_data = (const struct exynos_pm_data *) match->data;
 753
 754         /* All wakeup disable */
 755         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 756         tmp |= pm_data->wake_disable_mask;
 757         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 758
 759         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
 760         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
 761
 762         register_syscore_ops(&exynos_pm_syscore_ops);
 763         suspend_set_ops(&exynos_suspend_ops);
 764 }