arch/arm/mach-dove/common.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * arch/arm/mach-dove/common.c
   4  *
   5  * Core functions for Marvell Dove 88AP510 System On Chip
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/of.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dma-mv_xor.h>
  15 #include <linux/platform_data/usb-ehci-orion.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/soc/dove/pmu.h>
  18 #include <asm/hardware/cache-tauros2.h>
  19 #include <asm/mach/arch.h>
  20 #include <asm/mach/map.h>
  21 #include <asm/mach/time.h>
  22 #include <plat/common.h>
  23 #include <plat/irq.h>
  24 #include <plat/time.h>
  25 #include "bridge-regs.h"
  26 #include "pm.h"
  27 #include "common.h"
  28
  29 /* These can go away once Dove uses the mvebu-mbus DT binding */
  30 #define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
  31 #define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
  32 #define DOVE_MBUS_PCIE0_IO_TARGET     0x4
  33 #define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
  34 #define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
  35 #define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
  36 #define DOVE_MBUS_PCIE1_IO_TARGET     0x8
  37 #define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
  38 #define DOVE_MBUS_CESA_TARGET         0x3
  39 #define DOVE_MBUS_CESA_ATTR           0x1
  40 #define DOVE_MBUS_BOOTROM_TARGET      0x1
  41 #define DOVE_MBUS_BOOTROM_ATTR        0xfd
  42 #define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
  43 #define DOVE_MBUS_SCRATCHPAD_ATTR     0x0
  44
  45 /*****************************************************************************
  46  * I/O Address Mapping
  47  ****************************************************************************/
  48 static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
  49         {
  50                 .virtual        = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
  51                 .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
  52                 .length         = DOVE_SB_REGS_SIZE,
  53                 .type           = MT_DEVICE,
  54         }, {
  55                 .virtual        = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
  56                 .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
  57                 .length         = DOVE_NB_REGS_SIZE,
  58                 .type           = MT_DEVICE,
  59         },
  60 };
  61
  62 void __init dove_map_io(void)
  63 {
  64         iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
  65 }
  66
  67 /*****************************************************************************
  68  * CLK tree
  69  ****************************************************************************/
  70 static int dove_tclk;
  71
  72 static DEFINE_SPINLOCK(gating_lock);
  73 static struct clk *tclk;
  74
  75 static struct clk __init *dove_register_gate(const char *name,
  76                                              const char *parent, u8 bit_idx)
  77 {
  78         return clk_register_gate(NULL, name, parent, 0,
  79                                  (void __iomem *)CLOCK_GATING_CONTROL,
  80                                  bit_idx, 0, &gating_lock);
  81 }
  82
  83 static void __init dove_clk_init(void)
  84 {
  85         struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
  86         struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
  87         struct clk *xor0, *xor1, *ge, *gephy;
  88
  89         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);
  90
  91         usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
  92         usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
  93         sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
  94         pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
  95         pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
  96         sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
  97         sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
  98         nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
  99         camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
 100         i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
 101         i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
 102         crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
 103         ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
 104         pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
 105         xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
 106         xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
 107         gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
 108         ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
 109
 110         orion_clkdev_add(NULL, "orion_spi.0", tclk);
 111         orion_clkdev_add(NULL, "orion_spi.1", tclk);
 112         orion_clkdev_add(NULL, "orion_wdt", tclk);
 113         orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
 114
 115         orion_clkdev_add(NULL, "orion-ehci.0", usb0);
 116         orion_clkdev_add(NULL, "orion-ehci.1", usb1);
 117         orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
 118         orion_clkdev_add(NULL, "sata_mv.0", sata);
 119         orion_clkdev_add("0", "pcie", pex0);
 120         orion_clkdev_add("1", "pcie", pex1);
 121         orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
 122         orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
 123         orion_clkdev_add(NULL, "orion_nand", nand);
 124         orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
 125         orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
 126         orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
 127         orion_clkdev_add(NULL, "mv_crypto", crypto);
 128         orion_clkdev_add(NULL, "dove-ac97", ac97);
 129         orion_clkdev_add(NULL, "dove-pdma", pdma);
 130         orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
 131         orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
 132 }
 133
 134 /*****************************************************************************
 135  * EHCI0
 136  ****************************************************************************/
 137 void __init dove_ehci0_init(void)
 138 {
 139         orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
 140 }
 141
 142 /*****************************************************************************
 143  * EHCI1
 144  ****************************************************************************/
 145 void __init dove_ehci1_init(void)
 146 {
 147         orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
 148 }
 149
 150 /*****************************************************************************
 151  * GE00
 152  ****************************************************************************/
 153 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 154 {
 155         orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
 156                         IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
 157                         1600);
 158 }
 159
 160 /*****************************************************************************
 161  * SoC RTC
 162  ****************************************************************************/
 163 static void __init dove_rtc_init(void)
 164 {
 165         orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
 166 }
 167
 168 /*****************************************************************************
 169  * SATA
 170  ****************************************************************************/
 171 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
 172 {
 173         orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
 174
 175 }
 176
 177 /*****************************************************************************
 178  * UART0
 179  ****************************************************************************/
 180 void __init dove_uart0_init(void)
 181 {
 182         orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
 183                          IRQ_DOVE_UART_0, tclk);
 184 }
 185
 186 /*****************************************************************************
 187  * UART1
 188  ****************************************************************************/
 189 void __init dove_uart1_init(void)
 190 {
 191         orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
 192                          IRQ_DOVE_UART_1, tclk);
 193 }
 194
 195 /*****************************************************************************
 196  * UART2
 197  ****************************************************************************/
 198 void __init dove_uart2_init(void)
 199 {
 200         orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
 201                          IRQ_DOVE_UART_2, tclk);
 202 }
 203
 204 /*****************************************************************************
 205  * UART3
 206  ****************************************************************************/
 207 void __init dove_uart3_init(void)
 208 {
 209         orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
 210                          IRQ_DOVE_UART_3, tclk);
 211 }
 212
 213 /*****************************************************************************
 214  * SPI
 215  ****************************************************************************/
 216 void __init dove_spi0_init(void)
 217 {
 218         orion_spi_init(DOVE_SPI0_PHYS_BASE);
 219 }
 220
 221 void __init dove_spi1_init(void)
 222 {
 223         orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
 224 }
 225
 226 /*****************************************************************************
 227  * I2C
 228  ****************************************************************************/
 229 void __init dove_i2c_init(void)
 230 {
 231         orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
 232 }
 233
 234 /*****************************************************************************
 235  * Time handling
 236  ****************************************************************************/
 237 void __init dove_init_early(void)
 238 {
 239         orion_time_set_base(TIMER_VIRT_BASE);
 240         mvebu_mbus_init("marvell,dove-mbus",
 241                         BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
 242                         DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
 243 }
 244
 245 static int __init dove_find_tclk(void)
 246 {
 247         return 166666667;
 248 }
 249
 250 void __init dove_timer_init(void)
 251 {
 252         dove_tclk = dove_find_tclk();
 253         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 254                         IRQ_DOVE_BRIDGE, dove_tclk);
 255 }
 256
 257 /*****************************************************************************
 258  * XOR 0
 259  ****************************************************************************/
 260 static void __init dove_xor0_init(void)
 261 {
 262         orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
 263                         IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
 264 }
 265
 266 /*****************************************************************************
 267  * XOR 1
 268  ****************************************************************************/
 269 static void __init dove_xor1_init(void)
 270 {
 271         orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
 272                         IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
 273 }
 274
 275 /*****************************************************************************
 276  * SDIO
 277  ****************************************************************************/
 278 static u64 sdio_dmamask = DMA_BIT_MASK(32);
 279
 280 static struct resource dove_sdio0_resources[] = {
 281         {
 282                 .start  = DOVE_SDIO0_PHYS_BASE,
 283                 .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
 284                 .flags  = IORESOURCE_MEM,
 285         }, {
 286                 .start  = IRQ_DOVE_SDIO0,
 287                 .end    = IRQ_DOVE_SDIO0,
 288                 .flags  = IORESOURCE_IRQ,
 289         },
 290 };
 291
 292 static struct platform_device dove_sdio0 = {
 293         .name           = "sdhci-dove",
 294         .id             = 0,
 295         .dev            = {
 296                 .dma_mask               = &sdio_dmamask,
 297                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 298         },
 299         .resource       = dove_sdio0_resources,
 300         .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
 301 };
 302
 303 void __init dove_sdio0_init(void)
 304 {
 305         platform_device_register(&dove_sdio0);
 306 }
 307
 308 static struct resource dove_sdio1_resources[] = {
 309         {
 310                 .start  = DOVE_SDIO1_PHYS_BASE,
 311                 .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
 312                 .flags  = IORESOURCE_MEM,
 313         }, {
 314                 .start  = IRQ_DOVE_SDIO1,
 315                 .end    = IRQ_DOVE_SDIO1,
 316                 .flags  = IORESOURCE_IRQ,
 317         },
 318 };
 319
 320 static struct platform_device dove_sdio1 = {
 321         .name           = "sdhci-dove",
 322         .id             = 1,
 323         .dev            = {
 324                 .dma_mask               = &sdio_dmamask,
 325                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 326         },
 327         .resource       = dove_sdio1_resources,
 328         .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
 329 };
 330
 331 void __init dove_sdio1_init(void)
 332 {
 333         platform_device_register(&dove_sdio1);
 334 }
 335
 336 void __init dove_setup_cpu_wins(void)
 337 {
 338         /*
 339          * The PCIe windows will no longer be statically allocated
 340          * here once Dove is migrated to the pci-mvebu driver. The
 341          * non-PCIe windows will no longer be created here once Dove
 342          * fully moves to DT.
 343          */
 344         mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
 345                                           DOVE_MBUS_PCIE0_IO_ATTR,
 346                                           DOVE_PCIE0_IO_PHYS_BASE,
 347                                           DOVE_PCIE0_IO_SIZE,
 348                                           DOVE_PCIE0_IO_BUS_BASE);
 349         mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
 350                                           DOVE_MBUS_PCIE1_IO_ATTR,
 351                                           DOVE_PCIE1_IO_PHYS_BASE,
 352                                           DOVE_PCIE1_IO_SIZE,
 353                                           DOVE_PCIE1_IO_BUS_BASE);
 354         mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
 355                                     DOVE_MBUS_PCIE0_MEM_ATTR,
 356                                     DOVE_PCIE0_MEM_PHYS_BASE,
 357                                     DOVE_PCIE0_MEM_SIZE);
 358         mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
 359                                     DOVE_MBUS_PCIE1_MEM_ATTR,
 360                                     DOVE_PCIE1_MEM_PHYS_BASE,
 361                                     DOVE_PCIE1_MEM_SIZE);
 362         mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
 363                                     DOVE_MBUS_CESA_ATTR,
 364                                     DOVE_CESA_PHYS_BASE,
 365                                     DOVE_CESA_SIZE);
 366         mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
 367                                     DOVE_MBUS_BOOTROM_ATTR,
 368                                     DOVE_BOOTROM_PHYS_BASE,
 369                                     DOVE_BOOTROM_SIZE);
 370         mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
 371                                     DOVE_MBUS_SCRATCHPAD_ATTR,
 372                                     DOVE_SCRATCHPAD_PHYS_BASE,
 373                                     DOVE_SCRATCHPAD_SIZE);
 374 }
 375
 376 static struct resource orion_wdt_resource[] = {
 377                 DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
 378                 DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
 379 };
 380
 381 static struct platform_device orion_wdt_device = {
 382         .name           = "orion_wdt",
 383         .id             = -1,
 384         .num_resources  = ARRAY_SIZE(orion_wdt_resource),
 385         .resource       = orion_wdt_resource,
 386 };
 387
 388 static void __init __maybe_unused orion_wdt_init(void)
 389 {
 390         platform_device_register(&orion_wdt_device);
 391 }
 392
 393 static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
 394         {
 395                 .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
 396                 .rst_mask = PMU_SW_RST_VIDEO_MASK,
 397                 .iso_mask = PMU_ISO_VIDEO_MASK,
 398                 .name = "vpu-domain",
 399         }, {
 400                 .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
 401                 .rst_mask = PMU_SW_RST_GPU_MASK,
 402                 .iso_mask = PMU_ISO_GPU_MASK,
 403                 .name = "gpu-domain",
 404         }, {
 405                 /* sentinel */
 406         },
 407 };
 408
 409 static const struct dove_pmu_initdata pmu_data __initconst = {
 410         .pmc_base = DOVE_PMU_VIRT_BASE,
 411         .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
 412         .irq = IRQ_DOVE_PMU,
 413         .irq_domain_start = IRQ_DOVE_PMU_START,
 414         .domains = pmu_domains,
 415 };
 416
 417 void __init dove_init(void)
 418 {
 419         pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
 420                 (dove_tclk + 499999) / 1000000);
 421
 422 #ifdef CONFIG_CACHE_TAUROS2
 423         tauros2_init(0);
 424 #endif
 425         dove_setup_cpu_wins();
 426
 427         /* Setup root of clk tree */
 428         dove_clk_init();
 429
 430         /* internal devices that every board has */
 431         dove_init_pmu_legacy(&pmu_data);
 432         dove_rtc_init();
 433         dove_xor0_init();
 434         dove_xor1_init();
 435 }
 436
 437 void dove_restart(enum reboot_mode mode, const char *cmd)
 438 {
 439         /*
 440          * Enable soft reset to assert RSTOUTn.
 441          */
 442         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 443
 444         /*
 445          * Assert soft reset.
 446          */
 447         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 448
 449         while (1)
 450                 ;
 451 }