2 * Pin-multiplex helper macros for TI DaVinci family devices
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 * Copyright (C) 2008 Texas Instruments.
13 #ifndef _MACH_DAVINCI_MUX_H_
14 #define _MACH_DAVINCI_MUX_H_
18 const char *mux_reg_name;
19 const unsigned char mux_reg;
20 const unsigned char mask_offset;
21 const unsigned char mask;
22 const unsigned char mode;
26 enum davinci_dm644x_index {
27 /* ATA and HDDIR functions */
72 /* EMAC and MDIO function */
75 /* GPIO3V[0:16] pins */
92 enum davinci_dm646x_index {
104 DM646X_STSOMUX_DISABLE,
105 DM646X_STSIMUX_DISABLE,
106 DM646X_PTSOMUX_DISABLE,
107 DM646X_PTSIMUX_DISABLE,
112 DM646X_PTSOMUX_PARALLEL,
113 DM646X_PTSIMUX_PARALLEL,
114 DM646X_PTSOMUX_SERIAL,
115 DM646X_PTSIMUX_SERIAL,
118 enum davinci_dm355_index {
149 DM355_INT_EDMA_TC0_ERR,
150 DM355_INT_EDMA_TC1_ERR,
152 /* EDMA event muxing */
159 DM355_VOUT_FIELD_G70,
164 /* Video In Pin Mux */
174 enum davinci_dm365_index {
303 DM365_VOUT_FIELD_G81,
315 DM365_INT_EDMA_TC0_ERR,
316 DM365_INT_EDMA_TC1_ERR,
317 DM365_INT_EDMA_TC2_ERR,
318 DM365_INT_EDMA_TC3_ERR,
320 DM365_INT_EMAC_RXTHRESH,
321 DM365_INT_EMAC_RXPULSE,
322 DM365_INT_EMAC_TXPULSE,
323 DM365_INT_EMAC_MISCPULSE,
324 DM365_INT_IMX0_ENABLE,
325 DM365_INT_IMX0_DISABLE,
326 DM365_INT_HDVICP_ENABLE,
327 DM365_INT_HDVICP_DISABLE,
328 DM365_INT_IMX1_ENABLE,
329 DM365_INT_IMX1_DISABLE,
330 DM365_INT_NSF_ENABLE,
331 DM365_INT_NSF_DISABLE,
333 /* EDMA event muxing */
489 DA830_RMII_MHZ_50_CLK,
696 DA830_NLCD_AC_ENB_CS,
745 enum davinci_da850_index {
797 DA850_RMII_MHZ_50_CLK,
844 DA850_NLCD_AC_ENB_CS,
846 /* MMC/SD0 function */
854 /* MMC/SD1 function */
862 /* EMIF2.5/EMIFA function */
969 #define PINMUX(x) (4 * (x))
971 #ifdef CONFIG_DAVINCI_MUX
972 /* setup pin muxing */
973 extern int davinci_cfg_reg(unsigned long reg_cfg);
974 extern int davinci_cfg_reg_list(const short pins[]);
976 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
977 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
978 static inline int davinci_cfg_reg_list(const short pins[])
985 #define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
989 .mux_reg_name = "PINMUX"#muxreg, \
990 .mux_reg = PINMUX(muxreg), \
991 .mask_offset = mode_offset, \
996 #define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
1000 .mux_reg_name = "INTMUX", \
1001 .mux_reg = INTMUX, \
1002 .mask_offset = mode_offset, \
1003 .mask = mode_mask, \
1007 #define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
1008 [soc##_##desc] = { \
1011 .mux_reg_name = "EVTMUX", \
1012 .mux_reg = EVTMUX, \
1013 .mask_offset = mode_offset, \
1014 .mask = mode_mask, \
1018 #endif /* _MACH_DAVINCI_MUX_H */