arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/clk/davinci.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_data/edma.h>
  19 #include <linux/platform_data/gpio-davinci.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22
  23 #include <asm/mach/map.h>
  24
  25 #include <mach/common.h>
  26 #include <mach/cputype.h>
  27 #include <mach/irqs.h>
  28 #include <mach/mux.h>
  29 #include <mach/serial.h>
  30 #include <mach/time.h>
  31
  32 #include "asp.h"
  33 #include "davinci.h"
  34 #include "mux.h"
  35
  36 #define DAVINCI_VPIF_BASE       (0x01C12000)
  37
  38 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  39                                         BIT_MASK(0))
  40 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  41                                         BIT_MASK(8))
  42
  43 #define DM646X_EMAC_BASE                0x01c80000
  44 #define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
  45 #define DM646X_EMAC_CNTRL_OFFSET        0x0000
  46 #define DM646X_EMAC_CNTRL_MOD_OFFSET    0x1000
  47 #define DM646X_EMAC_CNTRL_RAM_OFFSET    0x2000
  48 #define DM646X_EMAC_CNTRL_RAM_SIZE      0x2000
  49
  50 static struct emac_platform_data dm646x_emac_pdata = {
  51         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
  52         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
  53         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
  54         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
  55         .version                = EMAC_VERSION_2,
  56 };
  57
  58 static struct resource dm646x_emac_resources[] = {
  59         {
  60                 .start  = DM646X_EMAC_BASE,
  61                 .end    = DM646X_EMAC_BASE + SZ_16K - 1,
  62                 .flags  = IORESOURCE_MEM,
  63         },
  64         {
  65                 .start  = IRQ_DM646X_EMACRXTHINT,
  66                 .end    = IRQ_DM646X_EMACRXTHINT,
  67                 .flags  = IORESOURCE_IRQ,
  68         },
  69         {
  70                 .start  = IRQ_DM646X_EMACRXINT,
  71                 .end    = IRQ_DM646X_EMACRXINT,
  72                 .flags  = IORESOURCE_IRQ,
  73         },
  74         {
  75                 .start  = IRQ_DM646X_EMACTXINT,
  76                 .end    = IRQ_DM646X_EMACTXINT,
  77                 .flags  = IORESOURCE_IRQ,
  78         },
  79         {
  80                 .start  = IRQ_DM646X_EMACMISCINT,
  81                 .end    = IRQ_DM646X_EMACMISCINT,
  82                 .flags  = IORESOURCE_IRQ,
  83         },
  84 };
  85
  86 static struct platform_device dm646x_emac_device = {
  87         .name           = "davinci_emac",
  88         .id             = 1,
  89         .dev = {
  90                 .platform_data  = &dm646x_emac_pdata,
  91         },
  92         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
  93         .resource       = dm646x_emac_resources,
  94 };
  95
  96 static struct resource dm646x_mdio_resources[] = {
  97         {
  98                 .start  = DM646X_EMAC_MDIO_BASE,
  99                 .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
 100                 .flags  = IORESOURCE_MEM,
 101         },
 102 };
 103
 104 static struct platform_device dm646x_mdio_device = {
 105         .name           = "davinci_mdio",
 106         .id             = 0,
 107         .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
 108         .resource       = dm646x_mdio_resources,
 109 };
 110
 111 /*
 112  * Device specific mux setup
 113  *
 114  *      soc     description     mux  mode   mode  mux    dbg
 115  *                              reg  offset mask  mode
 116  */
 117 static const struct mux_config dm646x_pins[] = {
 118 #ifdef CONFIG_DAVINCI_MUX
 119 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 120
 121 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 122
 123 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 124
 125 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 126
 127 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 128
 129 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 130
 131 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 132
 133 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 134
 135 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 136
 137 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 138
 139 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 140
 141 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 142
 143 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 144
 145 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 146 #endif
 147 };
 148
 149 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 150         [IRQ_DM646X_VP_VERTINT0]        = 7,
 151         [IRQ_DM646X_VP_VERTINT1]        = 7,
 152         [IRQ_DM646X_VP_VERTINT2]        = 7,
 153         [IRQ_DM646X_VP_VERTINT3]        = 7,
 154         [IRQ_DM646X_VP_ERRINT]          = 7,
 155         [IRQ_DM646X_RESERVED_1]         = 7,
 156         [IRQ_DM646X_RESERVED_2]         = 7,
 157         [IRQ_DM646X_WDINT]              = 7,
 158         [IRQ_DM646X_CRGENINT0]          = 7,
 159         [IRQ_DM646X_CRGENINT1]          = 7,
 160         [IRQ_DM646X_TSIFINT0]           = 7,
 161         [IRQ_DM646X_TSIFINT1]           = 7,
 162         [IRQ_DM646X_VDCEINT]            = 7,
 163         [IRQ_DM646X_USBINT]             = 7,
 164         [IRQ_DM646X_USBDMAINT]          = 7,
 165         [IRQ_DM646X_PCIINT]             = 7,
 166         [IRQ_CCINT0]                    = 7,    /* dma */
 167         [IRQ_CCERRINT]                  = 7,    /* dma */
 168         [IRQ_TCERRINT0]                 = 7,    /* dma */
 169         [IRQ_TCERRINT]                  = 7,    /* dma */
 170         [IRQ_DM646X_TCERRINT2]          = 7,
 171         [IRQ_DM646X_TCERRINT3]          = 7,
 172         [IRQ_DM646X_IDE]                = 7,
 173         [IRQ_DM646X_HPIINT]             = 7,
 174         [IRQ_DM646X_EMACRXTHINT]        = 7,
 175         [IRQ_DM646X_EMACRXINT]          = 7,
 176         [IRQ_DM646X_EMACTXINT]          = 7,
 177         [IRQ_DM646X_EMACMISCINT]        = 7,
 178         [IRQ_DM646X_MCASP0TXINT]        = 7,
 179         [IRQ_DM646X_MCASP0RXINT]        = 7,
 180         [IRQ_DM646X_RESERVED_3]         = 7,
 181         [IRQ_DM646X_MCASP1TXINT]        = 7,
 182         [IRQ_TINT0_TINT12]              = 7,    /* clockevent */
 183         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 184         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 185         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 186         [IRQ_PWMINT0]                   = 7,
 187         [IRQ_PWMINT1]                   = 7,
 188         [IRQ_DM646X_VLQINT]             = 7,
 189         [IRQ_I2C]                       = 7,
 190         [IRQ_UARTINT0]                  = 7,
 191         [IRQ_UARTINT1]                  = 7,
 192         [IRQ_DM646X_UARTINT2]           = 7,
 193         [IRQ_DM646X_SPINT0]             = 7,
 194         [IRQ_DM646X_SPINT1]             = 7,
 195         [IRQ_DM646X_DSP2ARMINT]         = 7,
 196         [IRQ_DM646X_RESERVED_4]         = 7,
 197         [IRQ_DM646X_PSCINT]             = 7,
 198         [IRQ_DM646X_GPIO0]              = 7,
 199         [IRQ_DM646X_GPIO1]              = 7,
 200         [IRQ_DM646X_GPIO2]              = 7,
 201         [IRQ_DM646X_GPIO3]              = 7,
 202         [IRQ_DM646X_GPIO4]              = 7,
 203         [IRQ_DM646X_GPIO5]              = 7,
 204         [IRQ_DM646X_GPIO6]              = 7,
 205         [IRQ_DM646X_GPIO7]              = 7,
 206         [IRQ_DM646X_GPIOBNK0]           = 7,
 207         [IRQ_DM646X_GPIOBNK1]           = 7,
 208         [IRQ_DM646X_GPIOBNK2]           = 7,
 209         [IRQ_DM646X_DDRINT]             = 7,
 210         [IRQ_DM646X_AEMIFINT]           = 7,
 211         [IRQ_COMMTX]                    = 7,
 212         [IRQ_COMMRX]                    = 7,
 213         [IRQ_EMUINT]                    = 7,
 214 };
 215
 216 /*----------------------------------------------------------------------*/
 217
 218 /* Four Transfer Controllers on DM646x */
 219 static s8 dm646x_queue_priority_mapping[][2] = {
 220         /* {event queue no, Priority} */
 221         {0, 4},
 222         {1, 0},
 223         {2, 5},
 224         {3, 1},
 225         {-1, -1},
 226 };
 227
 228 static const struct dma_slave_map dm646x_edma_map[] = {
 229         { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
 230         { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
 231         { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
 232         { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
 233         { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
 234 };
 235
 236 static struct edma_soc_info dm646x_edma_pdata = {
 237         .queue_priority_mapping = dm646x_queue_priority_mapping,
 238         .default_queue          = EVENTQ_1,
 239         .slave_map              = dm646x_edma_map,
 240         .slavecnt               = ARRAY_SIZE(dm646x_edma_map),
 241 };
 242
 243 static struct resource edma_resources[] = {
 244         {
 245                 .name   = "edma3_cc",
 246                 .start  = 0x01c00000,
 247                 .end    = 0x01c00000 + SZ_64K - 1,
 248                 .flags  = IORESOURCE_MEM,
 249         },
 250         {
 251                 .name   = "edma3_tc0",
 252                 .start  = 0x01c10000,
 253                 .end    = 0x01c10000 + SZ_1K - 1,
 254                 .flags  = IORESOURCE_MEM,
 255         },
 256         {
 257                 .name   = "edma3_tc1",
 258                 .start  = 0x01c10400,
 259                 .end    = 0x01c10400 + SZ_1K - 1,
 260                 .flags  = IORESOURCE_MEM,
 261         },
 262         {
 263                 .name   = "edma3_tc2",
 264                 .start  = 0x01c10800,
 265                 .end    = 0x01c10800 + SZ_1K - 1,
 266                 .flags  = IORESOURCE_MEM,
 267         },
 268         {
 269                 .name   = "edma3_tc3",
 270                 .start  = 0x01c10c00,
 271                 .end    = 0x01c10c00 + SZ_1K - 1,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274         {
 275                 .name   = "edma3_ccint",
 276                 .start  = IRQ_CCINT0,
 277                 .flags  = IORESOURCE_IRQ,
 278         },
 279         {
 280                 .name   = "edma3_ccerrint",
 281                 .start  = IRQ_CCERRINT,
 282                 .flags  = IORESOURCE_IRQ,
 283         },
 284         /* not using TC*_ERR */
 285 };
 286
 287 static const struct platform_device_info dm646x_edma_device __initconst = {
 288         .name           = "edma",
 289         .id             = 0,
 290         .dma_mask       = DMA_BIT_MASK(32),
 291         .res            = edma_resources,
 292         .num_res        = ARRAY_SIZE(edma_resources),
 293         .data           = &dm646x_edma_pdata,
 294         .size_data      = sizeof(dm646x_edma_pdata),
 295 };
 296
 297 static struct resource dm646x_mcasp0_resources[] = {
 298         {
 299                 .name   = "mpu",
 300                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 301                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 302                 .flags  = IORESOURCE_MEM,
 303         },
 304         {
 305                 .name   = "tx",
 306                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 307                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 308                 .flags  = IORESOURCE_DMA,
 309         },
 310         {
 311                 .name   = "rx",
 312                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 313                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 314                 .flags  = IORESOURCE_DMA,
 315         },
 316         {
 317                 .name   = "tx",
 318                 .start  = IRQ_DM646X_MCASP0TXINT,
 319                 .flags  = IORESOURCE_IRQ,
 320         },
 321         {
 322                 .name   = "rx",
 323                 .start  = IRQ_DM646X_MCASP0RXINT,
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 /* DIT mode only, rx is not supported */
 329 static struct resource dm646x_mcasp1_resources[] = {
 330         {
 331                 .name   = "mpu",
 332                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 333                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 334                 .flags  = IORESOURCE_MEM,
 335         },
 336         {
 337                 .name   = "tx",
 338                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 339                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 340                 .flags  = IORESOURCE_DMA,
 341         },
 342         {
 343                 .name   = "tx",
 344                 .start  = IRQ_DM646X_MCASP1TXINT,
 345                 .flags  = IORESOURCE_IRQ,
 346         },
 347 };
 348
 349 static struct platform_device dm646x_mcasp0_device = {
 350         .name           = "davinci-mcasp",
 351         .id             = 0,
 352         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 353         .resource       = dm646x_mcasp0_resources,
 354 };
 355
 356 static struct platform_device dm646x_mcasp1_device = {
 357         .name           = "davinci-mcasp",
 358         .id             = 1,
 359         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 360         .resource       = dm646x_mcasp1_resources,
 361 };
 362
 363 static struct platform_device dm646x_dit_device = {
 364         .name   = "spdif-dit",
 365         .id     = -1,
 366 };
 367
 368 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 369
 370 static struct resource vpif_resource[] = {
 371         {
 372                 .start  = DAVINCI_VPIF_BASE,
 373                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 374                 .flags  = IORESOURCE_MEM,
 375         }
 376 };
 377
 378 static struct platform_device vpif_dev = {
 379         .name           = "vpif",
 380         .id             = -1,
 381         .dev            = {
 382                         .dma_mask               = &vpif_dma_mask,
 383                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 384         },
 385         .resource       = vpif_resource,
 386         .num_resources  = ARRAY_SIZE(vpif_resource),
 387 };
 388
 389 static struct resource vpif_display_resource[] = {
 390         {
 391                 .start = IRQ_DM646X_VP_VERTINT2,
 392                 .end   = IRQ_DM646X_VP_VERTINT2,
 393                 .flags = IORESOURCE_IRQ,
 394         },
 395         {
 396                 .start = IRQ_DM646X_VP_VERTINT3,
 397                 .end   = IRQ_DM646X_VP_VERTINT3,
 398                 .flags = IORESOURCE_IRQ,
 399         },
 400 };
 401
 402 static struct platform_device vpif_display_dev = {
 403         .name           = "vpif_display",
 404         .id             = -1,
 405         .dev            = {
 406                         .dma_mask               = &vpif_dma_mask,
 407                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 408         },
 409         .resource       = vpif_display_resource,
 410         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 411 };
 412
 413 static struct resource vpif_capture_resource[] = {
 414         {
 415                 .start = IRQ_DM646X_VP_VERTINT0,
 416                 .end   = IRQ_DM646X_VP_VERTINT0,
 417                 .flags = IORESOURCE_IRQ,
 418         },
 419         {
 420                 .start = IRQ_DM646X_VP_VERTINT1,
 421                 .end   = IRQ_DM646X_VP_VERTINT1,
 422                 .flags = IORESOURCE_IRQ,
 423         },
 424 };
 425
 426 static struct platform_device vpif_capture_dev = {
 427         .name           = "vpif_capture",
 428         .id             = -1,
 429         .dev            = {
 430                         .dma_mask               = &vpif_dma_mask,
 431                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 432         },
 433         .resource       = vpif_capture_resource,
 434         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 435 };
 436
 437 static struct resource dm646x_gpio_resources[] = {
 438         {       /* registers */
 439                 .start  = DAVINCI_GPIO_BASE,
 440                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 441                 .flags  = IORESOURCE_MEM,
 442         },
 443         {       /* interrupt */
 444                 .start  = IRQ_DM646X_GPIOBNK0,
 445                 .end    = IRQ_DM646X_GPIOBNK0,
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448         {
 449                 .start  = IRQ_DM646X_GPIOBNK1,
 450                 .end    = IRQ_DM646X_GPIOBNK1,
 451                 .flags  = IORESOURCE_IRQ,
 452         },
 453         {
 454                 .start  = IRQ_DM646X_GPIOBNK2,
 455                 .end    = IRQ_DM646X_GPIOBNK2,
 456                 .flags  = IORESOURCE_IRQ,
 457         },
 458 };
 459
 460 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
 461         .ngpio          = 43,
 462 };
 463
 464 int __init dm646x_gpio_register(void)
 465 {
 466         return davinci_gpio_register(dm646x_gpio_resources,
 467                                      ARRAY_SIZE(dm646x_gpio_resources),
 468                                      &dm646x_gpio_platform_data);
 469 }
 470 /*----------------------------------------------------------------------*/
 471
 472 static struct map_desc dm646x_io_desc[] = {
 473         {
 474                 .virtual        = IO_VIRT,
 475                 .pfn            = __phys_to_pfn(IO_PHYS),
 476                 .length         = IO_SIZE,
 477                 .type           = MT_DEVICE
 478         },
 479 };
 480
 481 /* Contents of JTAG ID register used to identify exact cpu type */
 482 static struct davinci_id dm646x_ids[] = {
 483         {
 484                 .variant        = 0x0,
 485                 .part_no        = 0xb770,
 486                 .manufacturer   = 0x017,
 487                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 488                 .name           = "dm6467_rev1.x",
 489         },
 490         {
 491                 .variant        = 0x1,
 492                 .part_no        = 0xb770,
 493                 .manufacturer   = 0x017,
 494                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 495                 .name           = "dm6467_rev3.x",
 496         },
 497 };
 498
 499 /*
 500  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 501  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 502  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 503  * T1_TOP: Timer 1, top   :  <unused>
 504  */
 505 static struct davinci_timer_info dm646x_timer_info = {
 506         .timers         = davinci_timer_instance,
 507         .clockevent_id  = T0_BOT,
 508         .clocksource_id = T0_TOP,
 509 };
 510
 511 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
 512         {
 513                 .mapbase        = DAVINCI_UART0_BASE,
 514                 .irq            = IRQ_UARTINT0,
 515                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 516                                   UPF_IOREMAP,
 517                 .iotype         = UPIO_MEM32,
 518                 .regshift       = 2,
 519         },
 520         {
 521                 .flags  = 0,
 522         }
 523 };
 524 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
 525         {
 526                 .mapbase        = DAVINCI_UART1_BASE,
 527                 .irq            = IRQ_UARTINT1,
 528                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 529                                   UPF_IOREMAP,
 530                 .iotype         = UPIO_MEM32,
 531                 .regshift       = 2,
 532         },
 533         {
 534                 .flags  = 0,
 535         }
 536 };
 537 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
 538         {
 539                 .mapbase        = DAVINCI_UART2_BASE,
 540                 .irq            = IRQ_DM646X_UARTINT2,
 541                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 542                                   UPF_IOREMAP,
 543                 .iotype         = UPIO_MEM32,
 544                 .regshift       = 2,
 545         },
 546         {
 547                 .flags  = 0,
 548         }
 549 };
 550
 551 struct platform_device dm646x_serial_device[] = {
 552         {
 553                 .name                   = "serial8250",
 554                 .id                     = PLAT8250_DEV_PLATFORM,
 555                 .dev                    = {
 556                         .platform_data  = dm646x_serial0_platform_data,
 557                 }
 558         },
 559         {
 560                 .name                   = "serial8250",
 561                 .id                     = PLAT8250_DEV_PLATFORM1,
 562                 .dev                    = {
 563                         .platform_data  = dm646x_serial1_platform_data,
 564                 }
 565         },
 566         {
 567                 .name                   = "serial8250",
 568                 .id                     = PLAT8250_DEV_PLATFORM2,
 569                 .dev                    = {
 570                         .platform_data  = dm646x_serial2_platform_data,
 571                 }
 572         },
 573         {
 574         }
 575 };
 576
 577 static const struct davinci_soc_info davinci_soc_info_dm646x = {
 578         .io_desc                = dm646x_io_desc,
 579         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 580         .jtag_id_reg            = 0x01c40028,
 581         .ids                    = dm646x_ids,
 582         .ids_num                = ARRAY_SIZE(dm646x_ids),
 583         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 584         .pinmux_pins            = dm646x_pins,
 585         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 586         .intc_base              = DAVINCI_ARM_INTC_BASE,
 587         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 588         .intc_irq_prios         = dm646x_default_priorities,
 589         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 590         .timer_info             = &dm646x_timer_info,
 591         .emac_pdata             = &dm646x_emac_pdata,
 592         .sram_dma               = 0x10010000,
 593         .sram_len               = SZ_32K,
 594 };
 595
 596 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 597 {
 598         dm646x_mcasp0_device.dev.platform_data = pdata;
 599         platform_device_register(&dm646x_mcasp0_device);
 600 }
 601
 602 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 603 {
 604         dm646x_mcasp1_device.dev.platform_data = pdata;
 605         platform_device_register(&dm646x_mcasp1_device);
 606         platform_device_register(&dm646x_dit_device);
 607 }
 608
 609 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 610                        struct vpif_capture_config *capture_config)
 611 {
 612         unsigned int value;
 613
 614         value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 615         value &= ~VSCLKDIS_MASK;
 616         __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 617
 618         value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 619         value &= ~VDD3P3V_VID_MASK;
 620         __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 621
 622         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 623         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 624         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 625         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 626
 627         vpif_display_dev.dev.platform_data = display_config;
 628         vpif_capture_dev.dev.platform_data = capture_config;
 629         platform_device_register(&vpif_dev);
 630         platform_device_register(&vpif_display_dev);
 631         platform_device_register(&vpif_capture_dev);
 632 }
 633
 634 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 635 {
 636         struct platform_device *edma_pdev;
 637
 638         dm646x_edma_pdata.rsv = rsv;
 639
 640         edma_pdev = platform_device_register_full(&dm646x_edma_device);
 641         return PTR_ERR_OR_ZERO(edma_pdev);
 642 }
 643
 644 void __init dm646x_init(void)
 645 {
 646         davinci_common_init(&davinci_soc_info_dm646x);
 647         davinci_map_sysmod();
 648 }
 649
 650 void __init dm646x_init_time(unsigned long ref_clk_rate,
 651                              unsigned long aux_clkin_rate)
 652 {
 653         void __iomem *pll1, *psc;
 654         struct clk *clk;
 655
 656         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
 657         clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
 658
 659         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 660         dm646x_pll1_init(NULL, pll1, NULL);
 661
 662         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 663         dm646x_psc_init(NULL, psc);
 664
 665         clk = clk_get(NULL, "timer0");
 666
 667         davinci_timer_init(clk);
 668 }
 669
 670 static struct resource dm646x_pll2_resources[] = {
 671         {
 672                 .start  = DAVINCI_PLL2_BASE,
 673                 .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
 674                 .flags  = IORESOURCE_MEM,
 675         },
 676 };
 677
 678 static struct platform_device dm646x_pll2_device = {
 679         .name           = "dm646x-pll2",
 680         .id             = -1,
 681         .resource       = dm646x_pll2_resources,
 682         .num_resources  = ARRAY_SIZE(dm646x_pll2_resources),
 683 };
 684
 685 void __init dm646x_register_clocks(void)
 686 {
 687         /* PLL1 and PSC are registered in dm646x_init_time() */
 688         platform_device_register(&dm646x_pll2_device);
 689 }
 690
 691 static int __init dm646x_init_devices(void)
 692 {
 693         int ret = 0;
 694
 695         if (!cpu_is_davinci_dm646x())
 696                 return 0;
 697
 698         platform_device_register(&dm646x_mdio_device);
 699         platform_device_register(&dm646x_emac_device);
 700
 701         ret = davinci_init_wdt();
 702         if (ret)
 703                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
 704
 705         return ret;
 706 }
 707 postcore_initcall(dm646x_init_devices);