arch/arm/mach-davinci/dm365.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * TI DaVinci DM365 chip specific setup
   4  *
   5  * Copyright (C) 2009 Texas Instruments
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/clk/davinci.h>
  10 #include <linux/clkdev.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/irqchip/irq-davinci-aintc.h>
  16 #include <linux/platform_data/edma.h>
  17 #include <linux/platform_data/gpio-davinci.h>
  18 #include <linux/platform_data/keyscan-davinci.h>
  19 #include <linux/platform_data/spi-davinci.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22 #include <linux/spi/spi.h>
  23
  24 #include <clocksource/timer-davinci.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include "common.h"
  29 #include "cputype.h"
  30 #include "serial.h"
  31 #include "asp.h"
  32 #include "davinci.h"
  33 #include "irqs.h"
  34 #include "mux.h"
  35
  36 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
  37 #define DM365_RTC_BASE                  0x01c69000
  38 #define DM365_KEYSCAN_BASE              0x01c69400
  39 #define DM365_OSD_BASE                  0x01c71c00
  40 #define DM365_VENC_BASE                 0x01c71e00
  41 #define DAVINCI_DM365_VC_BASE           0x01d0c000
  42 #define DAVINCI_DMA_VC_TX               2
  43 #define DAVINCI_DMA_VC_RX               3
  44 #define DM365_EMAC_BASE                 0x01d07000
  45 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
  46 #define DM365_EMAC_CNTRL_OFFSET         0x0000
  47 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
  48 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
  49 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
  50
  51 #define INTMUX          0x18
  52 #define EVTMUX          0x1c
  53
  54
  55 static const struct mux_config dm365_pins[] = {
  56 #ifdef CONFIG_DAVINCI_MUX
  57 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
  58
  59 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
  60 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
  61 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
  62 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
  63 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
  64 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
  65
  66 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
  67 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
  68
  69 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
  70 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
  71 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
  72 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
  73 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
  74 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
  75 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
  76 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
  77
  78 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
  79 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
  80 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
  81 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
  82 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
  83 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
  84
  85 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
  86 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
  87 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
  88 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
  89 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
  90
  91 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
  92 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
  93 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
  94 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
  95 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
  96 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
  97
  98 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
  99 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
 100 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
 101 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
 102 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
 103 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
 104 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
 105 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
 106 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
 107 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
 108 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
 109 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
 110 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
 111 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
 112 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
 113 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
 114 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
 115
 116 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
 117
 118 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
 119 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
 120 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
 121 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
 122 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
 123 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
 124 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
 125 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
 126 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
 127 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
 128 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
 129 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
 130
 131 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
 132 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
 133 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
 134 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
 135 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
 136
 137 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
 138 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
 139 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
 140 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
 141 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
 142
 143 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
 144 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
 145 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
 146 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
 147 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
 148
 149 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
 150 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
 151 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
 152 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
 153 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
 154
 155 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
 156 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
 157 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
 158
 159 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
 160 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
 161 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
 162 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
 163 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
 164 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
 165 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
 166
 167 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
 168 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
 169 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 170 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 171 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 172 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
 173 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
 174 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
 175 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
 176 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 177
 178 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 179 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
 180 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
 181 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
 182 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
 183 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
 184 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
 185 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
 186 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
 187 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 188 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
 189 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
 190 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
 191 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
 192 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
 193 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
 194 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
 195 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 196
 197 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 198 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
 199 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
 200 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 201 #endif
 202 };
 203
 204 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 205
 206 static struct davinci_spi_platform_data dm365_spi0_pdata = {
 207         .version        = SPI_VERSION_1,
 208         .num_chipselect = 2,
 209         .dma_event_q    = EVENTQ_3,
 210         .prescaler_limit = 1,
 211 };
 212
 213 static struct resource dm365_spi0_resources[] = {
 214         {
 215                 .start = 0x01c66000,
 216                 .end   = 0x01c667ff,
 217                 .flags = IORESOURCE_MEM,
 218         },
 219         {
 220                 .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
 221                 .flags = IORESOURCE_IRQ,
 222         },
 223 };
 224
 225 static struct platform_device dm365_spi0_device = {
 226         .name = "spi_davinci",
 227         .id = 0,
 228         .dev = {
 229                 .dma_mask = &dm365_spi0_dma_mask,
 230                 .coherent_dma_mask = DMA_BIT_MASK(32),
 231                 .platform_data = &dm365_spi0_pdata,
 232         },
 233         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
 234         .resource = dm365_spi0_resources,
 235 };
 236
 237 void __init dm365_init_spi0(unsigned chipselect_mask,
 238                 const struct spi_board_info *info, unsigned len)
 239 {
 240         davinci_cfg_reg(DM365_SPI0_SCLK);
 241         davinci_cfg_reg(DM365_SPI0_SDI);
 242         davinci_cfg_reg(DM365_SPI0_SDO);
 243
 244         /* not all slaves will be wired up */
 245         if (chipselect_mask & BIT(0))
 246                 davinci_cfg_reg(DM365_SPI0_SDENA0);
 247         if (chipselect_mask & BIT(1))
 248                 davinci_cfg_reg(DM365_SPI0_SDENA1);
 249
 250         spi_register_board_info(info, len);
 251
 252         platform_device_register(&dm365_spi0_device);
 253 }
 254
 255 static struct resource dm365_gpio_resources[] = {
 256         {       /* registers */
 257                 .start  = DAVINCI_GPIO_BASE,
 258                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         {       /* interrupt */
 262                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
 263                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
 264                 .flags  = IORESOURCE_IRQ,
 265         },
 266         {
 267                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
 268                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
 269                 .flags  = IORESOURCE_IRQ,
 270         },
 271         {
 272                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
 273                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
 274                 .flags  = IORESOURCE_IRQ,
 275         },
 276         {
 277                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
 278                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
 279                 .flags  = IORESOURCE_IRQ,
 280         },
 281         {
 282                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
 283                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
 284                 .flags  = IORESOURCE_IRQ,
 285         },
 286         {
 287                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
 288                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
 289                 .flags  = IORESOURCE_IRQ,
 290         },
 291         {
 292                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
 293                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
 294                 .flags  = IORESOURCE_IRQ,
 295         },
 296         {
 297                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
 298                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
 299                 .flags  = IORESOURCE_IRQ,
 300         },
 301 };
 302
 303 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
 304         .no_auto_base   = true,
 305         .base           = 0,
 306         .ngpio          = 104,
 307         .gpio_unbanked  = 8,
 308 };
 309
 310 int __init dm365_gpio_register(void)
 311 {
 312         return davinci_gpio_register(dm365_gpio_resources,
 313                                      ARRAY_SIZE(dm365_gpio_resources),
 314                                      &dm365_gpio_platform_data);
 315 }
 316
 317 static struct emac_platform_data dm365_emac_pdata = {
 318         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
 319         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
 320         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
 321         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
 322         .version                = EMAC_VERSION_2,
 323 };
 324
 325 static struct resource dm365_emac_resources[] = {
 326         {
 327                 .start  = DM365_EMAC_BASE,
 328                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
 329                 .flags  = IORESOURCE_MEM,
 330         },
 331         {
 332                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
 333                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
 334                 .flags  = IORESOURCE_IRQ,
 335         },
 336         {
 337                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
 338                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
 339                 .flags  = IORESOURCE_IRQ,
 340         },
 341         {
 342                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
 343                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
 344                 .flags  = IORESOURCE_IRQ,
 345         },
 346         {
 347                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
 348                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
 349                 .flags  = IORESOURCE_IRQ,
 350         },
 351 };
 352
 353 static struct platform_device dm365_emac_device = {
 354         .name           = "davinci_emac",
 355         .id             = 1,
 356         .dev = {
 357                 .platform_data  = &dm365_emac_pdata,
 358         },
 359         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
 360         .resource       = dm365_emac_resources,
 361 };
 362
 363 static struct resource dm365_mdio_resources[] = {
 364         {
 365                 .start  = DM365_EMAC_MDIO_BASE,
 366                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
 367                 .flags  = IORESOURCE_MEM,
 368         },
 369 };
 370
 371 static struct platform_device dm365_mdio_device = {
 372         .name           = "davinci_mdio",
 373         .id             = 0,
 374         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
 375         .resource       = dm365_mdio_resources,
 376 };
 377
 378 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 379         [IRQ_VDINT0]                    = 2,
 380         [IRQ_VDINT1]                    = 6,
 381         [IRQ_VDINT2]                    = 6,
 382         [IRQ_HISTINT]                   = 6,
 383         [IRQ_H3AINT]                    = 6,
 384         [IRQ_PRVUINT]                   = 6,
 385         [IRQ_RSZINT]                    = 6,
 386         [IRQ_DM365_INSFINT]             = 7,
 387         [IRQ_VENCINT]                   = 6,
 388         [IRQ_ASQINT]                    = 6,
 389         [IRQ_IMXINT]                    = 6,
 390         [IRQ_DM365_IMCOPINT]            = 4,
 391         [IRQ_USBINT]                    = 4,
 392         [IRQ_DM365_RTOINT]              = 7,
 393         [IRQ_DM365_TINT5]               = 7,
 394         [IRQ_DM365_TINT6]               = 5,
 395         [IRQ_CCINT0]                    = 5,
 396         [IRQ_CCERRINT]                  = 5,
 397         [IRQ_TCERRINT0]                 = 5,
 398         [IRQ_TCERRINT]                  = 7,
 399         [IRQ_PSCIN]                     = 4,
 400         [IRQ_DM365_SPINT2_1]            = 7,
 401         [IRQ_DM365_TINT7]               = 7,
 402         [IRQ_DM365_SDIOINT0]            = 7,
 403         [IRQ_MBXINT]                    = 7,
 404         [IRQ_MBRINT]                    = 7,
 405         [IRQ_MMCINT]                    = 7,
 406         [IRQ_DM365_MMCINT1]             = 7,
 407         [IRQ_DM365_PWMINT3]             = 7,
 408         [IRQ_AEMIFINT]                  = 2,
 409         [IRQ_DM365_SDIOINT1]            = 2,
 410         [IRQ_TINT0_TINT12]              = 7,
 411         [IRQ_TINT0_TINT34]              = 7,
 412         [IRQ_TINT1_TINT12]              = 7,
 413         [IRQ_TINT1_TINT34]              = 7,
 414         [IRQ_PWMINT0]                   = 7,
 415         [IRQ_PWMINT1]                   = 3,
 416         [IRQ_PWMINT2]                   = 3,
 417         [IRQ_I2C]                       = 3,
 418         [IRQ_UARTINT0]                  = 3,
 419         [IRQ_UARTINT1]                  = 3,
 420         [IRQ_DM365_RTCINT]              = 3,
 421         [IRQ_DM365_SPIINT0_0]           = 3,
 422         [IRQ_DM365_SPIINT3_0]           = 3,
 423         [IRQ_DM365_GPIO0]               = 3,
 424         [IRQ_DM365_GPIO1]               = 7,
 425         [IRQ_DM365_GPIO2]               = 4,
 426         [IRQ_DM365_GPIO3]               = 4,
 427         [IRQ_DM365_GPIO4]               = 7,
 428         [IRQ_DM365_GPIO5]               = 7,
 429         [IRQ_DM365_GPIO6]               = 7,
 430         [IRQ_DM365_GPIO7]               = 7,
 431         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
 432         [IRQ_DM365_EMAC_RXPULSE]        = 7,
 433         [IRQ_DM365_EMAC_TXPULSE]        = 7,
 434         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
 435         [IRQ_DM365_GPIO12]              = 7,
 436         [IRQ_DM365_GPIO13]              = 7,
 437         [IRQ_DM365_GPIO14]              = 7,
 438         [IRQ_DM365_GPIO15]              = 7,
 439         [IRQ_DM365_KEYINT]              = 7,
 440         [IRQ_DM365_TCERRINT2]           = 7,
 441         [IRQ_DM365_TCERRINT3]           = 7,
 442         [IRQ_DM365_EMUINT]              = 7,
 443 };
 444
 445 /* Four Transfer Controllers on DM365 */
 446 static s8 dm365_queue_priority_mapping[][2] = {
 447         /* {event queue no, Priority} */
 448         {0, 7},
 449         {1, 7},
 450         {2, 7},
 451         {3, 0},
 452         {-1, -1},
 453 };
 454
 455 static const struct dma_slave_map dm365_edma_map[] = {
 456         { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
 457         { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
 458         { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
 459         { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
 460         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
 461         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
 462         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
 463         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
 464         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
 465         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
 466         { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
 467         { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
 468         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
 469         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
 470         { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
 471         { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
 472 };
 473
 474 static struct edma_soc_info dm365_edma_pdata = {
 475         .queue_priority_mapping = dm365_queue_priority_mapping,
 476         .default_queue          = EVENTQ_3,
 477         .slave_map              = dm365_edma_map,
 478         .slavecnt               = ARRAY_SIZE(dm365_edma_map),
 479 };
 480
 481 static struct resource edma_resources[] = {
 482         {
 483                 .name   = "edma3_cc",
 484                 .start  = 0x01c00000,
 485                 .end    = 0x01c00000 + SZ_64K - 1,
 486                 .flags  = IORESOURCE_MEM,
 487         },
 488         {
 489                 .name   = "edma3_tc0",
 490                 .start  = 0x01c10000,
 491                 .end    = 0x01c10000 + SZ_1K - 1,
 492                 .flags  = IORESOURCE_MEM,
 493         },
 494         {
 495                 .name   = "edma3_tc1",
 496                 .start  = 0x01c10400,
 497                 .end    = 0x01c10400 + SZ_1K - 1,
 498                 .flags  = IORESOURCE_MEM,
 499         },
 500         {
 501                 .name   = "edma3_tc2",
 502                 .start  = 0x01c10800,
 503                 .end    = 0x01c10800 + SZ_1K - 1,
 504                 .flags  = IORESOURCE_MEM,
 505         },
 506         {
 507                 .name   = "edma3_tc3",
 508                 .start  = 0x01c10c00,
 509                 .end    = 0x01c10c00 + SZ_1K - 1,
 510                 .flags  = IORESOURCE_MEM,
 511         },
 512         {
 513                 .name   = "edma3_ccint",
 514                 .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
 515                 .flags  = IORESOURCE_IRQ,
 516         },
 517         {
 518                 .name   = "edma3_ccerrint",
 519                 .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
 520                 .flags  = IORESOURCE_IRQ,
 521         },
 522         /* not using TC*_ERR */
 523 };
 524
 525 static const struct platform_device_info dm365_edma_device __initconst = {
 526         .name           = "edma",
 527         .id             = 0,
 528         .dma_mask       = DMA_BIT_MASK(32),
 529         .res            = edma_resources,
 530         .num_res        = ARRAY_SIZE(edma_resources),
 531         .data           = &dm365_edma_pdata,
 532         .size_data      = sizeof(dm365_edma_pdata),
 533 };
 534
 535 static struct resource dm365_asp_resources[] = {
 536         {
 537                 .name   = "mpu",
 538                 .start  = DAVINCI_DM365_ASP0_BASE,
 539                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 540                 .flags  = IORESOURCE_MEM,
 541         },
 542         {
 543                 .start  = DAVINCI_DMA_ASP0_TX,
 544                 .end    = DAVINCI_DMA_ASP0_TX,
 545                 .flags  = IORESOURCE_DMA,
 546         },
 547         {
 548                 .start  = DAVINCI_DMA_ASP0_RX,
 549                 .end    = DAVINCI_DMA_ASP0_RX,
 550                 .flags  = IORESOURCE_DMA,
 551         },
 552 };
 553
 554 static struct platform_device dm365_asp_device = {
 555         .name           = "davinci-mcbsp",
 556         .id             = -1,
 557         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
 558         .resource       = dm365_asp_resources,
 559 };
 560
 561 static struct resource dm365_vc_resources[] = {
 562         {
 563                 .start  = DAVINCI_DM365_VC_BASE,
 564                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         {
 568                 .start  = DAVINCI_DMA_VC_TX,
 569                 .end    = DAVINCI_DMA_VC_TX,
 570                 .flags  = IORESOURCE_DMA,
 571         },
 572         {
 573                 .start  = DAVINCI_DMA_VC_RX,
 574                 .end    = DAVINCI_DMA_VC_RX,
 575                 .flags  = IORESOURCE_DMA,
 576         },
 577 };
 578
 579 static struct platform_device dm365_vc_device = {
 580         .name           = "davinci_voicecodec",
 581         .id             = -1,
 582         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
 583         .resource       = dm365_vc_resources,
 584 };
 585
 586 static struct resource dm365_rtc_resources[] = {
 587         {
 588                 .start = DM365_RTC_BASE,
 589                 .end = DM365_RTC_BASE + SZ_1K - 1,
 590                 .flags = IORESOURCE_MEM,
 591         },
 592         {
 593                 .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
 594                 .flags = IORESOURCE_IRQ,
 595         },
 596 };
 597
 598 static struct platform_device dm365_rtc_device = {
 599         .name = "rtc_davinci",
 600         .id = 0,
 601         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
 602         .resource = dm365_rtc_resources,
 603 };
 604
 605 static struct map_desc dm365_io_desc[] = {
 606         {
 607                 .virtual        = IO_VIRT,
 608                 .pfn            = __phys_to_pfn(IO_PHYS),
 609                 .length         = IO_SIZE,
 610                 .type           = MT_DEVICE
 611         },
 612 };
 613
 614 static struct resource dm365_ks_resources[] = {
 615         {
 616                 /* registers */
 617                 .start = DM365_KEYSCAN_BASE,
 618                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
 619                 .flags = IORESOURCE_MEM,
 620         },
 621         {
 622                 /* interrupt */
 623                 .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
 624                 .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
 625                 .flags = IORESOURCE_IRQ,
 626         },
 627 };
 628
 629 static struct platform_device dm365_ks_device = {
 630         .name           = "davinci_keyscan",
 631         .id             = 0,
 632         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
 633         .resource       = dm365_ks_resources,
 634 };
 635
 636 /* Contents of JTAG ID register used to identify exact cpu type */
 637 static struct davinci_id dm365_ids[] = {
 638         {
 639                 .variant        = 0x0,
 640                 .part_no        = 0xb83e,
 641                 .manufacturer   = 0x017,
 642                 .cpu_id         = DAVINCI_CPU_ID_DM365,
 643                 .name           = "dm365_rev1.1",
 644         },
 645         {
 646                 .variant        = 0x8,
 647                 .part_no        = 0xb83e,
 648                 .manufacturer   = 0x017,
 649                 .cpu_id         = DAVINCI_CPU_ID_DM365,
 650                 .name           = "dm365_rev1.2",
 651         },
 652 };
 653
 654 /*
 655  * Bottom half of timer0 is used for clockevent, top half is used for
 656  * clocksource.
 657  */
 658 static const struct davinci_timer_cfg dm365_timer_cfg = {
 659         .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
 660         .irq = {
 661                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
 662                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
 663         },
 664 };
 665
 666 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
 667
 668 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
 669         {
 670                 .mapbase        = DAVINCI_UART0_BASE,
 671                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
 672                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 673                                   UPF_IOREMAP,
 674                 .iotype         = UPIO_MEM,
 675                 .regshift       = 2,
 676         },
 677         {
 678                 .flags  = 0,
 679         }
 680 };
 681 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
 682         {
 683                 .mapbase        = DM365_UART1_BASE,
 684                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
 685                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 686                                   UPF_IOREMAP,
 687                 .iotype         = UPIO_MEM,
 688                 .regshift       = 2,
 689         },
 690         {
 691                 .flags  = 0,
 692         }
 693 };
 694
 695 struct platform_device dm365_serial_device[] = {
 696         {
 697                 .name                   = "serial8250",
 698                 .id                     = PLAT8250_DEV_PLATFORM,
 699                 .dev                    = {
 700                         .platform_data  = dm365_serial0_platform_data,
 701                 }
 702         },
 703         {
 704                 .name                   = "serial8250",
 705                 .id                     = PLAT8250_DEV_PLATFORM1,
 706                 .dev                    = {
 707                         .platform_data  = dm365_serial1_platform_data,
 708                 }
 709         },
 710         {
 711         }
 712 };
 713
 714 static const struct davinci_soc_info davinci_soc_info_dm365 = {
 715         .io_desc                = dm365_io_desc,
 716         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
 717         .jtag_id_reg            = 0x01c40028,
 718         .ids                    = dm365_ids,
 719         .ids_num                = ARRAY_SIZE(dm365_ids),
 720         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 721         .pinmux_pins            = dm365_pins,
 722         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
 723         .emac_pdata             = &dm365_emac_pdata,
 724         .sram_dma               = 0x00010000,
 725         .sram_len               = SZ_32K,
 726 };
 727
 728 void __init dm365_init_asp(void)
 729 {
 730         davinci_cfg_reg(DM365_MCBSP0_BDX);
 731         davinci_cfg_reg(DM365_MCBSP0_X);
 732         davinci_cfg_reg(DM365_MCBSP0_BFSX);
 733         davinci_cfg_reg(DM365_MCBSP0_BDR);
 734         davinci_cfg_reg(DM365_MCBSP0_R);
 735         davinci_cfg_reg(DM365_MCBSP0_BFSR);
 736         davinci_cfg_reg(DM365_EVT2_ASP_TX);
 737         davinci_cfg_reg(DM365_EVT3_ASP_RX);
 738         platform_device_register(&dm365_asp_device);
 739 }
 740
 741 void __init dm365_init_vc(void)
 742 {
 743         davinci_cfg_reg(DM365_EVT2_VC_TX);
 744         davinci_cfg_reg(DM365_EVT3_VC_RX);
 745         platform_device_register(&dm365_vc_device);
 746 }
 747
 748 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
 749 {
 750         dm365_ks_device.dev.platform_data = pdata;
 751         platform_device_register(&dm365_ks_device);
 752 }
 753
 754 void __init dm365_init_rtc(void)
 755 {
 756         davinci_cfg_reg(DM365_INT_PRTCSS);
 757         platform_device_register(&dm365_rtc_device);
 758 }
 759
 760 void __init dm365_init(void)
 761 {
 762         davinci_common_init(&davinci_soc_info_dm365);
 763         davinci_map_sysmod();
 764 }
 765
 766 void __init dm365_init_time(void)
 767 {
 768         void __iomem *pll1, *pll2, *psc;
 769         struct clk *clk;
 770         int rv;
 771
 772         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
 773
 774         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 775         dm365_pll1_init(NULL, pll1, NULL);
 776
 777         pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
 778         dm365_pll2_init(NULL, pll2, NULL);
 779
 780         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 781         dm365_psc_init(NULL, psc);
 782
 783         clk = clk_get(NULL, "timer0");
 784         if (WARN_ON(IS_ERR(clk))) {
 785                 pr_err("Unable to get the timer clock\n");
 786                 return;
 787         }
 788
 789         rv = davinci_timer_register(clk, &dm365_timer_cfg);
 790         WARN(rv, "Unable to register the timer: %d\n", rv);
 791 }
 792
 793 void __init dm365_register_clocks(void)
 794 {
 795         /* all clocks are currently registered in dm365_init_time() */
 796 }
 797
 798 static struct resource dm365_vpss_resources[] = {
 799         {
 800                 /* VPSS ISP5 Base address */
 801                 .name           = "isp5",
 802                 .start          = 0x01c70000,
 803                 .end            = 0x01c70000 + 0xff,
 804                 .flags          = IORESOURCE_MEM,
 805         },
 806         {
 807                 /* VPSS CLK Base address */
 808                 .name           = "vpss",
 809                 .start          = 0x01c70200,
 810                 .end            = 0x01c70200 + 0xff,
 811                 .flags          = IORESOURCE_MEM,
 812         },
 813 };
 814
 815 static struct platform_device dm365_vpss_device = {
 816        .name                   = "vpss",
 817        .id                     = -1,
 818        .dev.platform_data      = "dm365_vpss",
 819        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
 820        .resource               = dm365_vpss_resources,
 821 };
 822
 823 static struct resource vpfe_resources[] = {
 824         {
 825                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 826                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 827                 .flags          = IORESOURCE_IRQ,
 828         },
 829         {
 830                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 831                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 832                 .flags          = IORESOURCE_IRQ,
 833         },
 834 };
 835
 836 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 837 static struct platform_device vpfe_capture_dev = {
 838         .name           = CAPTURE_DRV_NAME,
 839         .id             = -1,
 840         .num_resources  = ARRAY_SIZE(vpfe_resources),
 841         .resource       = vpfe_resources,
 842         .dev = {
 843                 .dma_mask               = &vpfe_capture_dma_mask,
 844                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 845         },
 846 };
 847
 848 static void dm365_isif_setup_pinmux(void)
 849 {
 850         davinci_cfg_reg(DM365_VIN_CAM_WEN);
 851         davinci_cfg_reg(DM365_VIN_CAM_VD);
 852         davinci_cfg_reg(DM365_VIN_CAM_HD);
 853         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
 854         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
 855 }
 856
 857 static struct resource isif_resource[] = {
 858         /* ISIF Base address */
 859         {
 860                 .start          = 0x01c71000,
 861                 .end            = 0x01c71000 + 0x1ff,
 862                 .flags          = IORESOURCE_MEM,
 863         },
 864         /* ISIF Linearization table 0 */
 865         {
 866                 .start          = 0x1C7C000,
 867                 .end            = 0x1C7C000 + 0x2ff,
 868                 .flags          = IORESOURCE_MEM,
 869         },
 870         /* ISIF Linearization table 1 */
 871         {
 872                 .start          = 0x1C7C400,
 873                 .end            = 0x1C7C400 + 0x2ff,
 874                 .flags          = IORESOURCE_MEM,
 875         },
 876 };
 877 static struct platform_device dm365_isif_dev = {
 878         .name           = "isif",
 879         .id             = -1,
 880         .num_resources  = ARRAY_SIZE(isif_resource),
 881         .resource       = isif_resource,
 882         .dev = {
 883                 .dma_mask               = &vpfe_capture_dma_mask,
 884                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 885                 .platform_data          = dm365_isif_setup_pinmux,
 886         },
 887 };
 888
 889 static struct resource dm365_osd_resources[] = {
 890         {
 891                 .start = DM365_OSD_BASE,
 892                 .end   = DM365_OSD_BASE + 0xff,
 893                 .flags = IORESOURCE_MEM,
 894         },
 895 };
 896
 897 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
 898
 899 static struct platform_device dm365_osd_dev = {
 900         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
 901         .id             = -1,
 902         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
 903         .resource       = dm365_osd_resources,
 904         .dev            = {
 905                 .dma_mask               = &dm365_video_dma_mask,
 906                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 907         },
 908 };
 909
 910 static struct resource dm365_venc_resources[] = {
 911         {
 912                 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 913                 .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 914                 .flags = IORESOURCE_IRQ,
 915         },
 916         /* venc registers io space */
 917         {
 918                 .start = DM365_VENC_BASE,
 919                 .end   = DM365_VENC_BASE + 0x177,
 920                 .flags = IORESOURCE_MEM,
 921         },
 922         /* vdaccfg registers io space */
 923         {
 924                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
 925                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
 926                 .flags = IORESOURCE_MEM,
 927         },
 928 };
 929
 930 static struct resource dm365_v4l2_disp_resources[] = {
 931         {
 932                 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 933                 .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 934                 .flags = IORESOURCE_IRQ,
 935         },
 936         /* venc registers io space */
 937         {
 938                 .start = DM365_VENC_BASE,
 939                 .end   = DM365_VENC_BASE + 0x177,
 940                 .flags = IORESOURCE_MEM,
 941         },
 942 };
 943
 944 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
 945 {
 946         switch (if_type) {
 947         case MEDIA_BUS_FMT_SGRBG8_1X8:
 948                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
 949                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
 950                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
 951                 break;
 952         case MEDIA_BUS_FMT_YUYV10_1X20:
 953                 if (field)
 954                         davinci_cfg_reg(DM365_VOUT_FIELD);
 955                 else
 956                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
 957                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
 958                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
 959                 break;
 960         default:
 961                 return -EINVAL;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
 968                                   unsigned int pclock)
 969 {
 970         void __iomem *vpss_clkctl_reg;
 971         u32 val;
 972
 973         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
 974
 975         switch (type) {
 976         case VPBE_ENC_STD:
 977                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
 978                 break;
 979         case VPBE_ENC_DV_TIMINGS:
 980                 if (pclock <= 27000000) {
 981                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
 982                 } else {
 983                         /* set sysclk4 to output 74.25 MHz from pll1 */
 984                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
 985                               VPSS_VENCCLKEN_ENABLE;
 986                 }
 987                 break;
 988         default:
 989                 return -EINVAL;
 990         }
 991         writel(val, vpss_clkctl_reg);
 992
 993         return 0;
 994 }
 995
 996 static struct platform_device dm365_vpbe_display = {
 997         .name           = "vpbe-v4l2",
 998         .id             = -1,
 999         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1000         .resource       = dm365_v4l2_disp_resources,
1001         .dev            = {
1002                 .dma_mask               = &dm365_video_dma_mask,
1003                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1004         },
1005 };
1006
1007 static struct venc_platform_data dm365_venc_pdata = {
1008         .setup_pinmux   = dm365_vpbe_setup_pinmux,
1009         .setup_clock    = dm365_venc_setup_clock,
1010 };
1011
1012 static struct platform_device dm365_venc_dev = {
1013         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
1014         .id             = -1,
1015         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1016         .resource       = dm365_venc_resources,
1017         .dev            = {
1018                 .dma_mask               = &dm365_video_dma_mask,
1019                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1020                 .platform_data          = (void *)&dm365_venc_pdata,
1021         },
1022 };
1023
1024 static struct platform_device dm365_vpbe_dev = {
1025         .name           = "vpbe_controller",
1026         .id             = -1,
1027         .dev            = {
1028                 .dma_mask               = &dm365_video_dma_mask,
1029                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1030         },
1031 };
1032
1033 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1034                                 struct vpbe_config *vpbe_cfg)
1035 {
1036         if (vpfe_cfg || vpbe_cfg)
1037                 platform_device_register(&dm365_vpss_device);
1038
1039         if (vpfe_cfg) {
1040                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1041                 platform_device_register(&dm365_isif_dev);
1042                 platform_device_register(&vpfe_capture_dev);
1043         }
1044         if (vpbe_cfg) {
1045                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1046                 platform_device_register(&dm365_osd_dev);
1047                 platform_device_register(&dm365_venc_dev);
1048                 platform_device_register(&dm365_vpbe_dev);
1049                 platform_device_register(&dm365_vpbe_display);
1050         }
1051
1052         return 0;
1053 }
1054
1055 static const struct davinci_aintc_config dm365_aintc_config = {
1056         .reg = {
1057                 .start          = DAVINCI_ARM_INTC_BASE,
1058                 .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1059                 .flags          = IORESOURCE_MEM,
1060         },
1061         .num_irqs               = 64,
1062         .prios                  = dm365_default_priorities,
1063 };
1064
1065 void __init dm365_init_irq(void)
1066 {
1067         davinci_aintc_init(&dm365_aintc_config);
1068 }
1069
1070 static int __init dm365_init_devices(void)
1071 {
1072         struct platform_device *edma_pdev;
1073         int ret = 0;
1074
1075         if (!cpu_is_davinci_dm365())
1076                 return 0;
1077
1078         davinci_cfg_reg(DM365_INT_EDMA_CC);
1079         edma_pdev = platform_device_register_full(&dm365_edma_device);
1080         if (IS_ERR(edma_pdev)) {
1081                 pr_warn("%s: Failed to register eDMA\n", __func__);
1082                 return PTR_ERR(edma_pdev);
1083         }
1084
1085         platform_device_register(&dm365_mdio_device);
1086         platform_device_register(&dm365_emac_device);
1087
1088         ret = davinci_init_wdt();
1089         if (ret)
1090                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1091
1092         return ret;
1093 }
1094 postcore_initcall(dm365_init_devices);