arch/arm/mach-davinci/dm365.c

   1 /*
   2  * TI DaVinci DM365 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/clk/davinci.h>
  18 #include <linux/clkdev.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/irqchip/irq-davinci-aintc.h>
  24 #include <linux/platform_data/edma.h>
  25 #include <linux/platform_data/gpio-davinci.h>
  26 #include <linux/platform_data/keyscan-davinci.h>
  27 #include <linux/platform_data/spi-davinci.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/serial_8250.h>
  30 #include <linux/spi/spi.h>
  31
  32 #include <clocksource/timer-davinci.h>
  33
  34 #include <asm/mach/map.h>
  35
  36 #include "common.h"
  37 #include "cputype.h"
  38 #include "serial.h"
  39 #include "asp.h"
  40 #include "davinci.h"
  41 #include "irqs.h"
  42 #include "mux.h"
  43
  44 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
  45 #define DM365_RTC_BASE                  0x01c69000
  46 #define DM365_KEYSCAN_BASE              0x01c69400
  47 #define DM365_OSD_BASE                  0x01c71c00
  48 #define DM365_VENC_BASE                 0x01c71e00
  49 #define DAVINCI_DM365_VC_BASE           0x01d0c000
  50 #define DAVINCI_DMA_VC_TX               2
  51 #define DAVINCI_DMA_VC_RX               3
  52 #define DM365_EMAC_BASE                 0x01d07000
  53 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
  54 #define DM365_EMAC_CNTRL_OFFSET         0x0000
  55 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
  56 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
  57 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
  58
  59 #define INTMUX          0x18
  60 #define EVTMUX          0x1c
  61
  62
  63 static const struct mux_config dm365_pins[] = {
  64 #ifdef CONFIG_DAVINCI_MUX
  65 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
  66
  67 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
  68 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
  69 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
  70 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
  71 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
  72 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
  73
  74 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
  75 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
  76
  77 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
  78 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
  79 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
  80 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
  81 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
  82 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
  83 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
  84 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
  85
  86 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
  87 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
  88 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
  89 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
  90 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
  91 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
  92
  93 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
  94 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
  95 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
  96 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
  97 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
  98
  99 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
 100 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
 101 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
 102 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
 103 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
 104 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
 105
 106 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
 107 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
 108 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
 109 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
 110 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
 111 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
 112 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
 113 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
 114 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
 115 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
 116 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
 117 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
 118 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
 119 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
 120 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
 121 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
 122 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
 123
 124 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
 125
 126 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
 127 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
 128 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
 129 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
 130 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
 131 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
 132 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
 133 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
 134 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
 135 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
 136 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
 137 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
 138
 139 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
 140 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
 141 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
 142 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
 143 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
 144
 145 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
 146 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
 147 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
 148 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
 149 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
 150
 151 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
 152 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
 153 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
 154 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
 155 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
 156
 157 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
 158 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
 159 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
 160 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
 161 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
 162
 163 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
 164 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
 165 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
 166
 167 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
 168 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
 169 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
 170 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
 171 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
 172 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
 173 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
 174
 175 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
 176 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
 177 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 178 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 179 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 180 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
 181 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
 182 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
 183 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
 184 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 185
 186 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 187 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
 188 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
 189 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
 190 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
 191 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
 192 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
 193 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
 194 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
 195 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 196 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
 197 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
 198 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
 199 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
 200 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
 201 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
 202 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
 203 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 204
 205 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 206 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
 207 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
 208 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 209 #endif
 210 };
 211
 212 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 213
 214 static struct davinci_spi_platform_data dm365_spi0_pdata = {
 215         .version        = SPI_VERSION_1,
 216         .num_chipselect = 2,
 217         .dma_event_q    = EVENTQ_3,
 218         .prescaler_limit = 1,
 219 };
 220
 221 static struct resource dm365_spi0_resources[] = {
 222         {
 223                 .start = 0x01c66000,
 224                 .end   = 0x01c667ff,
 225                 .flags = IORESOURCE_MEM,
 226         },
 227         {
 228                 .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
 229                 .flags = IORESOURCE_IRQ,
 230         },
 231 };
 232
 233 static struct platform_device dm365_spi0_device = {
 234         .name = "spi_davinci",
 235         .id = 0,
 236         .dev = {
 237                 .dma_mask = &dm365_spi0_dma_mask,
 238                 .coherent_dma_mask = DMA_BIT_MASK(32),
 239                 .platform_data = &dm365_spi0_pdata,
 240         },
 241         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
 242         .resource = dm365_spi0_resources,
 243 };
 244
 245 void __init dm365_init_spi0(unsigned chipselect_mask,
 246                 const struct spi_board_info *info, unsigned len)
 247 {
 248         davinci_cfg_reg(DM365_SPI0_SCLK);
 249         davinci_cfg_reg(DM365_SPI0_SDI);
 250         davinci_cfg_reg(DM365_SPI0_SDO);
 251
 252         /* not all slaves will be wired up */
 253         if (chipselect_mask & BIT(0))
 254                 davinci_cfg_reg(DM365_SPI0_SDENA0);
 255         if (chipselect_mask & BIT(1))
 256                 davinci_cfg_reg(DM365_SPI0_SDENA1);
 257
 258         spi_register_board_info(info, len);
 259
 260         platform_device_register(&dm365_spi0_device);
 261 }
 262
 263 static struct resource dm365_gpio_resources[] = {
 264         {       /* registers */
 265                 .start  = DAVINCI_GPIO_BASE,
 266                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 267                 .flags  = IORESOURCE_MEM,
 268         },
 269         {       /* interrupt */
 270                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
 271                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
 272                 .flags  = IORESOURCE_IRQ,
 273         },
 274         {
 275                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
 276                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
 277                 .flags  = IORESOURCE_IRQ,
 278         },
 279         {
 280                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
 281                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
 282                 .flags  = IORESOURCE_IRQ,
 283         },
 284         {
 285                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
 286                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
 287                 .flags  = IORESOURCE_IRQ,
 288         },
 289         {
 290                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
 291                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
 292                 .flags  = IORESOURCE_IRQ,
 293         },
 294         {
 295                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
 296                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
 297                 .flags  = IORESOURCE_IRQ,
 298         },
 299         {
 300                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
 301                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
 302                 .flags  = IORESOURCE_IRQ,
 303         },
 304         {
 305                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
 306                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
 307                 .flags  = IORESOURCE_IRQ,
 308         },
 309 };
 310
 311 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
 312         .no_auto_base   = true,
 313         .base           = 0,
 314         .ngpio          = 104,
 315         .gpio_unbanked  = 8,
 316 };
 317
 318 int __init dm365_gpio_register(void)
 319 {
 320         return davinci_gpio_register(dm365_gpio_resources,
 321                                      ARRAY_SIZE(dm365_gpio_resources),
 322                                      &dm365_gpio_platform_data);
 323 }
 324
 325 static struct emac_platform_data dm365_emac_pdata = {
 326         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
 327         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
 328         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
 329         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
 330         .version                = EMAC_VERSION_2,
 331 };
 332
 333 static struct resource dm365_emac_resources[] = {
 334         {
 335                 .start  = DM365_EMAC_BASE,
 336                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
 337                 .flags  = IORESOURCE_MEM,
 338         },
 339         {
 340                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
 341                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
 342                 .flags  = IORESOURCE_IRQ,
 343         },
 344         {
 345                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
 346                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
 347                 .flags  = IORESOURCE_IRQ,
 348         },
 349         {
 350                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
 351                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
 352                 .flags  = IORESOURCE_IRQ,
 353         },
 354         {
 355                 .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
 356                 .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
 357                 .flags  = IORESOURCE_IRQ,
 358         },
 359 };
 360
 361 static struct platform_device dm365_emac_device = {
 362         .name           = "davinci_emac",
 363         .id             = 1,
 364         .dev = {
 365                 .platform_data  = &dm365_emac_pdata,
 366         },
 367         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
 368         .resource       = dm365_emac_resources,
 369 };
 370
 371 static struct resource dm365_mdio_resources[] = {
 372         {
 373                 .start  = DM365_EMAC_MDIO_BASE,
 374                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
 375                 .flags  = IORESOURCE_MEM,
 376         },
 377 };
 378
 379 static struct platform_device dm365_mdio_device = {
 380         .name           = "davinci_mdio",
 381         .id             = 0,
 382         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
 383         .resource       = dm365_mdio_resources,
 384 };
 385
 386 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 387         [IRQ_VDINT0]                    = 2,
 388         [IRQ_VDINT1]                    = 6,
 389         [IRQ_VDINT2]                    = 6,
 390         [IRQ_HISTINT]                   = 6,
 391         [IRQ_H3AINT]                    = 6,
 392         [IRQ_PRVUINT]                   = 6,
 393         [IRQ_RSZINT]                    = 6,
 394         [IRQ_DM365_INSFINT]             = 7,
 395         [IRQ_VENCINT]                   = 6,
 396         [IRQ_ASQINT]                    = 6,
 397         [IRQ_IMXINT]                    = 6,
 398         [IRQ_DM365_IMCOPINT]            = 4,
 399         [IRQ_USBINT]                    = 4,
 400         [IRQ_DM365_RTOINT]              = 7,
 401         [IRQ_DM365_TINT5]               = 7,
 402         [IRQ_DM365_TINT6]               = 5,
 403         [IRQ_CCINT0]                    = 5,
 404         [IRQ_CCERRINT]                  = 5,
 405         [IRQ_TCERRINT0]                 = 5,
 406         [IRQ_TCERRINT]                  = 7,
 407         [IRQ_PSCIN]                     = 4,
 408         [IRQ_DM365_SPINT2_1]            = 7,
 409         [IRQ_DM365_TINT7]               = 7,
 410         [IRQ_DM365_SDIOINT0]            = 7,
 411         [IRQ_MBXINT]                    = 7,
 412         [IRQ_MBRINT]                    = 7,
 413         [IRQ_MMCINT]                    = 7,
 414         [IRQ_DM365_MMCINT1]             = 7,
 415         [IRQ_DM365_PWMINT3]             = 7,
 416         [IRQ_AEMIFINT]                  = 2,
 417         [IRQ_DM365_SDIOINT1]            = 2,
 418         [IRQ_TINT0_TINT12]              = 7,
 419         [IRQ_TINT0_TINT34]              = 7,
 420         [IRQ_TINT1_TINT12]              = 7,
 421         [IRQ_TINT1_TINT34]              = 7,
 422         [IRQ_PWMINT0]                   = 7,
 423         [IRQ_PWMINT1]                   = 3,
 424         [IRQ_PWMINT2]                   = 3,
 425         [IRQ_I2C]                       = 3,
 426         [IRQ_UARTINT0]                  = 3,
 427         [IRQ_UARTINT1]                  = 3,
 428         [IRQ_DM365_RTCINT]              = 3,
 429         [IRQ_DM365_SPIINT0_0]           = 3,
 430         [IRQ_DM365_SPIINT3_0]           = 3,
 431         [IRQ_DM365_GPIO0]               = 3,
 432         [IRQ_DM365_GPIO1]               = 7,
 433         [IRQ_DM365_GPIO2]               = 4,
 434         [IRQ_DM365_GPIO3]               = 4,
 435         [IRQ_DM365_GPIO4]               = 7,
 436         [IRQ_DM365_GPIO5]               = 7,
 437         [IRQ_DM365_GPIO6]               = 7,
 438         [IRQ_DM365_GPIO7]               = 7,
 439         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
 440         [IRQ_DM365_EMAC_RXPULSE]        = 7,
 441         [IRQ_DM365_EMAC_TXPULSE]        = 7,
 442         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
 443         [IRQ_DM365_GPIO12]              = 7,
 444         [IRQ_DM365_GPIO13]              = 7,
 445         [IRQ_DM365_GPIO14]              = 7,
 446         [IRQ_DM365_GPIO15]              = 7,
 447         [IRQ_DM365_KEYINT]              = 7,
 448         [IRQ_DM365_TCERRINT2]           = 7,
 449         [IRQ_DM365_TCERRINT3]           = 7,
 450         [IRQ_DM365_EMUINT]              = 7,
 451 };
 452
 453 /* Four Transfer Controllers on DM365 */
 454 static s8 dm365_queue_priority_mapping[][2] = {
 455         /* {event queue no, Priority} */
 456         {0, 7},
 457         {1, 7},
 458         {2, 7},
 459         {3, 0},
 460         {-1, -1},
 461 };
 462
 463 static const struct dma_slave_map dm365_edma_map[] = {
 464         { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
 465         { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
 466         { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
 467         { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
 468         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
 469         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
 470         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
 471         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
 472         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
 473         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
 474         { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
 475         { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
 476         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
 477         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
 478         { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
 479         { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
 480 };
 481
 482 static struct edma_soc_info dm365_edma_pdata = {
 483         .queue_priority_mapping = dm365_queue_priority_mapping,
 484         .default_queue          = EVENTQ_3,
 485         .slave_map              = dm365_edma_map,
 486         .slavecnt               = ARRAY_SIZE(dm365_edma_map),
 487 };
 488
 489 static struct resource edma_resources[] = {
 490         {
 491                 .name   = "edma3_cc",
 492                 .start  = 0x01c00000,
 493                 .end    = 0x01c00000 + SZ_64K - 1,
 494                 .flags  = IORESOURCE_MEM,
 495         },
 496         {
 497                 .name   = "edma3_tc0",
 498                 .start  = 0x01c10000,
 499                 .end    = 0x01c10000 + SZ_1K - 1,
 500                 .flags  = IORESOURCE_MEM,
 501         },
 502         {
 503                 .name   = "edma3_tc1",
 504                 .start  = 0x01c10400,
 505                 .end    = 0x01c10400 + SZ_1K - 1,
 506                 .flags  = IORESOURCE_MEM,
 507         },
 508         {
 509                 .name   = "edma3_tc2",
 510                 .start  = 0x01c10800,
 511                 .end    = 0x01c10800 + SZ_1K - 1,
 512                 .flags  = IORESOURCE_MEM,
 513         },
 514         {
 515                 .name   = "edma3_tc3",
 516                 .start  = 0x01c10c00,
 517                 .end    = 0x01c10c00 + SZ_1K - 1,
 518                 .flags  = IORESOURCE_MEM,
 519         },
 520         {
 521                 .name   = "edma3_ccint",
 522                 .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
 523                 .flags  = IORESOURCE_IRQ,
 524         },
 525         {
 526                 .name   = "edma3_ccerrint",
 527                 .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
 528                 .flags  = IORESOURCE_IRQ,
 529         },
 530         /* not using TC*_ERR */
 531 };
 532
 533 static const struct platform_device_info dm365_edma_device __initconst = {
 534         .name           = "edma",
 535         .id             = 0,
 536         .dma_mask       = DMA_BIT_MASK(32),
 537         .res            = edma_resources,
 538         .num_res        = ARRAY_SIZE(edma_resources),
 539         .data           = &dm365_edma_pdata,
 540         .size_data      = sizeof(dm365_edma_pdata),
 541 };
 542
 543 static struct resource dm365_asp_resources[] = {
 544         {
 545                 .name   = "mpu",
 546                 .start  = DAVINCI_DM365_ASP0_BASE,
 547                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 548                 .flags  = IORESOURCE_MEM,
 549         },
 550         {
 551                 .start  = DAVINCI_DMA_ASP0_TX,
 552                 .end    = DAVINCI_DMA_ASP0_TX,
 553                 .flags  = IORESOURCE_DMA,
 554         },
 555         {
 556                 .start  = DAVINCI_DMA_ASP0_RX,
 557                 .end    = DAVINCI_DMA_ASP0_RX,
 558                 .flags  = IORESOURCE_DMA,
 559         },
 560 };
 561
 562 static struct platform_device dm365_asp_device = {
 563         .name           = "davinci-mcbsp",
 564         .id             = -1,
 565         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
 566         .resource       = dm365_asp_resources,
 567 };
 568
 569 static struct resource dm365_vc_resources[] = {
 570         {
 571                 .start  = DAVINCI_DM365_VC_BASE,
 572                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
 573                 .flags  = IORESOURCE_MEM,
 574         },
 575         {
 576                 .start  = DAVINCI_DMA_VC_TX,
 577                 .end    = DAVINCI_DMA_VC_TX,
 578                 .flags  = IORESOURCE_DMA,
 579         },
 580         {
 581                 .start  = DAVINCI_DMA_VC_RX,
 582                 .end    = DAVINCI_DMA_VC_RX,
 583                 .flags  = IORESOURCE_DMA,
 584         },
 585 };
 586
 587 static struct platform_device dm365_vc_device = {
 588         .name           = "davinci_voicecodec",
 589         .id             = -1,
 590         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
 591         .resource       = dm365_vc_resources,
 592 };
 593
 594 static struct resource dm365_rtc_resources[] = {
 595         {
 596                 .start = DM365_RTC_BASE,
 597                 .end = DM365_RTC_BASE + SZ_1K - 1,
 598                 .flags = IORESOURCE_MEM,
 599         },
 600         {
 601                 .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
 602                 .flags = IORESOURCE_IRQ,
 603         },
 604 };
 605
 606 static struct platform_device dm365_rtc_device = {
 607         .name = "rtc_davinci",
 608         .id = 0,
 609         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
 610         .resource = dm365_rtc_resources,
 611 };
 612
 613 static struct map_desc dm365_io_desc[] = {
 614         {
 615                 .virtual        = IO_VIRT,
 616                 .pfn            = __phys_to_pfn(IO_PHYS),
 617                 .length         = IO_SIZE,
 618                 .type           = MT_DEVICE
 619         },
 620 };
 621
 622 static struct resource dm365_ks_resources[] = {
 623         {
 624                 /* registers */
 625                 .start = DM365_KEYSCAN_BASE,
 626                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
 627                 .flags = IORESOURCE_MEM,
 628         },
 629         {
 630                 /* interrupt */
 631                 .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
 632                 .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
 633                 .flags = IORESOURCE_IRQ,
 634         },
 635 };
 636
 637 static struct platform_device dm365_ks_device = {
 638         .name           = "davinci_keyscan",
 639         .id             = 0,
 640         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
 641         .resource       = dm365_ks_resources,
 642 };
 643
 644 /* Contents of JTAG ID register used to identify exact cpu type */
 645 static struct davinci_id dm365_ids[] = {
 646         {
 647                 .variant        = 0x0,
 648                 .part_no        = 0xb83e,
 649                 .manufacturer   = 0x017,
 650                 .cpu_id         = DAVINCI_CPU_ID_DM365,
 651                 .name           = "dm365_rev1.1",
 652         },
 653         {
 654                 .variant        = 0x8,
 655                 .part_no        = 0xb83e,
 656                 .manufacturer   = 0x017,
 657                 .cpu_id         = DAVINCI_CPU_ID_DM365,
 658                 .name           = "dm365_rev1.2",
 659         },
 660 };
 661
 662 /*
 663  * Bottom half of timer0 is used for clockevent, top half is used for
 664  * clocksource.
 665  */
 666 static const struct davinci_timer_cfg dm365_timer_cfg = {
 667         .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
 668         .irq = {
 669                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
 670                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
 671         },
 672 };
 673
 674 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
 675
 676 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
 677         {
 678                 .mapbase        = DAVINCI_UART0_BASE,
 679                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
 680                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 681                                   UPF_IOREMAP,
 682                 .iotype         = UPIO_MEM,
 683                 .regshift       = 2,
 684         },
 685         {
 686                 .flags  = 0,
 687         }
 688 };
 689 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
 690         {
 691                 .mapbase        = DM365_UART1_BASE,
 692                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
 693                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 694                                   UPF_IOREMAP,
 695                 .iotype         = UPIO_MEM,
 696                 .regshift       = 2,
 697         },
 698         {
 699                 .flags  = 0,
 700         }
 701 };
 702
 703 struct platform_device dm365_serial_device[] = {
 704         {
 705                 .name                   = "serial8250",
 706                 .id                     = PLAT8250_DEV_PLATFORM,
 707                 .dev                    = {
 708                         .platform_data  = dm365_serial0_platform_data,
 709                 }
 710         },
 711         {
 712                 .name                   = "serial8250",
 713                 .id                     = PLAT8250_DEV_PLATFORM1,
 714                 .dev                    = {
 715                         .platform_data  = dm365_serial1_platform_data,
 716                 }
 717         },
 718         {
 719         }
 720 };
 721
 722 static const struct davinci_soc_info davinci_soc_info_dm365 = {
 723         .io_desc                = dm365_io_desc,
 724         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
 725         .jtag_id_reg            = 0x01c40028,
 726         .ids                    = dm365_ids,
 727         .ids_num                = ARRAY_SIZE(dm365_ids),
 728         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 729         .pinmux_pins            = dm365_pins,
 730         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
 731         .emac_pdata             = &dm365_emac_pdata,
 732         .sram_dma               = 0x00010000,
 733         .sram_len               = SZ_32K,
 734 };
 735
 736 void __init dm365_init_asp(void)
 737 {
 738         davinci_cfg_reg(DM365_MCBSP0_BDX);
 739         davinci_cfg_reg(DM365_MCBSP0_X);
 740         davinci_cfg_reg(DM365_MCBSP0_BFSX);
 741         davinci_cfg_reg(DM365_MCBSP0_BDR);
 742         davinci_cfg_reg(DM365_MCBSP0_R);
 743         davinci_cfg_reg(DM365_MCBSP0_BFSR);
 744         davinci_cfg_reg(DM365_EVT2_ASP_TX);
 745         davinci_cfg_reg(DM365_EVT3_ASP_RX);
 746         platform_device_register(&dm365_asp_device);
 747 }
 748
 749 void __init dm365_init_vc(void)
 750 {
 751         davinci_cfg_reg(DM365_EVT2_VC_TX);
 752         davinci_cfg_reg(DM365_EVT3_VC_RX);
 753         platform_device_register(&dm365_vc_device);
 754 }
 755
 756 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
 757 {
 758         dm365_ks_device.dev.platform_data = pdata;
 759         platform_device_register(&dm365_ks_device);
 760 }
 761
 762 void __init dm365_init_rtc(void)
 763 {
 764         davinci_cfg_reg(DM365_INT_PRTCSS);
 765         platform_device_register(&dm365_rtc_device);
 766 }
 767
 768 void __init dm365_init(void)
 769 {
 770         davinci_common_init(&davinci_soc_info_dm365);
 771         davinci_map_sysmod();
 772 }
 773
 774 void __init dm365_init_time(void)
 775 {
 776         void __iomem *pll1, *pll2, *psc;
 777         struct clk *clk;
 778         int rv;
 779
 780         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
 781
 782         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 783         dm365_pll1_init(NULL, pll1, NULL);
 784
 785         pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
 786         dm365_pll2_init(NULL, pll2, NULL);
 787
 788         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 789         dm365_psc_init(NULL, psc);
 790
 791         clk = clk_get(NULL, "timer0");
 792         if (WARN_ON(IS_ERR(clk))) {
 793                 pr_err("Unable to get the timer clock\n");
 794                 return;
 795         }
 796
 797         rv = davinci_timer_register(clk, &dm365_timer_cfg);
 798         WARN(rv, "Unable to register the timer: %d\n", rv);
 799 }
 800
 801 void __init dm365_register_clocks(void)
 802 {
 803         /* all clocks are currently registered in dm365_init_time() */
 804 }
 805
 806 static struct resource dm365_vpss_resources[] = {
 807         {
 808                 /* VPSS ISP5 Base address */
 809                 .name           = "isp5",
 810                 .start          = 0x01c70000,
 811                 .end            = 0x01c70000 + 0xff,
 812                 .flags          = IORESOURCE_MEM,
 813         },
 814         {
 815                 /* VPSS CLK Base address */
 816                 .name           = "vpss",
 817                 .start          = 0x01c70200,
 818                 .end            = 0x01c70200 + 0xff,
 819                 .flags          = IORESOURCE_MEM,
 820         },
 821 };
 822
 823 static struct platform_device dm365_vpss_device = {
 824        .name                   = "vpss",
 825        .id                     = -1,
 826        .dev.platform_data      = "dm365_vpss",
 827        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
 828        .resource               = dm365_vpss_resources,
 829 };
 830
 831 static struct resource vpfe_resources[] = {
 832         {
 833                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 834                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 835                 .flags          = IORESOURCE_IRQ,
 836         },
 837         {
 838                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 839                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 840                 .flags          = IORESOURCE_IRQ,
 841         },
 842 };
 843
 844 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 845 static struct platform_device vpfe_capture_dev = {
 846         .name           = CAPTURE_DRV_NAME,
 847         .id             = -1,
 848         .num_resources  = ARRAY_SIZE(vpfe_resources),
 849         .resource       = vpfe_resources,
 850         .dev = {
 851                 .dma_mask               = &vpfe_capture_dma_mask,
 852                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 853         },
 854 };
 855
 856 static void dm365_isif_setup_pinmux(void)
 857 {
 858         davinci_cfg_reg(DM365_VIN_CAM_WEN);
 859         davinci_cfg_reg(DM365_VIN_CAM_VD);
 860         davinci_cfg_reg(DM365_VIN_CAM_HD);
 861         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
 862         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
 863 }
 864
 865 static struct resource isif_resource[] = {
 866         /* ISIF Base address */
 867         {
 868                 .start          = 0x01c71000,
 869                 .end            = 0x01c71000 + 0x1ff,
 870                 .flags          = IORESOURCE_MEM,
 871         },
 872         /* ISIF Linearization table 0 */
 873         {
 874                 .start          = 0x1C7C000,
 875                 .end            = 0x1C7C000 + 0x2ff,
 876                 .flags          = IORESOURCE_MEM,
 877         },
 878         /* ISIF Linearization table 1 */
 879         {
 880                 .start          = 0x1C7C400,
 881                 .end            = 0x1C7C400 + 0x2ff,
 882                 .flags          = IORESOURCE_MEM,
 883         },
 884 };
 885 static struct platform_device dm365_isif_dev = {
 886         .name           = "isif",
 887         .id             = -1,
 888         .num_resources  = ARRAY_SIZE(isif_resource),
 889         .resource       = isif_resource,
 890         .dev = {
 891                 .dma_mask               = &vpfe_capture_dma_mask,
 892                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 893                 .platform_data          = dm365_isif_setup_pinmux,
 894         },
 895 };
 896
 897 static struct resource dm365_osd_resources[] = {
 898         {
 899                 .start = DM365_OSD_BASE,
 900                 .end   = DM365_OSD_BASE + 0xff,
 901                 .flags = IORESOURCE_MEM,
 902         },
 903 };
 904
 905 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
 906
 907 static struct platform_device dm365_osd_dev = {
 908         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
 909         .id             = -1,
 910         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
 911         .resource       = dm365_osd_resources,
 912         .dev            = {
 913                 .dma_mask               = &dm365_video_dma_mask,
 914                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 915         },
 916 };
 917
 918 static struct resource dm365_venc_resources[] = {
 919         {
 920                 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 921                 .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 922                 .flags = IORESOURCE_IRQ,
 923         },
 924         /* venc registers io space */
 925         {
 926                 .start = DM365_VENC_BASE,
 927                 .end   = DM365_VENC_BASE + 0x177,
 928                 .flags = IORESOURCE_MEM,
 929         },
 930         /* vdaccfg registers io space */
 931         {
 932                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
 933                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
 934                 .flags = IORESOURCE_MEM,
 935         },
 936 };
 937
 938 static struct resource dm365_v4l2_disp_resources[] = {
 939         {
 940                 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 941                 .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 942                 .flags = IORESOURCE_IRQ,
 943         },
 944         /* venc registers io space */
 945         {
 946                 .start = DM365_VENC_BASE,
 947                 .end   = DM365_VENC_BASE + 0x177,
 948                 .flags = IORESOURCE_MEM,
 949         },
 950 };
 951
 952 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
 953 {
 954         switch (if_type) {
 955         case MEDIA_BUS_FMT_SGRBG8_1X8:
 956                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
 957                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
 958                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
 959                 break;
 960         case MEDIA_BUS_FMT_YUYV10_1X20:
 961                 if (field)
 962                         davinci_cfg_reg(DM365_VOUT_FIELD);
 963                 else
 964                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
 965                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
 966                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
 967                 break;
 968         default:
 969                 return -EINVAL;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
 976                                   unsigned int pclock)
 977 {
 978         void __iomem *vpss_clkctl_reg;
 979         u32 val;
 980
 981         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
 982
 983         switch (type) {
 984         case VPBE_ENC_STD:
 985                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
 986                 break;
 987         case VPBE_ENC_DV_TIMINGS:
 988                 if (pclock <= 27000000) {
 989                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
 990                 } else {
 991                         /* set sysclk4 to output 74.25 MHz from pll1 */
 992                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
 993                               VPSS_VENCCLKEN_ENABLE;
 994                 }
 995                 break;
 996         default:
 997                 return -EINVAL;
 998         }
 999         writel(val, vpss_clkctl_reg);
1000
1001         return 0;
1002 }
1003
1004 static struct platform_device dm365_vpbe_display = {
1005         .name           = "vpbe-v4l2",
1006         .id             = -1,
1007         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1008         .resource       = dm365_v4l2_disp_resources,
1009         .dev            = {
1010                 .dma_mask               = &dm365_video_dma_mask,
1011                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1012         },
1013 };
1014
1015 static struct venc_platform_data dm365_venc_pdata = {
1016         .setup_pinmux   = dm365_vpbe_setup_pinmux,
1017         .setup_clock    = dm365_venc_setup_clock,
1018 };
1019
1020 static struct platform_device dm365_venc_dev = {
1021         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
1022         .id             = -1,
1023         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1024         .resource       = dm365_venc_resources,
1025         .dev            = {
1026                 .dma_mask               = &dm365_video_dma_mask,
1027                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1028                 .platform_data          = (void *)&dm365_venc_pdata,
1029         },
1030 };
1031
1032 static struct platform_device dm365_vpbe_dev = {
1033         .name           = "vpbe_controller",
1034         .id             = -1,
1035         .dev            = {
1036                 .dma_mask               = &dm365_video_dma_mask,
1037                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1038         },
1039 };
1040
1041 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1042                                 struct vpbe_config *vpbe_cfg)
1043 {
1044         if (vpfe_cfg || vpbe_cfg)
1045                 platform_device_register(&dm365_vpss_device);
1046
1047         if (vpfe_cfg) {
1048                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1049                 platform_device_register(&dm365_isif_dev);
1050                 platform_device_register(&vpfe_capture_dev);
1051         }
1052         if (vpbe_cfg) {
1053                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1054                 platform_device_register(&dm365_osd_dev);
1055                 platform_device_register(&dm365_venc_dev);
1056                 platform_device_register(&dm365_vpbe_dev);
1057                 platform_device_register(&dm365_vpbe_display);
1058         }
1059
1060         return 0;
1061 }
1062
1063 static const struct davinci_aintc_config dm365_aintc_config = {
1064         .reg = {
1065                 .start          = DAVINCI_ARM_INTC_BASE,
1066                 .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1067                 .flags          = IORESOURCE_MEM,
1068         },
1069         .num_irqs               = 64,
1070         .prios                  = dm365_default_priorities,
1071 };
1072
1073 void __init dm365_init_irq(void)
1074 {
1075         davinci_aintc_init(&dm365_aintc_config);
1076 }
1077
1078 static int __init dm365_init_devices(void)
1079 {
1080         struct platform_device *edma_pdev;
1081         int ret = 0;
1082
1083         if (!cpu_is_davinci_dm365())
1084                 return 0;
1085
1086         davinci_cfg_reg(DM365_INT_EDMA_CC);
1087         edma_pdev = platform_device_register_full(&dm365_edma_device);
1088         if (IS_ERR(edma_pdev)) {
1089                 pr_warn("%s: Failed to register eDMA\n", __func__);
1090                 return PTR_ERR(edma_pdev);
1091         }
1092
1093         platform_device_register(&dm365_mdio_device);
1094         platform_device_register(&dm365_emac_device);
1095
1096         ret = davinci_init_wdt();
1097         if (ret)
1098                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1099
1100         return ret;
1101 }
1102 postcore_initcall(dm365_init_devices);