2 * TI DaVinci DM355 chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/init.h>
19 #include <linux/irqchip/irq-davinci-aintc.h>
20 #include <linux/platform_data/edma.h>
21 #include <linux/platform_data/gpio-davinci.h>
22 #include <linux/platform_data/spi-davinci.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_8250.h>
25 #include <linux/spi/spi.h>
27 #include <clocksource/timer-davinci.h>
29 #include <asm/mach/map.h>
39 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
40 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
41 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
44 * Device specific clocks
46 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
48 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
50 static struct resource dm355_spi0_resources[] = {
54 .flags = IORESOURCE_MEM,
57 .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
58 .flags = IORESOURCE_IRQ,
62 static struct davinci_spi_platform_data dm355_spi0_pdata = {
63 .version = SPI_VERSION_1,
66 .dma_event_q = EVENTQ_1,
69 static struct platform_device dm355_spi0_device = {
70 .name = "spi_davinci",
73 .dma_mask = &dm355_spi0_dma_mask,
74 .coherent_dma_mask = DMA_BIT_MASK(32),
75 .platform_data = &dm355_spi0_pdata,
77 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
78 .resource = dm355_spi0_resources,
81 void __init dm355_init_spi0(unsigned chipselect_mask,
82 const struct spi_board_info *info, unsigned len)
84 /* for now, assume we need MISO */
85 davinci_cfg_reg(DM355_SPI0_SDI);
87 /* not all slaves will be wired up */
88 if (chipselect_mask & BIT(0))
89 davinci_cfg_reg(DM355_SPI0_SDENA0);
90 if (chipselect_mask & BIT(1))
91 davinci_cfg_reg(DM355_SPI0_SDENA1);
93 spi_register_board_info(info, len);
95 platform_device_register(&dm355_spi0_device);
98 /*----------------------------------------------------------------------*/
104 * Device specific mux setup
106 * soc description mux mode mode mux dbg
107 * reg offset mask mode
109 static const struct mux_config dm355_pins[] = {
110 #ifdef CONFIG_DAVINCI_MUX
111 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
113 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
114 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
115 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
116 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
117 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
118 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
120 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
121 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
123 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
124 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
125 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
126 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
127 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
128 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
130 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
131 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
132 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
134 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
135 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
136 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
138 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
139 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
140 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
142 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
143 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
144 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
145 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
146 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
148 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
149 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
150 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
151 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
152 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
153 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
154 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
158 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
159 [IRQ_DM355_CCDC_VDINT0] = 2,
160 [IRQ_DM355_CCDC_VDINT1] = 6,
161 [IRQ_DM355_CCDC_VDINT2] = 6,
162 [IRQ_DM355_IPIPE_HST] = 6,
163 [IRQ_DM355_H3AINT] = 6,
164 [IRQ_DM355_IPIPE_SDR] = 6,
165 [IRQ_DM355_IPIPEIFINT] = 6,
166 [IRQ_DM355_OSDINT] = 7,
167 [IRQ_DM355_VENCINT] = 6,
171 [IRQ_DM355_RTOINT] = 4,
172 [IRQ_DM355_UARTINT2] = 7,
173 [IRQ_DM355_TINT6] = 7,
174 [IRQ_CCINT0] = 5, /* dma */
175 [IRQ_CCERRINT] = 5, /* dma */
176 [IRQ_TCERRINT0] = 5, /* dma */
177 [IRQ_TCERRINT] = 5, /* dma */
178 [IRQ_DM355_SPINT2_1] = 7,
179 [IRQ_DM355_TINT7] = 4,
180 [IRQ_DM355_SDIOINT0] = 7,
184 [IRQ_DM355_MMCINT1] = 7,
185 [IRQ_DM355_PWMINT3] = 7,
188 [IRQ_DM355_SDIOINT1] = 4,
189 [IRQ_TINT0_TINT12] = 2, /* clockevent */
190 [IRQ_TINT0_TINT34] = 2, /* clocksource */
191 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
192 [IRQ_TINT1_TINT34] = 7, /* system tick */
199 [IRQ_DM355_SPINT0_0] = 3,
200 [IRQ_DM355_SPINT0_1] = 3,
201 [IRQ_DM355_GPIO0] = 3,
202 [IRQ_DM355_GPIO1] = 7,
203 [IRQ_DM355_GPIO2] = 4,
204 [IRQ_DM355_GPIO3] = 4,
205 [IRQ_DM355_GPIO4] = 7,
206 [IRQ_DM355_GPIO5] = 7,
207 [IRQ_DM355_GPIO6] = 7,
208 [IRQ_DM355_GPIO7] = 7,
209 [IRQ_DM355_GPIO8] = 7,
210 [IRQ_DM355_GPIO9] = 7,
211 [IRQ_DM355_GPIOBNK0] = 7,
212 [IRQ_DM355_GPIOBNK1] = 7,
213 [IRQ_DM355_GPIOBNK2] = 7,
214 [IRQ_DM355_GPIOBNK3] = 7,
215 [IRQ_DM355_GPIOBNK4] = 7,
216 [IRQ_DM355_GPIOBNK5] = 7,
217 [IRQ_DM355_GPIOBNK6] = 7,
223 /*----------------------------------------------------------------------*/
225 static s8 queue_priority_mapping[][2] = {
226 /* {event queue no, Priority} */
232 static const struct dma_slave_map dm355_edma_map[] = {
233 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
234 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
235 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
236 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
237 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
238 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
239 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
240 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
241 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
242 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
243 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
244 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
245 { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
246 { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
249 static struct edma_soc_info dm355_edma_pdata = {
250 .queue_priority_mapping = queue_priority_mapping,
251 .default_queue = EVENTQ_1,
252 .slave_map = dm355_edma_map,
253 .slavecnt = ARRAY_SIZE(dm355_edma_map),
256 static struct resource edma_resources[] = {
260 .end = 0x01c00000 + SZ_64K - 1,
261 .flags = IORESOURCE_MEM,
266 .end = 0x01c10000 + SZ_1K - 1,
267 .flags = IORESOURCE_MEM,
272 .end = 0x01c10400 + SZ_1K - 1,
273 .flags = IORESOURCE_MEM,
276 .name = "edma3_ccint",
277 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
278 .flags = IORESOURCE_IRQ,
281 .name = "edma3_ccerrint",
282 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
283 .flags = IORESOURCE_IRQ,
285 /* not using (or muxing) TC*_ERR */
288 static const struct platform_device_info dm355_edma_device __initconst = {
291 .dma_mask = DMA_BIT_MASK(32),
292 .res = edma_resources,
293 .num_res = ARRAY_SIZE(edma_resources),
294 .data = &dm355_edma_pdata,
295 .size_data = sizeof(dm355_edma_pdata),
298 static struct resource dm355_asp1_resources[] = {
301 .start = DAVINCI_ASP1_BASE,
302 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
303 .flags = IORESOURCE_MEM,
306 .start = DAVINCI_DMA_ASP1_TX,
307 .end = DAVINCI_DMA_ASP1_TX,
308 .flags = IORESOURCE_DMA,
311 .start = DAVINCI_DMA_ASP1_RX,
312 .end = DAVINCI_DMA_ASP1_RX,
313 .flags = IORESOURCE_DMA,
317 static struct platform_device dm355_asp1_device = {
318 .name = "davinci-mcbsp",
320 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
321 .resource = dm355_asp1_resources,
324 static void dm355_ccdc_setup_pinmux(void)
326 davinci_cfg_reg(DM355_VIN_PCLK);
327 davinci_cfg_reg(DM355_VIN_CAM_WEN);
328 davinci_cfg_reg(DM355_VIN_CAM_VD);
329 davinci_cfg_reg(DM355_VIN_CAM_HD);
330 davinci_cfg_reg(DM355_VIN_YIN_EN);
331 davinci_cfg_reg(DM355_VIN_CINL_EN);
332 davinci_cfg_reg(DM355_VIN_CINH_EN);
335 static struct resource dm355_vpss_resources[] = {
337 /* VPSS BL Base address */
340 .end = 0x01c70800 + 0xff,
341 .flags = IORESOURCE_MEM,
344 /* VPSS CLK Base address */
347 .end = 0x01c70000 + 0xf,
348 .flags = IORESOURCE_MEM,
352 static struct platform_device dm355_vpss_device = {
355 .dev.platform_data = "dm355_vpss",
356 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
357 .resource = dm355_vpss_resources,
360 static struct resource vpfe_resources[] = {
362 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
363 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
364 .flags = IORESOURCE_IRQ,
367 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
368 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
369 .flags = IORESOURCE_IRQ,
373 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
374 static struct resource dm355_ccdc_resource[] = {
375 /* CCDC Base address */
377 .flags = IORESOURCE_MEM,
379 .end = 0x01c70600 + 0x1ff,
382 static struct platform_device dm355_ccdc_dev = {
383 .name = "dm355_ccdc",
385 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
386 .resource = dm355_ccdc_resource,
388 .dma_mask = &vpfe_capture_dma_mask,
389 .coherent_dma_mask = DMA_BIT_MASK(32),
390 .platform_data = dm355_ccdc_setup_pinmux,
394 static struct platform_device vpfe_capture_dev = {
395 .name = CAPTURE_DRV_NAME,
397 .num_resources = ARRAY_SIZE(vpfe_resources),
398 .resource = vpfe_resources,
400 .dma_mask = &vpfe_capture_dma_mask,
401 .coherent_dma_mask = DMA_BIT_MASK(32),
405 static struct resource dm355_osd_resources[] = {
407 .start = DM355_OSD_BASE,
408 .end = DM355_OSD_BASE + 0x17f,
409 .flags = IORESOURCE_MEM,
413 static struct platform_device dm355_osd_dev = {
414 .name = DM355_VPBE_OSD_SUBDEV_NAME,
416 .num_resources = ARRAY_SIZE(dm355_osd_resources),
417 .resource = dm355_osd_resources,
419 .dma_mask = &vpfe_capture_dma_mask,
420 .coherent_dma_mask = DMA_BIT_MASK(32),
424 static struct resource dm355_venc_resources[] = {
426 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
427 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
428 .flags = IORESOURCE_IRQ,
430 /* venc registers io space */
432 .start = DM355_VENC_BASE,
433 .end = DM355_VENC_BASE + 0x17f,
434 .flags = IORESOURCE_MEM,
436 /* VDAC config register io space */
438 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
439 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
440 .flags = IORESOURCE_MEM,
444 static struct resource dm355_v4l2_disp_resources[] = {
446 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
447 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
448 .flags = IORESOURCE_IRQ,
450 /* venc registers io space */
452 .start = DM355_VENC_BASE,
453 .end = DM355_VENC_BASE + 0x17f,
454 .flags = IORESOURCE_MEM,
458 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
461 case MEDIA_BUS_FMT_SGRBG8_1X8:
462 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
464 case MEDIA_BUS_FMT_YUYV10_1X20:
466 davinci_cfg_reg(DM355_VOUT_FIELD);
468 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
474 davinci_cfg_reg(DM355_VOUT_COUTL_EN);
475 davinci_cfg_reg(DM355_VOUT_COUTH_EN);
480 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
483 void __iomem *vpss_clk_ctrl_reg;
485 vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
489 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
492 case VPBE_ENC_DV_TIMINGS:
493 if (pclock > 27000000)
495 * For HD, use external clock source since we cannot
496 * support HD mode with internal clocks.
498 writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
507 static struct platform_device dm355_vpbe_display = {
510 .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
511 .resource = dm355_v4l2_disp_resources,
513 .dma_mask = &vpfe_capture_dma_mask,
514 .coherent_dma_mask = DMA_BIT_MASK(32),
518 static struct venc_platform_data dm355_venc_pdata = {
519 .setup_pinmux = dm355_vpbe_setup_pinmux,
520 .setup_clock = dm355_venc_setup_clock,
523 static struct platform_device dm355_venc_dev = {
524 .name = DM355_VPBE_VENC_SUBDEV_NAME,
526 .num_resources = ARRAY_SIZE(dm355_venc_resources),
527 .resource = dm355_venc_resources,
529 .dma_mask = &vpfe_capture_dma_mask,
530 .coherent_dma_mask = DMA_BIT_MASK(32),
531 .platform_data = (void *)&dm355_venc_pdata,
535 static struct platform_device dm355_vpbe_dev = {
536 .name = "vpbe_controller",
539 .dma_mask = &vpfe_capture_dma_mask,
540 .coherent_dma_mask = DMA_BIT_MASK(32),
544 static struct resource dm355_gpio_resources[] = {
546 .start = DAVINCI_GPIO_BASE,
547 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
548 .flags = IORESOURCE_MEM,
551 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
552 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
553 .flags = IORESOURCE_IRQ,
556 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
557 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
558 .flags = IORESOURCE_IRQ,
561 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
562 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
563 .flags = IORESOURCE_IRQ,
566 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
567 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
568 .flags = IORESOURCE_IRQ,
571 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
572 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
573 .flags = IORESOURCE_IRQ,
576 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
577 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
578 .flags = IORESOURCE_IRQ,
581 .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
582 .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
583 .flags = IORESOURCE_IRQ,
587 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
588 .no_auto_base = true,
593 int __init dm355_gpio_register(void)
595 return davinci_gpio_register(dm355_gpio_resources,
596 ARRAY_SIZE(dm355_gpio_resources),
597 &dm355_gpio_platform_data);
599 /*----------------------------------------------------------------------*/
601 static struct map_desc dm355_io_desc[] = {
604 .pfn = __phys_to_pfn(IO_PHYS),
610 /* Contents of JTAG ID register used to identify exact cpu type */
611 static struct davinci_id dm355_ids[] = {
615 .manufacturer = 0x00f,
616 .cpu_id = DAVINCI_CPU_ID_DM355,
622 * Bottom half of timer0 is used for clockevent, top half is used for
625 static const struct davinci_timer_cfg dm355_timer_cfg = {
626 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
628 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
629 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
633 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
635 .mapbase = DAVINCI_UART0_BASE,
636 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
637 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
646 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
648 .mapbase = DAVINCI_UART1_BASE,
649 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
650 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
659 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
661 .mapbase = DM355_UART2_BASE,
662 .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
663 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
673 struct platform_device dm355_serial_device[] = {
675 .name = "serial8250",
676 .id = PLAT8250_DEV_PLATFORM,
678 .platform_data = dm355_serial0_platform_data,
682 .name = "serial8250",
683 .id = PLAT8250_DEV_PLATFORM1,
685 .platform_data = dm355_serial1_platform_data,
689 .name = "serial8250",
690 .id = PLAT8250_DEV_PLATFORM2,
692 .platform_data = dm355_serial2_platform_data,
699 static const struct davinci_soc_info davinci_soc_info_dm355 = {
700 .io_desc = dm355_io_desc,
701 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
702 .jtag_id_reg = 0x01c40028,
704 .ids_num = ARRAY_SIZE(dm355_ids),
705 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
706 .pinmux_pins = dm355_pins,
707 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
708 .sram_dma = 0x00010000,
712 void __init dm355_init_asp1(u32 evt_enable)
714 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
715 if (evt_enable & ASP1_TX_EVT_EN)
716 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
718 if (evt_enable & ASP1_RX_EVT_EN)
719 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
721 platform_device_register(&dm355_asp1_device);
724 void __init dm355_init(void)
726 davinci_common_init(&davinci_soc_info_dm355);
727 davinci_map_sysmod();
730 void __init dm355_init_time(void)
732 void __iomem *pll1, *psc;
736 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
738 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
739 dm355_pll1_init(NULL, pll1, NULL);
741 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
742 dm355_psc_init(NULL, psc);
744 clk = clk_get(NULL, "timer0");
745 if (WARN_ON(IS_ERR(clk))) {
746 pr_err("Unable to get the timer clock\n");
750 rv = davinci_timer_register(clk, &dm355_timer_cfg);
751 WARN(rv, "Unable to register the timer: %d\n", rv);
754 static struct resource dm355_pll2_resources[] = {
756 .start = DAVINCI_PLL2_BASE,
757 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
758 .flags = IORESOURCE_MEM,
762 static struct platform_device dm355_pll2_device = {
763 .name = "dm355-pll2",
765 .resource = dm355_pll2_resources,
766 .num_resources = ARRAY_SIZE(dm355_pll2_resources),
769 void __init dm355_register_clocks(void)
771 /* PLL1 and PSC are registered in dm355_init_time() */
772 platform_device_register(&dm355_pll2_device);
775 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
776 struct vpbe_config *vpbe_cfg)
778 if (vpfe_cfg || vpbe_cfg)
779 platform_device_register(&dm355_vpss_device);
782 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
783 platform_device_register(&dm355_ccdc_dev);
784 platform_device_register(&vpfe_capture_dev);
788 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
789 platform_device_register(&dm355_osd_dev);
790 platform_device_register(&dm355_venc_dev);
791 platform_device_register(&dm355_vpbe_dev);
792 platform_device_register(&dm355_vpbe_display);
798 static const struct davinci_aintc_config dm355_aintc_config = {
800 .start = DAVINCI_ARM_INTC_BASE,
801 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
802 .flags = IORESOURCE_MEM,
805 .prios = dm355_default_priorities,
808 void __init dm355_init_irq(void)
810 davinci_aintc_init(&dm355_aintc_config);
813 static int __init dm355_init_devices(void)
815 struct platform_device *edma_pdev;
818 if (!cpu_is_davinci_dm355())
821 davinci_cfg_reg(DM355_INT_EDMA_CC);
822 edma_pdev = platform_device_register_full(&dm355_edma_device);
823 if (IS_ERR(edma_pdev)) {
824 pr_warn("%s: Failed to register eDMA\n", __func__);
825 return PTR_ERR(edma_pdev);
828 ret = davinci_init_wdt();
830 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
834 postcore_initcall(dm355_init_devices);