arch/arm/mach-davinci/dm355.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * TI DaVinci DM355 chip specific setup
   4  *
   5  * Author: Kevin Hilman, Deep Root Systems, LLC
   6  *
   7  * 2007 (c) Deep Root Systems, LLC.
   8  */
   9
  10 #include <linux/clk-provider.h>
  11 #include <linux/clk/davinci.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/irqchip/irq-davinci-aintc.h>
  18 #include <linux/platform_data/edma.h>
  19 #include <linux/platform_data/gpio-davinci.h>
  20 #include <linux/platform_data/spi-davinci.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/serial_8250.h>
  23 #include <linux/spi/spi.h>
  24
  25 #include <clocksource/timer-davinci.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include "common.h"
  30 #include "cputype.h"
  31 #include "serial.h"
  32 #include "asp.h"
  33 #include "davinci.h"
  34 #include "irqs.h"
  35 #include "mux.h"
  36
  37 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  38 #define DM355_OSD_BASE          (IO_PHYS + 0x70200)
  39 #define DM355_VENC_BASE         (IO_PHYS + 0x70400)
  40
  41 /*
  42  * Device specific clocks
  43  */
  44 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  45
  46 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
  47
  48 static struct resource dm355_spi0_resources[] = {
  49         {
  50                 .start = 0x01c66000,
  51                 .end   = 0x01c667ff,
  52                 .flags = IORESOURCE_MEM,
  53         },
  54         {
  55                 .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
  56                 .flags = IORESOURCE_IRQ,
  57         },
  58 };
  59
  60 static struct davinci_spi_platform_data dm355_spi0_pdata = {
  61         .version        = SPI_VERSION_1,
  62         .num_chipselect = 2,
  63         .cshold_bug     = true,
  64         .dma_event_q    = EVENTQ_1,
  65         .prescaler_limit = 1,
  66 };
  67 static struct platform_device dm355_spi0_device = {
  68         .name = "spi_davinci",
  69         .id = 0,
  70         .dev = {
  71                 .dma_mask = &dm355_spi0_dma_mask,
  72                 .coherent_dma_mask = DMA_BIT_MASK(32),
  73                 .platform_data = &dm355_spi0_pdata,
  74         },
  75         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
  76         .resource = dm355_spi0_resources,
  77 };
  78
  79 void __init dm355_init_spi0(unsigned chipselect_mask,
  80                 const struct spi_board_info *info, unsigned len)
  81 {
  82         /* for now, assume we need MISO */
  83         davinci_cfg_reg(DM355_SPI0_SDI);
  84
  85         /* not all slaves will be wired up */
  86         if (chipselect_mask & BIT(0))
  87                 davinci_cfg_reg(DM355_SPI0_SDENA0);
  88         if (chipselect_mask & BIT(1))
  89                 davinci_cfg_reg(DM355_SPI0_SDENA1);
  90
  91         spi_register_board_info(info, len);
  92
  93         platform_device_register(&dm355_spi0_device);
  94 }
  95
  96 /*----------------------------------------------------------------------*/
  97
  98 #define INTMUX          0x18
  99 #define EVTMUX          0x1c
 100
 101 /*
 102  * Device specific mux setup
 103  *
 104  *      soc     description     mux  mode   mode  mux    dbg
 105  *                              reg  offset mask  mode
 106  */
 107 static const struct mux_config dm355_pins[] = {
 108 #ifdef CONFIG_DAVINCI_MUX
 109 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 110
 111 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 112 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 113 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 114 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 115 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 116 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 117
 118 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 119 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 120
 121 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 122 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 123 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 124 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 125 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 126 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 127
 128 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 129 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 130 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 131
 132 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 133 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 134 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 135
 136 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 137 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 138 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 139
 140 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 141 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 142 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 143 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 144 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 145
 146 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 147 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 148 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 149 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 150 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 151 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 152 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 153 #endif
 154 };
 155
 156 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 157         [IRQ_DM355_CCDC_VDINT0]         = 2,
 158         [IRQ_DM355_CCDC_VDINT1]         = 6,
 159         [IRQ_DM355_CCDC_VDINT2]         = 6,
 160         [IRQ_DM355_IPIPE_HST]           = 6,
 161         [IRQ_DM355_H3AINT]              = 6,
 162         [IRQ_DM355_IPIPE_SDR]           = 6,
 163         [IRQ_DM355_IPIPEIFINT]          = 6,
 164         [IRQ_DM355_OSDINT]              = 7,
 165         [IRQ_DM355_VENCINT]             = 6,
 166         [IRQ_ASQINT]                    = 6,
 167         [IRQ_IMXINT]                    = 6,
 168         [IRQ_USBINT]                    = 4,
 169         [IRQ_DM355_RTOINT]              = 4,
 170         [IRQ_DM355_UARTINT2]            = 7,
 171         [IRQ_DM355_TINT6]               = 7,
 172         [IRQ_CCINT0]                    = 5,    /* dma */
 173         [IRQ_CCERRINT]                  = 5,    /* dma */
 174         [IRQ_TCERRINT0]                 = 5,    /* dma */
 175         [IRQ_TCERRINT]                  = 5,    /* dma */
 176         [IRQ_DM355_SPINT2_1]            = 7,
 177         [IRQ_DM355_TINT7]               = 4,
 178         [IRQ_DM355_SDIOINT0]            = 7,
 179         [IRQ_MBXINT]                    = 7,
 180         [IRQ_MBRINT]                    = 7,
 181         [IRQ_MMCINT]                    = 7,
 182         [IRQ_DM355_MMCINT1]             = 7,
 183         [IRQ_DM355_PWMINT3]             = 7,
 184         [IRQ_DDRINT]                    = 7,
 185         [IRQ_AEMIFINT]                  = 7,
 186         [IRQ_DM355_SDIOINT1]            = 4,
 187         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 188         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 189         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 190         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 191         [IRQ_PWMINT0]                   = 7,
 192         [IRQ_PWMINT1]                   = 7,
 193         [IRQ_PWMINT2]                   = 7,
 194         [IRQ_I2C]                       = 3,
 195         [IRQ_UARTINT0]                  = 3,
 196         [IRQ_UARTINT1]                  = 3,
 197         [IRQ_DM355_SPINT0_0]            = 3,
 198         [IRQ_DM355_SPINT0_1]            = 3,
 199         [IRQ_DM355_GPIO0]               = 3,
 200         [IRQ_DM355_GPIO1]               = 7,
 201         [IRQ_DM355_GPIO2]               = 4,
 202         [IRQ_DM355_GPIO3]               = 4,
 203         [IRQ_DM355_GPIO4]               = 7,
 204         [IRQ_DM355_GPIO5]               = 7,
 205         [IRQ_DM355_GPIO6]               = 7,
 206         [IRQ_DM355_GPIO7]               = 7,
 207         [IRQ_DM355_GPIO8]               = 7,
 208         [IRQ_DM355_GPIO9]               = 7,
 209         [IRQ_DM355_GPIOBNK0]            = 7,
 210         [IRQ_DM355_GPIOBNK1]            = 7,
 211         [IRQ_DM355_GPIOBNK2]            = 7,
 212         [IRQ_DM355_GPIOBNK3]            = 7,
 213         [IRQ_DM355_GPIOBNK4]            = 7,
 214         [IRQ_DM355_GPIOBNK5]            = 7,
 215         [IRQ_DM355_GPIOBNK6]            = 7,
 216         [IRQ_COMMTX]                    = 7,
 217         [IRQ_COMMRX]                    = 7,
 218         [IRQ_EMUINT]                    = 7,
 219 };
 220
 221 /*----------------------------------------------------------------------*/
 222
 223 static s8 queue_priority_mapping[][2] = {
 224         /* {event queue no, Priority} */
 225         {0, 3},
 226         {1, 7},
 227         {-1, -1},
 228 };
 229
 230 static const struct dma_slave_map dm355_edma_map[] = {
 231         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
 232         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
 233         { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
 234         { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
 235         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
 236         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
 237         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
 238         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
 239         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
 240         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
 241         { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
 242         { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
 243         { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
 244         { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
 245 };
 246
 247 static struct edma_soc_info dm355_edma_pdata = {
 248         .queue_priority_mapping = queue_priority_mapping,
 249         .default_queue          = EVENTQ_1,
 250         .slave_map              = dm355_edma_map,
 251         .slavecnt               = ARRAY_SIZE(dm355_edma_map),
 252 };
 253
 254 static struct resource edma_resources[] = {
 255         {
 256                 .name   = "edma3_cc",
 257                 .start  = 0x01c00000,
 258                 .end    = 0x01c00000 + SZ_64K - 1,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         {
 262                 .name   = "edma3_tc0",
 263                 .start  = 0x01c10000,
 264                 .end    = 0x01c10000 + SZ_1K - 1,
 265                 .flags  = IORESOURCE_MEM,
 266         },
 267         {
 268                 .name   = "edma3_tc1",
 269                 .start  = 0x01c10400,
 270                 .end    = 0x01c10400 + SZ_1K - 1,
 271                 .flags  = IORESOURCE_MEM,
 272         },
 273         {
 274                 .name   = "edma3_ccint",
 275                 .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
 276                 .flags  = IORESOURCE_IRQ,
 277         },
 278         {
 279                 .name   = "edma3_ccerrint",
 280                 .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
 281                 .flags  = IORESOURCE_IRQ,
 282         },
 283         /* not using (or muxing) TC*_ERR */
 284 };
 285
 286 static const struct platform_device_info dm355_edma_device __initconst = {
 287         .name           = "edma",
 288         .id             = 0,
 289         .dma_mask       = DMA_BIT_MASK(32),
 290         .res            = edma_resources,
 291         .num_res        = ARRAY_SIZE(edma_resources),
 292         .data           = &dm355_edma_pdata,
 293         .size_data      = sizeof(dm355_edma_pdata),
 294 };
 295
 296 static struct resource dm355_asp1_resources[] = {
 297         {
 298                 .name   = "mpu",
 299                 .start  = DAVINCI_ASP1_BASE,
 300                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 301                 .flags  = IORESOURCE_MEM,
 302         },
 303         {
 304                 .start  = DAVINCI_DMA_ASP1_TX,
 305                 .end    = DAVINCI_DMA_ASP1_TX,
 306                 .flags  = IORESOURCE_DMA,
 307         },
 308         {
 309                 .start  = DAVINCI_DMA_ASP1_RX,
 310                 .end    = DAVINCI_DMA_ASP1_RX,
 311                 .flags  = IORESOURCE_DMA,
 312         },
 313 };
 314
 315 static struct platform_device dm355_asp1_device = {
 316         .name           = "davinci-mcbsp",
 317         .id             = 1,
 318         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 319         .resource       = dm355_asp1_resources,
 320 };
 321
 322 static void dm355_ccdc_setup_pinmux(void)
 323 {
 324         davinci_cfg_reg(DM355_VIN_PCLK);
 325         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 326         davinci_cfg_reg(DM355_VIN_CAM_VD);
 327         davinci_cfg_reg(DM355_VIN_CAM_HD);
 328         davinci_cfg_reg(DM355_VIN_YIN_EN);
 329         davinci_cfg_reg(DM355_VIN_CINL_EN);
 330         davinci_cfg_reg(DM355_VIN_CINH_EN);
 331 }
 332
 333 static struct resource dm355_vpss_resources[] = {
 334         {
 335                 /* VPSS BL Base address */
 336                 .name           = "vpss",
 337                 .start          = 0x01c70800,
 338                 .end            = 0x01c70800 + 0xff,
 339                 .flags          = IORESOURCE_MEM,
 340         },
 341         {
 342                 /* VPSS CLK Base address */
 343                 .name           = "vpss",
 344                 .start          = 0x01c70000,
 345                 .end            = 0x01c70000 + 0xf,
 346                 .flags          = IORESOURCE_MEM,
 347         },
 348 };
 349
 350 static struct platform_device dm355_vpss_device = {
 351         .name                   = "vpss",
 352         .id                     = -1,
 353         .dev.platform_data      = "dm355_vpss",
 354         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 355         .resource               = dm355_vpss_resources,
 356 };
 357
 358 static struct resource vpfe_resources[] = {
 359         {
 360                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 361                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 362                 .flags          = IORESOURCE_IRQ,
 363         },
 364         {
 365                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 366                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 367                 .flags          = IORESOURCE_IRQ,
 368         },
 369 };
 370
 371 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 372 static struct resource dm355_ccdc_resource[] = {
 373         /* CCDC Base address */
 374         {
 375                 .flags          = IORESOURCE_MEM,
 376                 .start          = 0x01c70600,
 377                 .end            = 0x01c70600 + 0x1ff,
 378         },
 379 };
 380 static struct platform_device dm355_ccdc_dev = {
 381         .name           = "dm355_ccdc",
 382         .id             = -1,
 383         .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
 384         .resource       = dm355_ccdc_resource,
 385         .dev = {
 386                 .dma_mask               = &vpfe_capture_dma_mask,
 387                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 388                 .platform_data          = dm355_ccdc_setup_pinmux,
 389         },
 390 };
 391
 392 static struct platform_device vpfe_capture_dev = {
 393         .name           = CAPTURE_DRV_NAME,
 394         .id             = -1,
 395         .num_resources  = ARRAY_SIZE(vpfe_resources),
 396         .resource       = vpfe_resources,
 397         .dev = {
 398                 .dma_mask               = &vpfe_capture_dma_mask,
 399                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 400         },
 401 };
 402
 403 static struct resource dm355_osd_resources[] = {
 404         {
 405                 .start  = DM355_OSD_BASE,
 406                 .end    = DM355_OSD_BASE + 0x17f,
 407                 .flags  = IORESOURCE_MEM,
 408         },
 409 };
 410
 411 static struct platform_device dm355_osd_dev = {
 412         .name           = DM355_VPBE_OSD_SUBDEV_NAME,
 413         .id             = -1,
 414         .num_resources  = ARRAY_SIZE(dm355_osd_resources),
 415         .resource       = dm355_osd_resources,
 416         .dev            = {
 417                 .dma_mask               = &vpfe_capture_dma_mask,
 418                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 419         },
 420 };
 421
 422 static struct resource dm355_venc_resources[] = {
 423         {
 424                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 425                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 426                 .flags  = IORESOURCE_IRQ,
 427         },
 428         /* venc registers io space */
 429         {
 430                 .start  = DM355_VENC_BASE,
 431                 .end    = DM355_VENC_BASE + 0x17f,
 432                 .flags  = IORESOURCE_MEM,
 433         },
 434         /* VDAC config register io space */
 435         {
 436                 .start  = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
 437                 .end    = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
 438                 .flags  = IORESOURCE_MEM,
 439         },
 440 };
 441
 442 static struct resource dm355_v4l2_disp_resources[] = {
 443         {
 444                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 445                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448         /* venc registers io space */
 449         {
 450                 .start  = DM355_VENC_BASE,
 451                 .end    = DM355_VENC_BASE + 0x17f,
 452                 .flags  = IORESOURCE_MEM,
 453         },
 454 };
 455
 456 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
 457 {
 458         switch (if_type) {
 459         case MEDIA_BUS_FMT_SGRBG8_1X8:
 460                 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 461                 break;
 462         case MEDIA_BUS_FMT_YUYV10_1X20:
 463                 if (field)
 464                         davinci_cfg_reg(DM355_VOUT_FIELD);
 465                 else
 466                         davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 467                 break;
 468         default:
 469                 return -EINVAL;
 470         }
 471
 472         davinci_cfg_reg(DM355_VOUT_COUTL_EN);
 473         davinci_cfg_reg(DM355_VOUT_COUTH_EN);
 474
 475         return 0;
 476 }
 477
 478 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
 479                                    unsigned int pclock)
 480 {
 481         void __iomem *vpss_clk_ctrl_reg;
 482
 483         vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
 484
 485         switch (type) {
 486         case VPBE_ENC_STD:
 487                 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
 488                        vpss_clk_ctrl_reg);
 489                 break;
 490         case VPBE_ENC_DV_TIMINGS:
 491                 if (pclock > 27000000)
 492                         /*
 493                          * For HD, use external clock source since we cannot
 494                          * support HD mode with internal clocks.
 495                          */
 496                         writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
 497                 break;
 498         default:
 499                 return -EINVAL;
 500         }
 501
 502         return 0;
 503 }
 504
 505 static struct platform_device dm355_vpbe_display = {
 506         .name           = "vpbe-v4l2",
 507         .id             = -1,
 508         .num_resources  = ARRAY_SIZE(dm355_v4l2_disp_resources),
 509         .resource       = dm355_v4l2_disp_resources,
 510         .dev            = {
 511                 .dma_mask               = &vpfe_capture_dma_mask,
 512                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 513         },
 514 };
 515
 516 static struct venc_platform_data dm355_venc_pdata = {
 517         .setup_pinmux   = dm355_vpbe_setup_pinmux,
 518         .setup_clock    = dm355_venc_setup_clock,
 519 };
 520
 521 static struct platform_device dm355_venc_dev = {
 522         .name           = DM355_VPBE_VENC_SUBDEV_NAME,
 523         .id             = -1,
 524         .num_resources  = ARRAY_SIZE(dm355_venc_resources),
 525         .resource       = dm355_venc_resources,
 526         .dev            = {
 527                 .dma_mask               = &vpfe_capture_dma_mask,
 528                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 529                 .platform_data          = (void *)&dm355_venc_pdata,
 530         },
 531 };
 532
 533 static struct platform_device dm355_vpbe_dev = {
 534         .name           = "vpbe_controller",
 535         .id             = -1,
 536         .dev            = {
 537                 .dma_mask               = &vpfe_capture_dma_mask,
 538                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 539         },
 540 };
 541
 542 static struct resource dm355_gpio_resources[] = {
 543         {       /* registers */
 544                 .start  = DAVINCI_GPIO_BASE,
 545                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 546                 .flags  = IORESOURCE_MEM,
 547         },
 548         {       /* interrupt */
 549                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
 550                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
 551                 .flags  = IORESOURCE_IRQ,
 552         },
 553         {
 554                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
 555                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
 556                 .flags  = IORESOURCE_IRQ,
 557         },
 558         {
 559                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
 560                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
 561                 .flags  = IORESOURCE_IRQ,
 562         },
 563         {
 564                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
 565                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
 566                 .flags  = IORESOURCE_IRQ,
 567         },
 568         {
 569                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
 570                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
 571                 .flags  = IORESOURCE_IRQ,
 572         },
 573         {
 574                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
 575                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
 576                 .flags  = IORESOURCE_IRQ,
 577         },
 578         {
 579                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
 580                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
 581                 .flags  = IORESOURCE_IRQ,
 582         },
 583 };
 584
 585 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
 586         .no_auto_base   = true,
 587         .base           = 0,
 588         .ngpio          = 104,
 589 };
 590
 591 int __init dm355_gpio_register(void)
 592 {
 593         return davinci_gpio_register(dm355_gpio_resources,
 594                                      ARRAY_SIZE(dm355_gpio_resources),
 595                                      &dm355_gpio_platform_data);
 596 }
 597 /*----------------------------------------------------------------------*/
 598
 599 static struct map_desc dm355_io_desc[] = {
 600         {
 601                 .virtual        = IO_VIRT,
 602                 .pfn            = __phys_to_pfn(IO_PHYS),
 603                 .length         = IO_SIZE,
 604                 .type           = MT_DEVICE
 605         },
 606 };
 607
 608 /* Contents of JTAG ID register used to identify exact cpu type */
 609 static struct davinci_id dm355_ids[] = {
 610         {
 611                 .variant        = 0x0,
 612                 .part_no        = 0xb73b,
 613                 .manufacturer   = 0x00f,
 614                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 615                 .name           = "dm355",
 616         },
 617 };
 618
 619 /*
 620  * Bottom half of timer0 is used for clockevent, top half is used for
 621  * clocksource.
 622  */
 623 static const struct davinci_timer_cfg dm355_timer_cfg = {
 624         .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
 625         .irq = {
 626                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
 627                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
 628         },
 629 };
 630
 631 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
 632         {
 633                 .mapbase        = DAVINCI_UART0_BASE,
 634                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
 635                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 636                                   UPF_IOREMAP,
 637                 .iotype         = UPIO_MEM,
 638                 .regshift       = 2,
 639         },
 640         {
 641                 .flags  = 0,
 642         }
 643 };
 644 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
 645         {
 646                 .mapbase        = DAVINCI_UART1_BASE,
 647                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
 648                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 649                                   UPF_IOREMAP,
 650                 .iotype         = UPIO_MEM,
 651                 .regshift       = 2,
 652         },
 653         {
 654                 .flags  = 0,
 655         }
 656 };
 657 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
 658         {
 659                 .mapbase        = DM355_UART2_BASE,
 660                 .irq            = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
 661                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 662                                   UPF_IOREMAP,
 663                 .iotype         = UPIO_MEM,
 664                 .regshift       = 2,
 665         },
 666         {
 667                 .flags  = 0,
 668         }
 669 };
 670
 671 struct platform_device dm355_serial_device[] = {
 672         {
 673                 .name                   = "serial8250",
 674                 .id                     = PLAT8250_DEV_PLATFORM,
 675                 .dev                    = {
 676                         .platform_data  = dm355_serial0_platform_data,
 677                 }
 678         },
 679         {
 680                 .name                   = "serial8250",
 681                 .id                     = PLAT8250_DEV_PLATFORM1,
 682                 .dev                    = {
 683                         .platform_data  = dm355_serial1_platform_data,
 684                 }
 685         },
 686         {
 687                 .name                   = "serial8250",
 688                 .id                     = PLAT8250_DEV_PLATFORM2,
 689                 .dev                    = {
 690                         .platform_data  = dm355_serial2_platform_data,
 691                 }
 692         },
 693         {
 694         }
 695 };
 696
 697 static const struct davinci_soc_info davinci_soc_info_dm355 = {
 698         .io_desc                = dm355_io_desc,
 699         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 700         .jtag_id_reg            = 0x01c40028,
 701         .ids                    = dm355_ids,
 702         .ids_num                = ARRAY_SIZE(dm355_ids),
 703         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 704         .pinmux_pins            = dm355_pins,
 705         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 706         .sram_dma               = 0x00010000,
 707         .sram_len               = SZ_32K,
 708 };
 709
 710 void __init dm355_init_asp1(u32 evt_enable)
 711 {
 712         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 713         if (evt_enable & ASP1_TX_EVT_EN)
 714                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 715
 716         if (evt_enable & ASP1_RX_EVT_EN)
 717                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 718
 719         platform_device_register(&dm355_asp1_device);
 720 }
 721
 722 void __init dm355_init(void)
 723 {
 724         davinci_common_init(&davinci_soc_info_dm355);
 725         davinci_map_sysmod();
 726 }
 727
 728 void __init dm355_init_time(void)
 729 {
 730         void __iomem *pll1, *psc;
 731         struct clk *clk;
 732         int rv;
 733
 734         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
 735
 736         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 737         dm355_pll1_init(NULL, pll1, NULL);
 738
 739         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 740         dm355_psc_init(NULL, psc);
 741
 742         clk = clk_get(NULL, "timer0");
 743         if (WARN_ON(IS_ERR(clk))) {
 744                 pr_err("Unable to get the timer clock\n");
 745                 return;
 746         }
 747
 748         rv = davinci_timer_register(clk, &dm355_timer_cfg);
 749         WARN(rv, "Unable to register the timer: %d\n", rv);
 750 }
 751
 752 static struct resource dm355_pll2_resources[] = {
 753         {
 754                 .start  = DAVINCI_PLL2_BASE,
 755                 .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
 756                 .flags  = IORESOURCE_MEM,
 757         },
 758 };
 759
 760 static struct platform_device dm355_pll2_device = {
 761         .name           = "dm355-pll2",
 762         .id             = -1,
 763         .resource       = dm355_pll2_resources,
 764         .num_resources  = ARRAY_SIZE(dm355_pll2_resources),
 765 };
 766
 767 void __init dm355_register_clocks(void)
 768 {
 769         /* PLL1 and PSC are registered in dm355_init_time() */
 770         platform_device_register(&dm355_pll2_device);
 771 }
 772
 773 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
 774                                 struct vpbe_config *vpbe_cfg)
 775 {
 776         if (vpfe_cfg || vpbe_cfg)
 777                 platform_device_register(&dm355_vpss_device);
 778
 779         if (vpfe_cfg) {
 780                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
 781                 platform_device_register(&dm355_ccdc_dev);
 782                 platform_device_register(&vpfe_capture_dev);
 783         }
 784
 785         if (vpbe_cfg) {
 786                 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
 787                 platform_device_register(&dm355_osd_dev);
 788                 platform_device_register(&dm355_venc_dev);
 789                 platform_device_register(&dm355_vpbe_dev);
 790                 platform_device_register(&dm355_vpbe_display);
 791         }
 792
 793         return 0;
 794 }
 795
 796 static const struct davinci_aintc_config dm355_aintc_config = {
 797         .reg = {
 798                 .start          = DAVINCI_ARM_INTC_BASE,
 799                 .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
 800                 .flags          = IORESOURCE_MEM,
 801         },
 802         .num_irqs               = 64,
 803         .prios                  = dm355_default_priorities,
 804 };
 805
 806 void __init dm355_init_irq(void)
 807 {
 808         davinci_aintc_init(&dm355_aintc_config);
 809 }
 810
 811 static int __init dm355_init_devices(void)
 812 {
 813         struct platform_device *edma_pdev;
 814         int ret = 0;
 815
 816         if (!cpu_is_davinci_dm355())
 817                 return 0;
 818
 819         davinci_cfg_reg(DM355_INT_EDMA_CC);
 820         edma_pdev = platform_device_register_full(&dm355_edma_device);
 821         if (IS_ERR(edma_pdev)) {
 822                 pr_warn("%s: Failed to register eDMA\n", __func__);
 823                 return PTR_ERR(edma_pdev);
 824         }
 825
 826         ret = davinci_init_wdt();
 827         if (ret)
 828                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
 829
 830         return ret;
 831 }
 832 postcore_initcall(dm355_init_devices);