2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-contiguous.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19 #include <linux/reboot.h>
20 #include <linux/dmaengine.h>
22 #include <mach/cputype.h>
23 #include <mach/common.h>
24 #include <mach/time.h>
25 #include <mach/da8xx.h>
32 #define DA8XX_TPCC_BASE 0x01c00000
33 #define DA8XX_TPTC0_BASE 0x01c08000
34 #define DA8XX_TPTC1_BASE 0x01c08400
35 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
36 #define DA8XX_I2C0_BASE 0x01c22000
37 #define DA8XX_RTC_BASE 0x01c23000
38 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
39 #define DA8XX_MMCSD0_BASE 0x01c40000
40 #define DA8XX_SPI0_BASE 0x01c41000
41 #define DA830_SPI1_BASE 0x01e12000
42 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
43 #define DA850_SATA_BASE 0x01e18000
44 #define DA850_MMCSD1_BASE 0x01e1b000
45 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
46 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
47 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
48 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
49 #define DA8XX_I2C1_BASE 0x01e28000
50 #define DA850_TPCC1_BASE 0x01e30000
51 #define DA850_TPTC2_BASE 0x01e38000
52 #define DA850_SPI1_BASE 0x01f0e000
53 #define DA8XX_DDR2_CTL_BASE 0xb0000000
55 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
56 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
57 #define DA8XX_EMAC_RAM_OFFSET 0x0000
58 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
60 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
61 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
62 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
63 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
64 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
65 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
66 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
67 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
69 void __iomem *da8xx_syscfg0_base;
70 void __iomem *da8xx_syscfg1_base;
72 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
74 .mapbase = DA8XX_UART0_BASE,
75 .irq = IRQ_DA8XX_UARTINT0,
76 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
85 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
87 .mapbase = DA8XX_UART1_BASE,
88 .irq = IRQ_DA8XX_UARTINT1,
89 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
98 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
100 .mapbase = DA8XX_UART2_BASE,
101 .irq = IRQ_DA8XX_UARTINT2,
102 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
112 struct platform_device da8xx_serial_device[] = {
114 .name = "serial8250",
115 .id = PLAT8250_DEV_PLATFORM,
117 .platform_data = da8xx_serial0_pdata,
121 .name = "serial8250",
122 .id = PLAT8250_DEV_PLATFORM1,
124 .platform_data = da8xx_serial1_pdata,
128 .name = "serial8250",
129 .id = PLAT8250_DEV_PLATFORM2,
131 .platform_data = da8xx_serial2_pdata,
138 static s8 da8xx_queue_priority_mapping[][2] = {
139 /* {event queue no, Priority} */
145 static s8 da850_queue_priority_mapping[][2] = {
146 /* {event queue no, Priority} */
151 static struct edma_soc_info da8xx_edma0_pdata = {
152 .queue_priority_mapping = da8xx_queue_priority_mapping,
153 .default_queue = EVENTQ_1,
156 static struct edma_soc_info da850_edma1_pdata = {
157 .queue_priority_mapping = da850_queue_priority_mapping,
158 .default_queue = EVENTQ_0,
161 static struct resource da8xx_edma0_resources[] = {
164 .start = DA8XX_TPCC_BASE,
165 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
166 .flags = IORESOURCE_MEM,
170 .start = DA8XX_TPTC0_BASE,
171 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
172 .flags = IORESOURCE_MEM,
176 .start = DA8XX_TPTC1_BASE,
177 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
178 .flags = IORESOURCE_MEM,
181 .name = "edma3_ccint",
182 .start = IRQ_DA8XX_CCINT0,
183 .flags = IORESOURCE_IRQ,
186 .name = "edma3_ccerrint",
187 .start = IRQ_DA8XX_CCERRINT,
188 .flags = IORESOURCE_IRQ,
192 static struct resource da850_edma1_resources[] = {
195 .start = DA850_TPCC1_BASE,
196 .end = DA850_TPCC1_BASE + SZ_32K - 1,
197 .flags = IORESOURCE_MEM,
201 .start = DA850_TPTC2_BASE,
202 .end = DA850_TPTC2_BASE + SZ_1K - 1,
203 .flags = IORESOURCE_MEM,
206 .name = "edma3_ccint",
207 .start = IRQ_DA850_CCINT1,
208 .flags = IORESOURCE_IRQ,
211 .name = "edma3_ccerrint",
212 .start = IRQ_DA850_CCERRINT1,
213 .flags = IORESOURCE_IRQ,
217 static const struct platform_device_info da8xx_edma0_device __initconst = {
220 .dma_mask = DMA_BIT_MASK(32),
221 .res = da8xx_edma0_resources,
222 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
223 .data = &da8xx_edma0_pdata,
224 .size_data = sizeof(da8xx_edma0_pdata),
227 static const struct platform_device_info da850_edma1_device __initconst = {
230 .dma_mask = DMA_BIT_MASK(32),
231 .res = da850_edma1_resources,
232 .num_res = ARRAY_SIZE(da850_edma1_resources),
233 .data = &da850_edma1_pdata,
234 .size_data = sizeof(da850_edma1_pdata),
237 static const struct dma_slave_map da830_edma_map[] = {
238 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
239 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
240 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
241 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
242 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
243 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
244 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
245 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
246 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
247 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
248 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
249 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
252 int __init da830_register_edma(struct edma_rsv_info *rsv)
254 struct platform_device *edma_pdev;
256 da8xx_edma0_pdata.rsv = rsv;
258 da8xx_edma0_pdata.slave_map = da830_edma_map;
259 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
261 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
262 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
265 static const struct dma_slave_map da850_edma0_map[] = {
266 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
267 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
268 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
269 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
270 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
271 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
272 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
273 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
274 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
275 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
276 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
277 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
280 static const struct dma_slave_map da850_edma1_map[] = {
281 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
282 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
285 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
287 struct platform_device *edma_pdev;
290 da8xx_edma0_pdata.rsv = rsv[0];
291 da850_edma1_pdata.rsv = rsv[1];
294 da8xx_edma0_pdata.slave_map = da850_edma0_map;
295 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
297 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
298 if (IS_ERR(edma_pdev)) {
299 pr_warn("%s: Failed to register eDMA0\n", __func__);
300 return PTR_ERR(edma_pdev);
303 da850_edma1_pdata.slave_map = da850_edma1_map;
304 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
306 edma_pdev = platform_device_register_full(&da850_edma1_device);
307 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
310 static struct resource da8xx_i2c_resources0[] = {
312 .start = DA8XX_I2C0_BASE,
313 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
314 .flags = IORESOURCE_MEM,
317 .start = IRQ_DA8XX_I2CINT0,
318 .end = IRQ_DA8XX_I2CINT0,
319 .flags = IORESOURCE_IRQ,
323 static struct platform_device da8xx_i2c_device0 = {
324 .name = "i2c_davinci",
326 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
327 .resource = da8xx_i2c_resources0,
330 static struct resource da8xx_i2c_resources1[] = {
332 .start = DA8XX_I2C1_BASE,
333 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
334 .flags = IORESOURCE_MEM,
337 .start = IRQ_DA8XX_I2CINT1,
338 .end = IRQ_DA8XX_I2CINT1,
339 .flags = IORESOURCE_IRQ,
343 static struct platform_device da8xx_i2c_device1 = {
344 .name = "i2c_davinci",
346 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
347 .resource = da8xx_i2c_resources1,
350 int __init da8xx_register_i2c(int instance,
351 struct davinci_i2c_platform_data *pdata)
353 struct platform_device *pdev;
356 pdev = &da8xx_i2c_device0;
357 else if (instance == 1)
358 pdev = &da8xx_i2c_device1;
362 pdev->dev.platform_data = pdata;
363 return platform_device_register(pdev);
366 static struct resource da8xx_watchdog_resources[] = {
368 .start = DA8XX_WDOG_BASE,
369 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
370 .flags = IORESOURCE_MEM,
374 static struct platform_device da8xx_wdt_device = {
375 .name = "davinci-wdt",
377 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
378 .resource = da8xx_watchdog_resources,
381 void da8xx_restart(enum reboot_mode mode, const char *cmd)
385 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
387 pr_err("%s: failed to find watchdog device\n", __func__);
391 davinci_watchdog_reset(to_platform_device(dev));
394 int __init da8xx_register_watchdog(void)
396 return platform_device_register(&da8xx_wdt_device);
399 static struct resource da8xx_emac_resources[] = {
401 .start = DA8XX_EMAC_CPPI_PORT_BASE,
402 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
403 .flags = IORESOURCE_MEM,
406 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
407 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
408 .flags = IORESOURCE_IRQ,
411 .start = IRQ_DA8XX_C0_RX_PULSE,
412 .end = IRQ_DA8XX_C0_RX_PULSE,
413 .flags = IORESOURCE_IRQ,
416 .start = IRQ_DA8XX_C0_TX_PULSE,
417 .end = IRQ_DA8XX_C0_TX_PULSE,
418 .flags = IORESOURCE_IRQ,
421 .start = IRQ_DA8XX_C0_MISC_PULSE,
422 .end = IRQ_DA8XX_C0_MISC_PULSE,
423 .flags = IORESOURCE_IRQ,
427 struct emac_platform_data da8xx_emac_pdata = {
428 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
429 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
430 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
431 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
432 .version = EMAC_VERSION_2,
435 static struct platform_device da8xx_emac_device = {
436 .name = "davinci_emac",
439 .platform_data = &da8xx_emac_pdata,
441 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
442 .resource = da8xx_emac_resources,
445 static struct resource da8xx_mdio_resources[] = {
447 .start = DA8XX_EMAC_MDIO_BASE,
448 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
449 .flags = IORESOURCE_MEM,
453 static struct platform_device da8xx_mdio_device = {
454 .name = "davinci_mdio",
456 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
457 .resource = da8xx_mdio_resources,
460 int __init da8xx_register_emac(void)
464 ret = platform_device_register(&da8xx_mdio_device);
468 return platform_device_register(&da8xx_emac_device);
471 static struct resource da830_mcasp1_resources[] = {
474 .start = DAVINCI_DA830_MCASP1_REG_BASE,
475 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
476 .flags = IORESOURCE_MEM,
481 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
482 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
483 .flags = IORESOURCE_DMA,
488 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
489 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
490 .flags = IORESOURCE_DMA,
494 .start = IRQ_DA8XX_MCASPINT,
495 .flags = IORESOURCE_IRQ,
499 static struct platform_device da830_mcasp1_device = {
500 .name = "davinci-mcasp",
502 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
503 .resource = da830_mcasp1_resources,
506 static struct resource da830_mcasp2_resources[] = {
509 .start = DAVINCI_DA830_MCASP2_REG_BASE,
510 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
511 .flags = IORESOURCE_MEM,
516 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
517 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
518 .flags = IORESOURCE_DMA,
523 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
524 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
525 .flags = IORESOURCE_DMA,
529 .start = IRQ_DA8XX_MCASPINT,
530 .flags = IORESOURCE_IRQ,
534 static struct platform_device da830_mcasp2_device = {
535 .name = "davinci-mcasp",
537 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
538 .resource = da830_mcasp2_resources,
541 static struct resource da850_mcasp_resources[] = {
544 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
545 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
546 .flags = IORESOURCE_MEM,
551 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
552 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
553 .flags = IORESOURCE_DMA,
558 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
559 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
560 .flags = IORESOURCE_DMA,
564 .start = IRQ_DA8XX_MCASPINT,
565 .flags = IORESOURCE_IRQ,
569 static struct platform_device da850_mcasp_device = {
570 .name = "davinci-mcasp",
572 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
573 .resource = da850_mcasp_resources,
576 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
578 struct platform_device *pdev;
582 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
583 pdev = &da850_mcasp_device;
586 /* Valid for DA830/OMAP-L137 only */
587 if (!cpu_is_davinci_da830())
589 pdev = &da830_mcasp1_device;
592 /* Valid for DA830/OMAP-L137 only */
593 if (!cpu_is_davinci_da830())
595 pdev = &da830_mcasp2_device;
601 pdev->dev.platform_data = pdata;
602 platform_device_register(pdev);
605 static struct resource da8xx_pruss_resources[] = {
607 .start = DA8XX_PRUSS_MEM_BASE,
608 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
609 .flags = IORESOURCE_MEM,
612 .start = IRQ_DA8XX_EVTOUT0,
613 .end = IRQ_DA8XX_EVTOUT0,
614 .flags = IORESOURCE_IRQ,
617 .start = IRQ_DA8XX_EVTOUT1,
618 .end = IRQ_DA8XX_EVTOUT1,
619 .flags = IORESOURCE_IRQ,
622 .start = IRQ_DA8XX_EVTOUT2,
623 .end = IRQ_DA8XX_EVTOUT2,
624 .flags = IORESOURCE_IRQ,
627 .start = IRQ_DA8XX_EVTOUT3,
628 .end = IRQ_DA8XX_EVTOUT3,
629 .flags = IORESOURCE_IRQ,
632 .start = IRQ_DA8XX_EVTOUT4,
633 .end = IRQ_DA8XX_EVTOUT4,
634 .flags = IORESOURCE_IRQ,
637 .start = IRQ_DA8XX_EVTOUT5,
638 .end = IRQ_DA8XX_EVTOUT5,
639 .flags = IORESOURCE_IRQ,
642 .start = IRQ_DA8XX_EVTOUT6,
643 .end = IRQ_DA8XX_EVTOUT6,
644 .flags = IORESOURCE_IRQ,
647 .start = IRQ_DA8XX_EVTOUT7,
648 .end = IRQ_DA8XX_EVTOUT7,
649 .flags = IORESOURCE_IRQ,
653 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
654 .pintc_base = 0x4000,
657 static struct platform_device da8xx_uio_pruss_dev = {
660 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
661 .resource = da8xx_pruss_resources,
663 .coherent_dma_mask = DMA_BIT_MASK(32),
664 .platform_data = &da8xx_uio_pruss_pdata,
668 int __init da8xx_register_uio_pruss(void)
670 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
671 return platform_device_register(&da8xx_uio_pruss_dev);
674 static struct lcd_ctrl_config lcd_cfg = {
675 .panel_shade = COLOR_ACTIVE,
679 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
680 .manu_name = "sharp",
681 .controller_data = &lcd_cfg,
682 .type = "Sharp_LCD035Q3DG01",
685 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
686 .manu_name = "sharp",
687 .controller_data = &lcd_cfg,
688 .type = "Sharp_LK043T1DG01",
691 static struct resource da8xx_lcdc_resources[] = {
692 [0] = { /* registers */
693 .start = DA8XX_LCD_CNTRL_BASE,
694 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
695 .flags = IORESOURCE_MEM,
697 [1] = { /* interrupt */
698 .start = IRQ_DA8XX_LCDINT,
699 .end = IRQ_DA8XX_LCDINT,
700 .flags = IORESOURCE_IRQ,
704 static struct platform_device da8xx_lcdc_device = {
705 .name = "da8xx_lcdc",
707 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
708 .resource = da8xx_lcdc_resources,
710 .coherent_dma_mask = DMA_BIT_MASK(32),
714 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
716 da8xx_lcdc_device.dev.platform_data = pdata;
717 return platform_device_register(&da8xx_lcdc_device);
720 static struct resource da8xx_gpio_resources[] = {
722 .start = DA8XX_GPIO_BASE,
723 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
724 .flags = IORESOURCE_MEM,
727 .start = IRQ_DA8XX_GPIO0,
728 .end = IRQ_DA8XX_GPIO8,
729 .flags = IORESOURCE_IRQ,
733 static struct platform_device da8xx_gpio_device = {
734 .name = "davinci_gpio",
736 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
737 .resource = da8xx_gpio_resources,
740 int __init da8xx_register_gpio(void *pdata)
742 da8xx_gpio_device.dev.platform_data = pdata;
743 return platform_device_register(&da8xx_gpio_device);
746 static struct resource da8xx_mmcsd0_resources[] = {
748 .start = DA8XX_MMCSD0_BASE,
749 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
750 .flags = IORESOURCE_MEM,
753 .start = IRQ_DA8XX_MMCSDINT0,
754 .end = IRQ_DA8XX_MMCSDINT0,
755 .flags = IORESOURCE_IRQ,
759 static struct platform_device da8xx_mmcsd0_device = {
762 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
763 .resource = da8xx_mmcsd0_resources,
766 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
768 da8xx_mmcsd0_device.dev.platform_data = config;
769 return platform_device_register(&da8xx_mmcsd0_device);
772 #ifdef CONFIG_ARCH_DAVINCI_DA850
773 static struct resource da850_mmcsd1_resources[] = {
775 .start = DA850_MMCSD1_BASE,
776 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
777 .flags = IORESOURCE_MEM,
780 .start = IRQ_DA850_MMCSDINT0_1,
781 .end = IRQ_DA850_MMCSDINT0_1,
782 .flags = IORESOURCE_IRQ,
786 static struct platform_device da850_mmcsd1_device = {
789 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
790 .resource = da850_mmcsd1_resources,
793 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
795 da850_mmcsd1_device.dev.platform_data = config;
796 return platform_device_register(&da850_mmcsd1_device);
800 static struct resource da8xx_rproc_resources[] = {
801 { /* DSP boot address */
802 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
803 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
804 .flags = IORESOURCE_MEM,
806 { /* DSP interrupt registers */
807 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
808 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
809 .flags = IORESOURCE_MEM,
812 .start = IRQ_DA8XX_CHIPINT0,
813 .end = IRQ_DA8XX_CHIPINT0,
814 .flags = IORESOURCE_IRQ,
818 static struct platform_device da8xx_dsp = {
819 .name = "davinci-rproc",
821 .coherent_dma_mask = DMA_BIT_MASK(32),
823 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
824 .resource = da8xx_rproc_resources,
827 static bool rproc_mem_inited __initdata;
829 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
831 static phys_addr_t rproc_base __initdata;
832 static unsigned long rproc_size __initdata;
834 static int __init early_rproc_mem(char *p)
841 rproc_size = memparse(p, &endp);
843 rproc_base = memparse(endp + 1, NULL);
847 early_param("rproc_mem", early_rproc_mem);
849 void __init da8xx_rproc_reserve_cma(void)
853 if (!rproc_base || !rproc_size) {
854 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
855 " 'nn' and 'address' must both be non-zero\n",
861 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
862 __func__, rproc_size, (unsigned long)rproc_base);
864 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
866 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
868 rproc_mem_inited = true;
873 void __init da8xx_rproc_reserve_cma(void)
879 int __init da8xx_register_rproc(void)
883 if (!rproc_mem_inited) {
884 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
889 ret = platform_device_register(&da8xx_dsp);
891 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
896 static struct resource da8xx_rtc_resources[] = {
898 .start = DA8XX_RTC_BASE,
899 .end = DA8XX_RTC_BASE + SZ_4K - 1,
900 .flags = IORESOURCE_MEM,
903 .start = IRQ_DA8XX_RTC,
904 .end = IRQ_DA8XX_RTC,
905 .flags = IORESOURCE_IRQ,
908 .start = IRQ_DA8XX_RTC,
909 .end = IRQ_DA8XX_RTC,
910 .flags = IORESOURCE_IRQ,
914 static struct platform_device da8xx_rtc_device = {
917 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
918 .resource = da8xx_rtc_resources,
921 int da8xx_register_rtc(void)
923 return platform_device_register(&da8xx_rtc_device);
926 static void __iomem *da8xx_ddr2_ctlr_base;
927 void __iomem * __init da8xx_get_mem_ctlr(void)
929 if (da8xx_ddr2_ctlr_base)
930 return da8xx_ddr2_ctlr_base;
932 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
933 if (!da8xx_ddr2_ctlr_base)
934 pr_warn("%s: Unable to map DDR2 controller", __func__);
936 return da8xx_ddr2_ctlr_base;
939 static struct resource da8xx_cpuidle_resources[] = {
941 .start = DA8XX_DDR2_CTL_BASE,
942 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
943 .flags = IORESOURCE_MEM,
947 /* DA8XX devices support DDR2 power down */
948 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
953 static struct platform_device da8xx_cpuidle_device = {
954 .name = "cpuidle-davinci",
955 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
956 .resource = da8xx_cpuidle_resources,
958 .platform_data = &da8xx_cpuidle_pdata,
962 int __init da8xx_register_cpuidle(void)
964 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
966 return platform_device_register(&da8xx_cpuidle_device);
969 static struct resource da8xx_spi0_resources[] = {
971 .start = DA8XX_SPI0_BASE,
972 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
973 .flags = IORESOURCE_MEM,
976 .start = IRQ_DA8XX_SPINT0,
977 .end = IRQ_DA8XX_SPINT0,
978 .flags = IORESOURCE_IRQ,
981 .start = DA8XX_DMA_SPI0_RX,
982 .end = DA8XX_DMA_SPI0_RX,
983 .flags = IORESOURCE_DMA,
986 .start = DA8XX_DMA_SPI0_TX,
987 .end = DA8XX_DMA_SPI0_TX,
988 .flags = IORESOURCE_DMA,
992 static struct resource da8xx_spi1_resources[] = {
994 .start = DA830_SPI1_BASE,
995 .end = DA830_SPI1_BASE + SZ_4K - 1,
996 .flags = IORESOURCE_MEM,
999 .start = IRQ_DA8XX_SPINT1,
1000 .end = IRQ_DA8XX_SPINT1,
1001 .flags = IORESOURCE_IRQ,
1004 .start = DA8XX_DMA_SPI1_RX,
1005 .end = DA8XX_DMA_SPI1_RX,
1006 .flags = IORESOURCE_DMA,
1009 .start = DA8XX_DMA_SPI1_TX,
1010 .end = DA8XX_DMA_SPI1_TX,
1011 .flags = IORESOURCE_DMA,
1015 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1017 .version = SPI_VERSION_2,
1019 .dma_event_q = EVENTQ_0,
1020 .prescaler_limit = 2,
1023 .version = SPI_VERSION_2,
1025 .dma_event_q = EVENTQ_0,
1026 .prescaler_limit = 2,
1030 static struct platform_device da8xx_spi_device[] = {
1032 .name = "spi_davinci",
1034 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1035 .resource = da8xx_spi0_resources,
1037 .platform_data = &da8xx_spi_pdata[0],
1041 .name = "spi_davinci",
1043 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1044 .resource = da8xx_spi1_resources,
1046 .platform_data = &da8xx_spi_pdata[1],
1051 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1053 if (instance < 0 || instance > 1)
1056 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1058 if (instance == 1 && cpu_is_davinci_da850()) {
1059 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1060 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1063 return platform_device_register(&da8xx_spi_device[instance]);
1066 #ifdef CONFIG_ARCH_DAVINCI_DA850
1067 static struct resource da850_sata_resources[] = {
1069 .start = DA850_SATA_BASE,
1070 .end = DA850_SATA_BASE + 0x1fff,
1071 .flags = IORESOURCE_MEM,
1074 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1075 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1076 .flags = IORESOURCE_MEM,
1079 .start = IRQ_DA850_SATAINT,
1080 .flags = IORESOURCE_IRQ,
1084 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1086 static struct platform_device da850_sata_device = {
1087 .name = "ahci_da850",
1090 .dma_mask = &da850_sata_dmamask,
1091 .coherent_dma_mask = DMA_BIT_MASK(32),
1093 .num_resources = ARRAY_SIZE(da850_sata_resources),
1094 .resource = da850_sata_resources,
1097 int __init da850_register_sata(unsigned long refclkpn)
1099 /* please see comment in drivers/ata/ahci_da850.c */
1100 BUG_ON(refclkpn != 100 * 1000 * 1000);
1102 return platform_device_register(&da850_sata_device);