2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-contiguous.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19 #include <linux/reboot.h>
21 #include <mach/cputype.h>
22 #include <mach/common.h>
23 #include <mach/time.h>
24 #include <mach/da8xx.h>
25 #include <mach/cpuidle.h>
26 #include <mach/sram.h>
31 #define DA8XX_TPCC_BASE 0x01c00000
32 #define DA8XX_TPTC0_BASE 0x01c08000
33 #define DA8XX_TPTC1_BASE 0x01c08400
34 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
35 #define DA8XX_I2C0_BASE 0x01c22000
36 #define DA8XX_RTC_BASE 0x01c23000
37 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
38 #define DA8XX_MMCSD0_BASE 0x01c40000
39 #define DA8XX_SPI0_BASE 0x01c41000
40 #define DA830_SPI1_BASE 0x01e12000
41 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
42 #define DA850_SATA_BASE 0x01e18000
43 #define DA850_MMCSD1_BASE 0x01e1b000
44 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
45 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
46 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
47 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
48 #define DA8XX_I2C1_BASE 0x01e28000
49 #define DA850_TPCC1_BASE 0x01e30000
50 #define DA850_TPTC2_BASE 0x01e38000
51 #define DA850_SPI1_BASE 0x01f0e000
52 #define DA8XX_DDR2_CTL_BASE 0xb0000000
54 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
55 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
56 #define DA8XX_EMAC_RAM_OFFSET 0x0000
57 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
59 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
60 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
61 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
62 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
63 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
64 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
65 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
66 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
68 void __iomem *da8xx_syscfg0_base;
69 void __iomem *da8xx_syscfg1_base;
71 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
73 .mapbase = DA8XX_UART0_BASE,
74 .irq = IRQ_DA8XX_UARTINT0,
75 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
84 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
86 .mapbase = DA8XX_UART1_BASE,
87 .irq = IRQ_DA8XX_UARTINT1,
88 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
97 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
99 .mapbase = DA8XX_UART2_BASE,
100 .irq = IRQ_DA8XX_UARTINT2,
101 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
111 struct platform_device da8xx_serial_device[] = {
113 .name = "serial8250",
114 .id = PLAT8250_DEV_PLATFORM,
116 .platform_data = da8xx_serial0_pdata,
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM1,
123 .platform_data = da8xx_serial1_pdata,
127 .name = "serial8250",
128 .id = PLAT8250_DEV_PLATFORM2,
130 .platform_data = da8xx_serial2_pdata,
137 static s8 da8xx_queue_priority_mapping[][2] = {
138 /* {event queue no, Priority} */
144 static s8 da850_queue_priority_mapping[][2] = {
145 /* {event queue no, Priority} */
150 static struct edma_soc_info da8xx_edma0_pdata = {
151 .queue_priority_mapping = da8xx_queue_priority_mapping,
152 .default_queue = EVENTQ_1,
155 static struct edma_soc_info da850_edma1_pdata = {
156 .queue_priority_mapping = da850_queue_priority_mapping,
157 .default_queue = EVENTQ_0,
160 static struct resource da8xx_edma0_resources[] = {
163 .start = DA8XX_TPCC_BASE,
164 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
165 .flags = IORESOURCE_MEM,
169 .start = DA8XX_TPTC0_BASE,
170 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
171 .flags = IORESOURCE_MEM,
175 .start = DA8XX_TPTC1_BASE,
176 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
177 .flags = IORESOURCE_MEM,
180 .name = "edma3_ccint",
181 .start = IRQ_DA8XX_CCINT0,
182 .flags = IORESOURCE_IRQ,
185 .name = "edma3_ccerrint",
186 .start = IRQ_DA8XX_CCERRINT,
187 .flags = IORESOURCE_IRQ,
191 static struct resource da850_edma1_resources[] = {
194 .start = DA850_TPCC1_BASE,
195 .end = DA850_TPCC1_BASE + SZ_32K - 1,
196 .flags = IORESOURCE_MEM,
200 .start = DA850_TPTC2_BASE,
201 .end = DA850_TPTC2_BASE + SZ_1K - 1,
202 .flags = IORESOURCE_MEM,
205 .name = "edma3_ccint",
206 .start = IRQ_DA850_CCINT1,
207 .flags = IORESOURCE_IRQ,
210 .name = "edma3_ccerrint",
211 .start = IRQ_DA850_CCERRINT1,
212 .flags = IORESOURCE_IRQ,
216 static const struct platform_device_info da8xx_edma0_device __initconst = {
219 .dma_mask = DMA_BIT_MASK(32),
220 .res = da8xx_edma0_resources,
221 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
222 .data = &da8xx_edma0_pdata,
223 .size_data = sizeof(da8xx_edma0_pdata),
226 static const struct platform_device_info da850_edma1_device __initconst = {
229 .dma_mask = DMA_BIT_MASK(32),
230 .res = da850_edma1_resources,
231 .num_res = ARRAY_SIZE(da850_edma1_resources),
232 .data = &da850_edma1_pdata,
233 .size_data = sizeof(da850_edma1_pdata),
236 int __init da830_register_edma(struct edma_rsv_info *rsv)
238 struct platform_device *edma_pdev;
240 da8xx_edma0_pdata.rsv = rsv;
242 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
243 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
246 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
248 struct platform_device *edma_pdev;
251 da8xx_edma0_pdata.rsv = rsv[0];
252 da850_edma1_pdata.rsv = rsv[1];
255 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
256 if (IS_ERR(edma_pdev)) {
257 pr_warn("%s: Failed to register eDMA0\n", __func__);
258 return PTR_ERR(edma_pdev);
260 edma_pdev = platform_device_register_full(&da850_edma1_device);
261 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
264 static struct resource da8xx_i2c_resources0[] = {
266 .start = DA8XX_I2C0_BASE,
267 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
268 .flags = IORESOURCE_MEM,
271 .start = IRQ_DA8XX_I2CINT0,
272 .end = IRQ_DA8XX_I2CINT0,
273 .flags = IORESOURCE_IRQ,
277 static struct platform_device da8xx_i2c_device0 = {
278 .name = "i2c_davinci",
280 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
281 .resource = da8xx_i2c_resources0,
284 static struct resource da8xx_i2c_resources1[] = {
286 .start = DA8XX_I2C1_BASE,
287 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
288 .flags = IORESOURCE_MEM,
291 .start = IRQ_DA8XX_I2CINT1,
292 .end = IRQ_DA8XX_I2CINT1,
293 .flags = IORESOURCE_IRQ,
297 static struct platform_device da8xx_i2c_device1 = {
298 .name = "i2c_davinci",
300 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
301 .resource = da8xx_i2c_resources1,
304 int __init da8xx_register_i2c(int instance,
305 struct davinci_i2c_platform_data *pdata)
307 struct platform_device *pdev;
310 pdev = &da8xx_i2c_device0;
311 else if (instance == 1)
312 pdev = &da8xx_i2c_device1;
316 pdev->dev.platform_data = pdata;
317 return platform_device_register(pdev);
320 static struct resource da8xx_watchdog_resources[] = {
322 .start = DA8XX_WDOG_BASE,
323 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
324 .flags = IORESOURCE_MEM,
328 static struct platform_device da8xx_wdt_device = {
329 .name = "davinci-wdt",
331 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
332 .resource = da8xx_watchdog_resources,
335 void da8xx_restart(enum reboot_mode mode, const char *cmd)
339 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
341 pr_err("%s: failed to find watchdog device\n", __func__);
345 davinci_watchdog_reset(to_platform_device(dev));
348 int __init da8xx_register_watchdog(void)
350 return platform_device_register(&da8xx_wdt_device);
353 static struct resource da8xx_emac_resources[] = {
355 .start = DA8XX_EMAC_CPPI_PORT_BASE,
356 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
357 .flags = IORESOURCE_MEM,
360 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
361 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
362 .flags = IORESOURCE_IRQ,
365 .start = IRQ_DA8XX_C0_RX_PULSE,
366 .end = IRQ_DA8XX_C0_RX_PULSE,
367 .flags = IORESOURCE_IRQ,
370 .start = IRQ_DA8XX_C0_TX_PULSE,
371 .end = IRQ_DA8XX_C0_TX_PULSE,
372 .flags = IORESOURCE_IRQ,
375 .start = IRQ_DA8XX_C0_MISC_PULSE,
376 .end = IRQ_DA8XX_C0_MISC_PULSE,
377 .flags = IORESOURCE_IRQ,
381 struct emac_platform_data da8xx_emac_pdata = {
382 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
383 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
384 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
385 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
386 .version = EMAC_VERSION_2,
389 static struct platform_device da8xx_emac_device = {
390 .name = "davinci_emac",
393 .platform_data = &da8xx_emac_pdata,
395 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
396 .resource = da8xx_emac_resources,
399 static struct resource da8xx_mdio_resources[] = {
401 .start = DA8XX_EMAC_MDIO_BASE,
402 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
403 .flags = IORESOURCE_MEM,
407 static struct platform_device da8xx_mdio_device = {
408 .name = "davinci_mdio",
410 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
411 .resource = da8xx_mdio_resources,
414 int __init da8xx_register_emac(void)
418 ret = platform_device_register(&da8xx_mdio_device);
422 return platform_device_register(&da8xx_emac_device);
425 static struct resource da830_mcasp1_resources[] = {
428 .start = DAVINCI_DA830_MCASP1_REG_BASE,
429 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
430 .flags = IORESOURCE_MEM,
435 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
436 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
437 .flags = IORESOURCE_DMA,
442 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
443 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
444 .flags = IORESOURCE_DMA,
448 .start = IRQ_DA8XX_MCASPINT,
449 .flags = IORESOURCE_IRQ,
453 static struct platform_device da830_mcasp1_device = {
454 .name = "davinci-mcasp",
456 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
457 .resource = da830_mcasp1_resources,
460 static struct resource da830_mcasp2_resources[] = {
463 .start = DAVINCI_DA830_MCASP2_REG_BASE,
464 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
465 .flags = IORESOURCE_MEM,
470 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
471 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
472 .flags = IORESOURCE_DMA,
477 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
478 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
479 .flags = IORESOURCE_DMA,
483 .start = IRQ_DA8XX_MCASPINT,
484 .flags = IORESOURCE_IRQ,
488 static struct platform_device da830_mcasp2_device = {
489 .name = "davinci-mcasp",
491 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
492 .resource = da830_mcasp2_resources,
495 static struct resource da850_mcasp_resources[] = {
498 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
499 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
500 .flags = IORESOURCE_MEM,
505 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
506 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
507 .flags = IORESOURCE_DMA,
512 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
513 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
514 .flags = IORESOURCE_DMA,
518 .start = IRQ_DA8XX_MCASPINT,
519 .flags = IORESOURCE_IRQ,
523 static struct platform_device da850_mcasp_device = {
524 .name = "davinci-mcasp",
526 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
527 .resource = da850_mcasp_resources,
530 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
532 struct platform_device *pdev;
536 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
537 pdev = &da850_mcasp_device;
540 /* Valid for DA830/OMAP-L137 only */
541 if (!cpu_is_davinci_da830())
543 pdev = &da830_mcasp1_device;
546 /* Valid for DA830/OMAP-L137 only */
547 if (!cpu_is_davinci_da830())
549 pdev = &da830_mcasp2_device;
555 pdev->dev.platform_data = pdata;
556 platform_device_register(pdev);
559 static struct resource da8xx_pruss_resources[] = {
561 .start = DA8XX_PRUSS_MEM_BASE,
562 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
563 .flags = IORESOURCE_MEM,
566 .start = IRQ_DA8XX_EVTOUT0,
567 .end = IRQ_DA8XX_EVTOUT0,
568 .flags = IORESOURCE_IRQ,
571 .start = IRQ_DA8XX_EVTOUT1,
572 .end = IRQ_DA8XX_EVTOUT1,
573 .flags = IORESOURCE_IRQ,
576 .start = IRQ_DA8XX_EVTOUT2,
577 .end = IRQ_DA8XX_EVTOUT2,
578 .flags = IORESOURCE_IRQ,
581 .start = IRQ_DA8XX_EVTOUT3,
582 .end = IRQ_DA8XX_EVTOUT3,
583 .flags = IORESOURCE_IRQ,
586 .start = IRQ_DA8XX_EVTOUT4,
587 .end = IRQ_DA8XX_EVTOUT4,
588 .flags = IORESOURCE_IRQ,
591 .start = IRQ_DA8XX_EVTOUT5,
592 .end = IRQ_DA8XX_EVTOUT5,
593 .flags = IORESOURCE_IRQ,
596 .start = IRQ_DA8XX_EVTOUT6,
597 .end = IRQ_DA8XX_EVTOUT6,
598 .flags = IORESOURCE_IRQ,
601 .start = IRQ_DA8XX_EVTOUT7,
602 .end = IRQ_DA8XX_EVTOUT7,
603 .flags = IORESOURCE_IRQ,
607 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
608 .pintc_base = 0x4000,
611 static struct platform_device da8xx_uio_pruss_dev = {
614 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
615 .resource = da8xx_pruss_resources,
617 .coherent_dma_mask = DMA_BIT_MASK(32),
618 .platform_data = &da8xx_uio_pruss_pdata,
622 int __init da8xx_register_uio_pruss(void)
624 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
625 return platform_device_register(&da8xx_uio_pruss_dev);
628 static struct lcd_ctrl_config lcd_cfg = {
629 .panel_shade = COLOR_ACTIVE,
633 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
634 .manu_name = "sharp",
635 .controller_data = &lcd_cfg,
636 .type = "Sharp_LCD035Q3DG01",
639 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
640 .manu_name = "sharp",
641 .controller_data = &lcd_cfg,
642 .type = "Sharp_LK043T1DG01",
645 static struct resource da8xx_lcdc_resources[] = {
646 [0] = { /* registers */
647 .start = DA8XX_LCD_CNTRL_BASE,
648 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
649 .flags = IORESOURCE_MEM,
651 [1] = { /* interrupt */
652 .start = IRQ_DA8XX_LCDINT,
653 .end = IRQ_DA8XX_LCDINT,
654 .flags = IORESOURCE_IRQ,
658 static struct platform_device da8xx_lcdc_device = {
659 .name = "da8xx_lcdc",
661 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
662 .resource = da8xx_lcdc_resources,
664 .coherent_dma_mask = DMA_BIT_MASK(32),
668 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
670 da8xx_lcdc_device.dev.platform_data = pdata;
671 return platform_device_register(&da8xx_lcdc_device);
674 static struct resource da8xx_gpio_resources[] = {
676 .start = DA8XX_GPIO_BASE,
677 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
678 .flags = IORESOURCE_MEM,
681 .start = IRQ_DA8XX_GPIO0,
682 .end = IRQ_DA8XX_GPIO8,
683 .flags = IORESOURCE_IRQ,
687 static struct platform_device da8xx_gpio_device = {
688 .name = "davinci_gpio",
690 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
691 .resource = da8xx_gpio_resources,
694 int __init da8xx_register_gpio(void *pdata)
696 da8xx_gpio_device.dev.platform_data = pdata;
697 return platform_device_register(&da8xx_gpio_device);
700 static struct resource da8xx_mmcsd0_resources[] = {
702 .start = DA8XX_MMCSD0_BASE,
703 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
704 .flags = IORESOURCE_MEM,
707 .start = IRQ_DA8XX_MMCSDINT0,
708 .end = IRQ_DA8XX_MMCSDINT0,
709 .flags = IORESOURCE_IRQ,
712 .start = DA8XX_DMA_MMCSD0_RX,
713 .end = DA8XX_DMA_MMCSD0_RX,
714 .flags = IORESOURCE_DMA,
717 .start = DA8XX_DMA_MMCSD0_TX,
718 .end = DA8XX_DMA_MMCSD0_TX,
719 .flags = IORESOURCE_DMA,
723 static struct platform_device da8xx_mmcsd0_device = {
726 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
727 .resource = da8xx_mmcsd0_resources,
730 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
732 da8xx_mmcsd0_device.dev.platform_data = config;
733 return platform_device_register(&da8xx_mmcsd0_device);
736 #ifdef CONFIG_ARCH_DAVINCI_DA850
737 static struct resource da850_mmcsd1_resources[] = {
739 .start = DA850_MMCSD1_BASE,
740 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
741 .flags = IORESOURCE_MEM,
744 .start = IRQ_DA850_MMCSDINT0_1,
745 .end = IRQ_DA850_MMCSDINT0_1,
746 .flags = IORESOURCE_IRQ,
749 .start = DA850_DMA_MMCSD1_RX,
750 .end = DA850_DMA_MMCSD1_RX,
751 .flags = IORESOURCE_DMA,
754 .start = DA850_DMA_MMCSD1_TX,
755 .end = DA850_DMA_MMCSD1_TX,
756 .flags = IORESOURCE_DMA,
760 static struct platform_device da850_mmcsd1_device = {
763 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
764 .resource = da850_mmcsd1_resources,
767 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
769 da850_mmcsd1_device.dev.platform_data = config;
770 return platform_device_register(&da850_mmcsd1_device);
774 static struct resource da8xx_rproc_resources[] = {
775 { /* DSP boot address */
776 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
777 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
778 .flags = IORESOURCE_MEM,
780 { /* DSP interrupt registers */
781 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
782 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
783 .flags = IORESOURCE_MEM,
786 .start = IRQ_DA8XX_CHIPINT0,
787 .end = IRQ_DA8XX_CHIPINT0,
788 .flags = IORESOURCE_IRQ,
792 static struct platform_device da8xx_dsp = {
793 .name = "davinci-rproc",
795 .coherent_dma_mask = DMA_BIT_MASK(32),
797 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
798 .resource = da8xx_rproc_resources,
801 static bool rproc_mem_inited __initdata;
803 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
805 static phys_addr_t rproc_base __initdata;
806 static unsigned long rproc_size __initdata;
808 static int __init early_rproc_mem(char *p)
815 rproc_size = memparse(p, &endp);
817 rproc_base = memparse(endp + 1, NULL);
821 early_param("rproc_mem", early_rproc_mem);
823 void __init da8xx_rproc_reserve_cma(void)
827 if (!rproc_base || !rproc_size) {
828 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
829 " 'nn' and 'address' must both be non-zero\n",
835 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
836 __func__, rproc_size, (unsigned long)rproc_base);
838 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
840 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
842 rproc_mem_inited = true;
847 void __init da8xx_rproc_reserve_cma(void)
853 int __init da8xx_register_rproc(void)
857 if (!rproc_mem_inited) {
858 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
863 ret = platform_device_register(&da8xx_dsp);
865 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
870 static struct resource da8xx_rtc_resources[] = {
872 .start = DA8XX_RTC_BASE,
873 .end = DA8XX_RTC_BASE + SZ_4K - 1,
874 .flags = IORESOURCE_MEM,
877 .start = IRQ_DA8XX_RTC,
878 .end = IRQ_DA8XX_RTC,
879 .flags = IORESOURCE_IRQ,
882 .start = IRQ_DA8XX_RTC,
883 .end = IRQ_DA8XX_RTC,
884 .flags = IORESOURCE_IRQ,
888 static struct platform_device da8xx_rtc_device = {
891 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
892 .resource = da8xx_rtc_resources,
895 int da8xx_register_rtc(void)
897 return platform_device_register(&da8xx_rtc_device);
900 static void __iomem *da8xx_ddr2_ctlr_base;
901 void __iomem * __init da8xx_get_mem_ctlr(void)
903 if (da8xx_ddr2_ctlr_base)
904 return da8xx_ddr2_ctlr_base;
906 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
907 if (!da8xx_ddr2_ctlr_base)
908 pr_warn("%s: Unable to map DDR2 controller", __func__);
910 return da8xx_ddr2_ctlr_base;
913 static struct resource da8xx_cpuidle_resources[] = {
915 .start = DA8XX_DDR2_CTL_BASE,
916 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
917 .flags = IORESOURCE_MEM,
921 /* DA8XX devices support DDR2 power down */
922 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
927 static struct platform_device da8xx_cpuidle_device = {
928 .name = "cpuidle-davinci",
929 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
930 .resource = da8xx_cpuidle_resources,
932 .platform_data = &da8xx_cpuidle_pdata,
936 int __init da8xx_register_cpuidle(void)
938 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
940 return platform_device_register(&da8xx_cpuidle_device);
943 static struct resource da8xx_spi0_resources[] = {
945 .start = DA8XX_SPI0_BASE,
946 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
947 .flags = IORESOURCE_MEM,
950 .start = IRQ_DA8XX_SPINT0,
951 .end = IRQ_DA8XX_SPINT0,
952 .flags = IORESOURCE_IRQ,
955 .start = DA8XX_DMA_SPI0_RX,
956 .end = DA8XX_DMA_SPI0_RX,
957 .flags = IORESOURCE_DMA,
960 .start = DA8XX_DMA_SPI0_TX,
961 .end = DA8XX_DMA_SPI0_TX,
962 .flags = IORESOURCE_DMA,
966 static struct resource da8xx_spi1_resources[] = {
968 .start = DA830_SPI1_BASE,
969 .end = DA830_SPI1_BASE + SZ_4K - 1,
970 .flags = IORESOURCE_MEM,
973 .start = IRQ_DA8XX_SPINT1,
974 .end = IRQ_DA8XX_SPINT1,
975 .flags = IORESOURCE_IRQ,
978 .start = DA8XX_DMA_SPI1_RX,
979 .end = DA8XX_DMA_SPI1_RX,
980 .flags = IORESOURCE_DMA,
983 .start = DA8XX_DMA_SPI1_TX,
984 .end = DA8XX_DMA_SPI1_TX,
985 .flags = IORESOURCE_DMA,
989 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
991 .version = SPI_VERSION_2,
993 .dma_event_q = EVENTQ_0,
994 .prescaler_limit = 2,
997 .version = SPI_VERSION_2,
999 .dma_event_q = EVENTQ_0,
1000 .prescaler_limit = 2,
1004 static struct platform_device da8xx_spi_device[] = {
1006 .name = "spi_davinci",
1008 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1009 .resource = da8xx_spi0_resources,
1011 .platform_data = &da8xx_spi_pdata[0],
1015 .name = "spi_davinci",
1017 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1018 .resource = da8xx_spi1_resources,
1020 .platform_data = &da8xx_spi_pdata[1],
1025 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1027 if (instance < 0 || instance > 1)
1030 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1032 if (instance == 1 && cpu_is_davinci_da850()) {
1033 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1034 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1037 return platform_device_register(&da8xx_spi_device[instance]);
1040 #ifdef CONFIG_ARCH_DAVINCI_DA850
1041 static struct resource da850_sata_resources[] = {
1043 .start = DA850_SATA_BASE,
1044 .end = DA850_SATA_BASE + 0x1fff,
1045 .flags = IORESOURCE_MEM,
1048 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1049 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1050 .flags = IORESOURCE_MEM,
1053 .start = IRQ_DA850_SATAINT,
1054 .flags = IORESOURCE_IRQ,
1058 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1060 static struct platform_device da850_sata_device = {
1061 .name = "ahci_da850",
1064 .dma_mask = &da850_sata_dmamask,
1065 .coherent_dma_mask = DMA_BIT_MASK(32),
1067 .num_resources = ARRAY_SIZE(da850_sata_resources),
1068 .resource = da850_sata_resources,
1071 int __init da850_register_sata(unsigned long refclkpn)
1073 /* please see comment in drivers/ata/ahci_da850.c */
1074 BUG_ON(refclkpn != 100 * 1000 * 1000);
1076 return platform_device_register(&da850_sata_device);