arch/arm/mach-davinci/devices-da8xx.c

   1 /*
   2  * DA8XX/OMAP L1XX platform device data
   3  *
   4  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
   5  * Derived from code that was:
   6  *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #include <linux/ahci_platform.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/dma-contiguous.h>
  18 #include <linux/dmaengine.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reboot.h>
  22 #include <linux/serial_8250.h>
  23
  24 #include <mach/common.h>
  25 #include <mach/cputype.h>
  26 #include <mach/da8xx.h>
  27 #include <mach/time.h>
  28
  29 #include "asp.h"
  30 #include "cpuidle.h"
  31 #include "sram.h"
  32
  33 #define DA8XX_TPCC_BASE                 0x01c00000
  34 #define DA8XX_TPTC0_BASE                0x01c08000
  35 #define DA8XX_TPTC1_BASE                0x01c08400
  36 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  37 #define DA8XX_I2C0_BASE                 0x01c22000
  38 #define DA8XX_RTC_BASE                  0x01c23000
  39 #define DA8XX_PRUSS_MEM_BASE            0x01c30000
  40 #define DA8XX_MMCSD0_BASE               0x01c40000
  41 #define DA8XX_SPI0_BASE                 0x01c41000
  42 #define DA830_SPI1_BASE                 0x01e12000
  43 #define DA8XX_LCD_CNTRL_BASE            0x01e13000
  44 #define DA850_SATA_BASE                 0x01e18000
  45 #define DA850_MMCSD1_BASE               0x01e1b000
  46 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
  47 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
  48 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
  49 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
  50 #define DA8XX_I2C1_BASE                 0x01e28000
  51 #define DA850_TPCC1_BASE                0x01e30000
  52 #define DA850_TPTC2_BASE                0x01e38000
  53 #define DA850_SPI1_BASE                 0x01f0e000
  54 #define DA8XX_DDR2_CTL_BASE             0xb0000000
  55
  56 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
  57 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
  58 #define DA8XX_EMAC_RAM_OFFSET           0x0000
  59 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
  60
  61 void __iomem *da8xx_syscfg0_base;
  62 void __iomem *da8xx_syscfg1_base;
  63
  64 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
  65         {
  66                 .mapbase        = DA8XX_UART0_BASE,
  67                 .irq            = IRQ_DA8XX_UARTINT0,
  68                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  69                                         UPF_IOREMAP,
  70                 .iotype         = UPIO_MEM,
  71                 .regshift       = 2,
  72         },
  73         {
  74                 .flags  = 0,
  75         }
  76 };
  77 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
  78         {
  79                 .mapbase        = DA8XX_UART1_BASE,
  80                 .irq            = IRQ_DA8XX_UARTINT1,
  81                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  82                                         UPF_IOREMAP,
  83                 .iotype         = UPIO_MEM,
  84                 .regshift       = 2,
  85         },
  86         {
  87                 .flags  = 0,
  88         }
  89 };
  90 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
  91         {
  92                 .mapbase        = DA8XX_UART2_BASE,
  93                 .irq            = IRQ_DA8XX_UARTINT2,
  94                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  95                                         UPF_IOREMAP,
  96                 .iotype         = UPIO_MEM,
  97                 .regshift       = 2,
  98         },
  99         {
 100                 .flags  = 0,
 101         }
 102 };
 103
 104 struct platform_device da8xx_serial_device[] = {
 105         {
 106                 .name   = "serial8250",
 107                 .id     = PLAT8250_DEV_PLATFORM,
 108                 .dev    = {
 109                         .platform_data  = da8xx_serial0_pdata,
 110                 }
 111         },
 112         {
 113                 .name   = "serial8250",
 114                 .id     = PLAT8250_DEV_PLATFORM1,
 115                 .dev    = {
 116                         .platform_data  = da8xx_serial1_pdata,
 117                 }
 118         },
 119         {
 120                 .name   = "serial8250",
 121                 .id     = PLAT8250_DEV_PLATFORM2,
 122                 .dev    = {
 123                         .platform_data  = da8xx_serial2_pdata,
 124                 }
 125         },
 126         {
 127         }
 128 };
 129
 130 static s8 da8xx_queue_priority_mapping[][2] = {
 131         /* {event queue no, Priority} */
 132         {0, 3},
 133         {1, 7},
 134         {-1, -1}
 135 };
 136
 137 static s8 da850_queue_priority_mapping[][2] = {
 138         /* {event queue no, Priority} */
 139         {0, 3},
 140         {-1, -1}
 141 };
 142
 143 static struct edma_soc_info da8xx_edma0_pdata = {
 144         .queue_priority_mapping = da8xx_queue_priority_mapping,
 145         .default_queue          = EVENTQ_1,
 146 };
 147
 148 static struct edma_soc_info da850_edma1_pdata = {
 149         .queue_priority_mapping = da850_queue_priority_mapping,
 150         .default_queue          = EVENTQ_0,
 151 };
 152
 153 static struct resource da8xx_edma0_resources[] = {
 154         {
 155                 .name   = "edma3_cc",
 156                 .start  = DA8XX_TPCC_BASE,
 157                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 158                 .flags  = IORESOURCE_MEM,
 159         },
 160         {
 161                 .name   = "edma3_tc0",
 162                 .start  = DA8XX_TPTC0_BASE,
 163                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 164                 .flags  = IORESOURCE_MEM,
 165         },
 166         {
 167                 .name   = "edma3_tc1",
 168                 .start  = DA8XX_TPTC1_BASE,
 169                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         {
 173                 .name   = "edma3_ccint",
 174                 .start  = IRQ_DA8XX_CCINT0,
 175                 .flags  = IORESOURCE_IRQ,
 176         },
 177         {
 178                 .name   = "edma3_ccerrint",
 179                 .start  = IRQ_DA8XX_CCERRINT,
 180                 .flags  = IORESOURCE_IRQ,
 181         },
 182 };
 183
 184 static struct resource da850_edma1_resources[] = {
 185         {
 186                 .name   = "edma3_cc",
 187                 .start  = DA850_TPCC1_BASE,
 188                 .end    = DA850_TPCC1_BASE + SZ_32K - 1,
 189                 .flags  = IORESOURCE_MEM,
 190         },
 191         {
 192                 .name   = "edma3_tc0",
 193                 .start  = DA850_TPTC2_BASE,
 194                 .end    = DA850_TPTC2_BASE + SZ_1K - 1,
 195                 .flags  = IORESOURCE_MEM,
 196         },
 197         {
 198                 .name   = "edma3_ccint",
 199                 .start  = IRQ_DA850_CCINT1,
 200                 .flags  = IORESOURCE_IRQ,
 201         },
 202         {
 203                 .name   = "edma3_ccerrint",
 204                 .start  = IRQ_DA850_CCERRINT1,
 205                 .flags  = IORESOURCE_IRQ,
 206         },
 207 };
 208
 209 static const struct platform_device_info da8xx_edma0_device __initconst = {
 210         .name           = "edma",
 211         .id             = 0,
 212         .dma_mask       = DMA_BIT_MASK(32),
 213         .res            = da8xx_edma0_resources,
 214         .num_res        = ARRAY_SIZE(da8xx_edma0_resources),
 215         .data           = &da8xx_edma0_pdata,
 216         .size_data      = sizeof(da8xx_edma0_pdata),
 217 };
 218
 219 static const struct platform_device_info da850_edma1_device __initconst = {
 220         .name           = "edma",
 221         .id             = 1,
 222         .dma_mask       = DMA_BIT_MASK(32),
 223         .res            = da850_edma1_resources,
 224         .num_res        = ARRAY_SIZE(da850_edma1_resources),
 225         .data           = &da850_edma1_pdata,
 226         .size_data      = sizeof(da850_edma1_pdata),
 227 };
 228
 229 static const struct dma_slave_map da830_edma_map[] = {
 230         { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
 231         { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
 232         { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
 233         { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
 234         { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
 235         { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
 236         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
 237         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
 238         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
 239         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
 240         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
 241         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
 242 };
 243
 244 int __init da830_register_edma(struct edma_rsv_info *rsv)
 245 {
 246         struct platform_device *edma_pdev;
 247
 248         da8xx_edma0_pdata.rsv = rsv;
 249
 250         da8xx_edma0_pdata.slave_map = da830_edma_map;
 251         da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
 252
 253         edma_pdev = platform_device_register_full(&da8xx_edma0_device);
 254         return PTR_ERR_OR_ZERO(edma_pdev);
 255 }
 256
 257 static const struct dma_slave_map da850_edma0_map[] = {
 258         { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
 259         { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
 260         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
 261         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
 262         { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
 263         { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
 264         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
 265         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
 266         { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
 267         { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
 268         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
 269         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
 270 };
 271
 272 static const struct dma_slave_map da850_edma1_map[] = {
 273         { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
 274         { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
 275 };
 276
 277 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
 278 {
 279         struct platform_device *edma_pdev;
 280
 281         if (rsv) {
 282                 da8xx_edma0_pdata.rsv = rsv[0];
 283                 da850_edma1_pdata.rsv = rsv[1];
 284         }
 285
 286         da8xx_edma0_pdata.slave_map = da850_edma0_map;
 287         da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
 288
 289         edma_pdev = platform_device_register_full(&da8xx_edma0_device);
 290         if (IS_ERR(edma_pdev)) {
 291                 pr_warn("%s: Failed to register eDMA0\n", __func__);
 292                 return PTR_ERR(edma_pdev);
 293         }
 294
 295         da850_edma1_pdata.slave_map = da850_edma1_map;
 296         da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
 297
 298         edma_pdev = platform_device_register_full(&da850_edma1_device);
 299         return PTR_ERR_OR_ZERO(edma_pdev);
 300 }
 301
 302 static struct resource da8xx_i2c_resources0[] = {
 303         {
 304                 .start  = DA8XX_I2C0_BASE,
 305                 .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
 306                 .flags  = IORESOURCE_MEM,
 307         },
 308         {
 309                 .start  = IRQ_DA8XX_I2CINT0,
 310                 .end    = IRQ_DA8XX_I2CINT0,
 311                 .flags  = IORESOURCE_IRQ,
 312         },
 313 };
 314
 315 static struct platform_device da8xx_i2c_device0 = {
 316         .name           = "i2c_davinci",
 317         .id             = 1,
 318         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
 319         .resource       = da8xx_i2c_resources0,
 320 };
 321
 322 static struct resource da8xx_i2c_resources1[] = {
 323         {
 324                 .start  = DA8XX_I2C1_BASE,
 325                 .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
 326                 .flags  = IORESOURCE_MEM,
 327         },
 328         {
 329                 .start  = IRQ_DA8XX_I2CINT1,
 330                 .end    = IRQ_DA8XX_I2CINT1,
 331                 .flags  = IORESOURCE_IRQ,
 332         },
 333 };
 334
 335 static struct platform_device da8xx_i2c_device1 = {
 336         .name           = "i2c_davinci",
 337         .id             = 2,
 338         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
 339         .resource       = da8xx_i2c_resources1,
 340 };
 341
 342 int __init da8xx_register_i2c(int instance,
 343                 struct davinci_i2c_platform_data *pdata)
 344 {
 345         struct platform_device *pdev;
 346
 347         if (instance == 0)
 348                 pdev = &da8xx_i2c_device0;
 349         else if (instance == 1)
 350                 pdev = &da8xx_i2c_device1;
 351         else
 352                 return -EINVAL;
 353
 354         pdev->dev.platform_data = pdata;
 355         return platform_device_register(pdev);
 356 }
 357
 358 static struct resource da8xx_watchdog_resources[] = {
 359         {
 360                 .start  = DA8XX_WDOG_BASE,
 361                 .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
 362                 .flags  = IORESOURCE_MEM,
 363         },
 364 };
 365
 366 static struct platform_device da8xx_wdt_device = {
 367         .name           = "davinci-wdt",
 368         .id             = -1,
 369         .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
 370         .resource       = da8xx_watchdog_resources,
 371 };
 372
 373 int __init da8xx_register_watchdog(void)
 374 {
 375         return platform_device_register(&da8xx_wdt_device);
 376 }
 377
 378 static struct resource da8xx_emac_resources[] = {
 379         {
 380                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
 381                 .end    = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
 382                 .flags  = IORESOURCE_MEM,
 383         },
 384         {
 385                 .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 386                 .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 387                 .flags  = IORESOURCE_IRQ,
 388         },
 389         {
 390                 .start  = IRQ_DA8XX_C0_RX_PULSE,
 391                 .end    = IRQ_DA8XX_C0_RX_PULSE,
 392                 .flags  = IORESOURCE_IRQ,
 393         },
 394         {
 395                 .start  = IRQ_DA8XX_C0_TX_PULSE,
 396                 .end    = IRQ_DA8XX_C0_TX_PULSE,
 397                 .flags  = IORESOURCE_IRQ,
 398         },
 399         {
 400                 .start  = IRQ_DA8XX_C0_MISC_PULSE,
 401                 .end    = IRQ_DA8XX_C0_MISC_PULSE,
 402                 .flags  = IORESOURCE_IRQ,
 403         },
 404 };
 405
 406 struct emac_platform_data da8xx_emac_pdata = {
 407         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
 408         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
 409         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
 410         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
 411         .version                = EMAC_VERSION_2,
 412 };
 413
 414 static struct platform_device da8xx_emac_device = {
 415         .name           = "davinci_emac",
 416         .id             = 1,
 417         .dev = {
 418                 .platform_data  = &da8xx_emac_pdata,
 419         },
 420         .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
 421         .resource       = da8xx_emac_resources,
 422 };
 423
 424 static struct resource da8xx_mdio_resources[] = {
 425         {
 426                 .start  = DA8XX_EMAC_MDIO_BASE,
 427                 .end    = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
 428                 .flags  = IORESOURCE_MEM,
 429         },
 430 };
 431
 432 static struct platform_device da8xx_mdio_device = {
 433         .name           = "davinci_mdio",
 434         .id             = 0,
 435         .num_resources  = ARRAY_SIZE(da8xx_mdio_resources),
 436         .resource       = da8xx_mdio_resources,
 437 };
 438
 439 int __init da8xx_register_emac(void)
 440 {
 441         int ret;
 442
 443         ret = platform_device_register(&da8xx_mdio_device);
 444         if (ret < 0)
 445                 return ret;
 446
 447         return platform_device_register(&da8xx_emac_device);
 448 }
 449
 450 static struct resource da830_mcasp1_resources[] = {
 451         {
 452                 .name   = "mpu",
 453                 .start  = DAVINCI_DA830_MCASP1_REG_BASE,
 454                 .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
 455                 .flags  = IORESOURCE_MEM,
 456         },
 457         /* TX event */
 458         {
 459                 .name   = "tx",
 460                 .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 461                 .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 462                 .flags  = IORESOURCE_DMA,
 463         },
 464         /* RX event */
 465         {
 466                 .name   = "rx",
 467                 .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
 468                 .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
 469                 .flags  = IORESOURCE_DMA,
 470         },
 471         {
 472                 .name   = "common",
 473                 .start  = IRQ_DA8XX_MCASPINT,
 474                 .flags  = IORESOURCE_IRQ,
 475         },
 476 };
 477
 478 static struct platform_device da830_mcasp1_device = {
 479         .name           = "davinci-mcasp",
 480         .id             = 1,
 481         .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
 482         .resource       = da830_mcasp1_resources,
 483 };
 484
 485 static struct resource da830_mcasp2_resources[] = {
 486         {
 487                 .name   = "mpu",
 488                 .start  = DAVINCI_DA830_MCASP2_REG_BASE,
 489                 .end    = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
 490                 .flags  = IORESOURCE_MEM,
 491         },
 492         /* TX event */
 493         {
 494                 .name   = "tx",
 495                 .start  = DAVINCI_DA830_DMA_MCASP2_AXEVT,
 496                 .end    = DAVINCI_DA830_DMA_MCASP2_AXEVT,
 497                 .flags  = IORESOURCE_DMA,
 498         },
 499         /* RX event */
 500         {
 501                 .name   = "rx",
 502                 .start  = DAVINCI_DA830_DMA_MCASP2_AREVT,
 503                 .end    = DAVINCI_DA830_DMA_MCASP2_AREVT,
 504                 .flags  = IORESOURCE_DMA,
 505         },
 506         {
 507                 .name   = "common",
 508                 .start  = IRQ_DA8XX_MCASPINT,
 509                 .flags  = IORESOURCE_IRQ,
 510         },
 511 };
 512
 513 static struct platform_device da830_mcasp2_device = {
 514         .name           = "davinci-mcasp",
 515         .id             = 2,
 516         .num_resources  = ARRAY_SIZE(da830_mcasp2_resources),
 517         .resource       = da830_mcasp2_resources,
 518 };
 519
 520 static struct resource da850_mcasp_resources[] = {
 521         {
 522                 .name   = "mpu",
 523                 .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
 524                 .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
 525                 .flags  = IORESOURCE_MEM,
 526         },
 527         /* TX event */
 528         {
 529                 .name   = "tx",
 530                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 531                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 532                 .flags  = IORESOURCE_DMA,
 533         },
 534         /* RX event */
 535         {
 536                 .name   = "rx",
 537                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 538                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 539                 .flags  = IORESOURCE_DMA,
 540         },
 541         {
 542                 .name   = "common",
 543                 .start  = IRQ_DA8XX_MCASPINT,
 544                 .flags  = IORESOURCE_IRQ,
 545         },
 546 };
 547
 548 static struct platform_device da850_mcasp_device = {
 549         .name           = "davinci-mcasp",
 550         .id             = 0,
 551         .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
 552         .resource       = da850_mcasp_resources,
 553 };
 554
 555 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 556 {
 557         struct platform_device *pdev;
 558
 559         switch (id) {
 560         case 0:
 561                 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
 562                 pdev = &da850_mcasp_device;
 563                 break;
 564         case 1:
 565                 /* Valid for DA830/OMAP-L137 only */
 566                 if (!cpu_is_davinci_da830())
 567                         return;
 568                 pdev = &da830_mcasp1_device;
 569                 break;
 570         case 2:
 571                 /* Valid for DA830/OMAP-L137 only */
 572                 if (!cpu_is_davinci_da830())
 573                         return;
 574                 pdev = &da830_mcasp2_device;
 575                 break;
 576         default:
 577                 return;
 578         }
 579
 580         pdev->dev.platform_data = pdata;
 581         platform_device_register(pdev);
 582 }
 583
 584 static struct resource da8xx_pruss_resources[] = {
 585         {
 586                 .start  = DA8XX_PRUSS_MEM_BASE,
 587                 .end    = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
 588                 .flags  = IORESOURCE_MEM,
 589         },
 590         {
 591                 .start  = IRQ_DA8XX_EVTOUT0,
 592                 .end    = IRQ_DA8XX_EVTOUT0,
 593                 .flags  = IORESOURCE_IRQ,
 594         },
 595         {
 596                 .start  = IRQ_DA8XX_EVTOUT1,
 597                 .end    = IRQ_DA8XX_EVTOUT1,
 598                 .flags  = IORESOURCE_IRQ,
 599         },
 600         {
 601                 .start  = IRQ_DA8XX_EVTOUT2,
 602                 .end    = IRQ_DA8XX_EVTOUT2,
 603                 .flags  = IORESOURCE_IRQ,
 604         },
 605         {
 606                 .start  = IRQ_DA8XX_EVTOUT3,
 607                 .end    = IRQ_DA8XX_EVTOUT3,
 608                 .flags  = IORESOURCE_IRQ,
 609         },
 610         {
 611                 .start  = IRQ_DA8XX_EVTOUT4,
 612                 .end    = IRQ_DA8XX_EVTOUT4,
 613                 .flags  = IORESOURCE_IRQ,
 614         },
 615         {
 616                 .start  = IRQ_DA8XX_EVTOUT5,
 617                 .end    = IRQ_DA8XX_EVTOUT5,
 618                 .flags  = IORESOURCE_IRQ,
 619         },
 620         {
 621                 .start  = IRQ_DA8XX_EVTOUT6,
 622                 .end    = IRQ_DA8XX_EVTOUT6,
 623                 .flags  = IORESOURCE_IRQ,
 624         },
 625         {
 626                 .start  = IRQ_DA8XX_EVTOUT7,
 627                 .end    = IRQ_DA8XX_EVTOUT7,
 628                 .flags  = IORESOURCE_IRQ,
 629         },
 630 };
 631
 632 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
 633         .pintc_base     = 0x4000,
 634 };
 635
 636 static struct platform_device da8xx_uio_pruss_dev = {
 637         .name           = "pruss_uio",
 638         .id             = -1,
 639         .num_resources  = ARRAY_SIZE(da8xx_pruss_resources),
 640         .resource       = da8xx_pruss_resources,
 641         .dev            = {
 642                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 643                 .platform_data          = &da8xx_uio_pruss_pdata,
 644         }
 645 };
 646
 647 int __init da8xx_register_uio_pruss(void)
 648 {
 649         da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
 650         return platform_device_register(&da8xx_uio_pruss_dev);
 651 }
 652
 653 static struct lcd_ctrl_config lcd_cfg = {
 654         .panel_shade            = COLOR_ACTIVE,
 655         .bpp                    = 16,
 656 };
 657
 658 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
 659         .manu_name              = "sharp",
 660         .controller_data        = &lcd_cfg,
 661         .type                   = "Sharp_LCD035Q3DG01",
 662 };
 663
 664 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
 665         .manu_name              = "sharp",
 666         .controller_data        = &lcd_cfg,
 667         .type                   = "Sharp_LK043T1DG01",
 668 };
 669
 670 static struct resource da8xx_lcdc_resources[] = {
 671         [0] = { /* registers */
 672                 .start  = DA8XX_LCD_CNTRL_BASE,
 673                 .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
 674                 .flags  = IORESOURCE_MEM,
 675         },
 676         [1] = { /* interrupt */
 677                 .start  = IRQ_DA8XX_LCDINT,
 678                 .end    = IRQ_DA8XX_LCDINT,
 679                 .flags  = IORESOURCE_IRQ,
 680         },
 681 };
 682
 683 static struct platform_device da8xx_lcdc_device = {
 684         .name           = "da8xx_lcdc",
 685         .id             = 0,
 686         .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
 687         .resource       = da8xx_lcdc_resources,
 688         .dev            = {
 689                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 690         }
 691 };
 692
 693 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 694 {
 695         da8xx_lcdc_device.dev.platform_data = pdata;
 696         return platform_device_register(&da8xx_lcdc_device);
 697 }
 698
 699 static struct resource da8xx_gpio_resources[] = {
 700         { /* registers */
 701                 .start  = DA8XX_GPIO_BASE,
 702                 .end    = DA8XX_GPIO_BASE + SZ_4K - 1,
 703                 .flags  = IORESOURCE_MEM,
 704         },
 705         { /* interrupt */
 706                 .start  = IRQ_DA8XX_GPIO0,
 707                 .end    = IRQ_DA8XX_GPIO0,
 708                 .flags  = IORESOURCE_IRQ,
 709         },
 710         {
 711                 .start  = IRQ_DA8XX_GPIO1,
 712                 .end    = IRQ_DA8XX_GPIO1,
 713                 .flags  = IORESOURCE_IRQ,
 714         },
 715         {
 716                 .start  = IRQ_DA8XX_GPIO2,
 717                 .end    = IRQ_DA8XX_GPIO2,
 718                 .flags  = IORESOURCE_IRQ,
 719         },
 720         {
 721                 .start  = IRQ_DA8XX_GPIO3,
 722                 .end    = IRQ_DA8XX_GPIO3,
 723                 .flags  = IORESOURCE_IRQ,
 724         },
 725         {
 726                 .start  = IRQ_DA8XX_GPIO4,
 727                 .end    = IRQ_DA8XX_GPIO4,
 728                 .flags  = IORESOURCE_IRQ,
 729         },
 730         {
 731                 .start  = IRQ_DA8XX_GPIO5,
 732                 .end    = IRQ_DA8XX_GPIO5,
 733                 .flags  = IORESOURCE_IRQ,
 734         },
 735         {
 736                 .start  = IRQ_DA8XX_GPIO6,
 737                 .end    = IRQ_DA8XX_GPIO6,
 738                 .flags  = IORESOURCE_IRQ,
 739         },
 740         {
 741                 .start  = IRQ_DA8XX_GPIO7,
 742                 .end    = IRQ_DA8XX_GPIO7,
 743                 .flags  = IORESOURCE_IRQ,
 744         },
 745         {
 746                 .start  = IRQ_DA8XX_GPIO8,
 747                 .end    = IRQ_DA8XX_GPIO8,
 748                 .flags  = IORESOURCE_IRQ,
 749         },
 750 };
 751
 752 static struct platform_device da8xx_gpio_device = {
 753         .name           = "davinci_gpio",
 754         .id             = -1,
 755         .num_resources  = ARRAY_SIZE(da8xx_gpio_resources),
 756         .resource       = da8xx_gpio_resources,
 757 };
 758
 759 int __init da8xx_register_gpio(void *pdata)
 760 {
 761         da8xx_gpio_device.dev.platform_data = pdata;
 762         return platform_device_register(&da8xx_gpio_device);
 763 }
 764
 765 static struct resource da8xx_mmcsd0_resources[] = {
 766         {               /* registers */
 767                 .start  = DA8XX_MMCSD0_BASE,
 768                 .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
 769                 .flags  = IORESOURCE_MEM,
 770         },
 771         {               /* interrupt */
 772                 .start  = IRQ_DA8XX_MMCSDINT0,
 773                 .end    = IRQ_DA8XX_MMCSDINT0,
 774                 .flags  = IORESOURCE_IRQ,
 775         },
 776 };
 777
 778 static struct platform_device da8xx_mmcsd0_device = {
 779         .name           = "da830-mmc",
 780         .id             = 0,
 781         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
 782         .resource       = da8xx_mmcsd0_resources,
 783 };
 784
 785 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
 786 {
 787         da8xx_mmcsd0_device.dev.platform_data = config;
 788         return platform_device_register(&da8xx_mmcsd0_device);
 789 }
 790
 791 #ifdef CONFIG_ARCH_DAVINCI_DA850
 792 static struct resource da850_mmcsd1_resources[] = {
 793         {               /* registers */
 794                 .start  = DA850_MMCSD1_BASE,
 795                 .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
 796                 .flags  = IORESOURCE_MEM,
 797         },
 798         {               /* interrupt */
 799                 .start  = IRQ_DA850_MMCSDINT0_1,
 800                 .end    = IRQ_DA850_MMCSDINT0_1,
 801                 .flags  = IORESOURCE_IRQ,
 802         },
 803 };
 804
 805 static struct platform_device da850_mmcsd1_device = {
 806         .name           = "da830-mmc",
 807         .id             = 1,
 808         .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
 809         .resource       = da850_mmcsd1_resources,
 810 };
 811
 812 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
 813 {
 814         da850_mmcsd1_device.dev.platform_data = config;
 815         return platform_device_register(&da850_mmcsd1_device);
 816 }
 817 #endif
 818
 819 static struct resource da8xx_rproc_resources[] = {
 820         { /* DSP boot address */
 821                 .name           = "host1cfg",
 822                 .start          = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
 823                 .end            = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
 824                 .flags          = IORESOURCE_MEM,
 825         },
 826         { /* DSP interrupt registers */
 827                 .name           = "chipsig",
 828                 .start          = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
 829                 .end            = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
 830                 .flags          = IORESOURCE_MEM,
 831         },
 832         { /* DSP L2 RAM */
 833                 .name           = "l2sram",
 834                 .start          = DA8XX_DSP_L2_RAM_BASE,
 835                 .end            = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
 836                 .flags          = IORESOURCE_MEM,
 837         },
 838         { /* DSP L1P RAM */
 839                 .name           = "l1pram",
 840                 .start          = DA8XX_DSP_L1P_RAM_BASE,
 841                 .end            = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
 842                 .flags          = IORESOURCE_MEM,
 843         },
 844         { /* DSP L1D RAM */
 845                 .name           = "l1dram",
 846                 .start          = DA8XX_DSP_L1D_RAM_BASE,
 847                 .end            = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
 848                 .flags          = IORESOURCE_MEM,
 849         },
 850         { /* dsp irq */
 851                 .start          = IRQ_DA8XX_CHIPINT0,
 852                 .end            = IRQ_DA8XX_CHIPINT0,
 853                 .flags          = IORESOURCE_IRQ,
 854         },
 855 };
 856
 857 static struct platform_device da8xx_dsp = {
 858         .name   = "davinci-rproc",
 859         .dev    = {
 860                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 861         },
 862         .num_resources  = ARRAY_SIZE(da8xx_rproc_resources),
 863         .resource       = da8xx_rproc_resources,
 864 };
 865
 866 static bool rproc_mem_inited __initdata;
 867
 868 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
 869
 870 static phys_addr_t rproc_base __initdata;
 871 static unsigned long rproc_size __initdata;
 872
 873 static int __init early_rproc_mem(char *p)
 874 {
 875         char *endp;
 876
 877         if (p == NULL)
 878                 return 0;
 879
 880         rproc_size = memparse(p, &endp);
 881         if (*endp == '@')
 882                 rproc_base = memparse(endp + 1, NULL);
 883
 884         return 0;
 885 }
 886 early_param("rproc_mem", early_rproc_mem);
 887
 888 void __init da8xx_rproc_reserve_cma(void)
 889 {
 890         int ret;
 891
 892         if (!rproc_base || !rproc_size) {
 893                 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
 894                        "    'nn' and 'address' must both be non-zero\n",
 895                        __func__);
 896
 897                 return;
 898         }
 899
 900         pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
 901                 __func__, rproc_size, (unsigned long)rproc_base);
 902
 903         ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
 904         if (ret)
 905                 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
 906         else
 907                 rproc_mem_inited = true;
 908 }
 909
 910 #else
 911
 912 void __init da8xx_rproc_reserve_cma(void)
 913 {
 914 }
 915
 916 #endif
 917
 918 int __init da8xx_register_rproc(void)
 919 {
 920         int ret;
 921
 922         if (!rproc_mem_inited) {
 923                 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
 924                         __func__);
 925                 return -ENOMEM;
 926         }
 927
 928         ret = platform_device_register(&da8xx_dsp);
 929         if (ret)
 930                 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
 931
 932         return ret;
 933 };
 934
 935 static struct resource da8xx_rtc_resources[] = {
 936         {
 937                 .start          = DA8XX_RTC_BASE,
 938                 .end            = DA8XX_RTC_BASE + SZ_4K - 1,
 939                 .flags          = IORESOURCE_MEM,
 940         },
 941         { /* timer irq */
 942                 .start          = IRQ_DA8XX_RTC,
 943                 .end            = IRQ_DA8XX_RTC,
 944                 .flags          = IORESOURCE_IRQ,
 945         },
 946         { /* alarm irq */
 947                 .start          = IRQ_DA8XX_RTC,
 948                 .end            = IRQ_DA8XX_RTC,
 949                 .flags          = IORESOURCE_IRQ,
 950         },
 951 };
 952
 953 static struct platform_device da8xx_rtc_device = {
 954         .name           = "da830-rtc",
 955         .id             = -1,
 956         .num_resources  = ARRAY_SIZE(da8xx_rtc_resources),
 957         .resource       = da8xx_rtc_resources,
 958 };
 959
 960 int da8xx_register_rtc(void)
 961 {
 962         return platform_device_register(&da8xx_rtc_device);
 963 }
 964
 965 static void __iomem *da8xx_ddr2_ctlr_base;
 966 void __iomem * __init da8xx_get_mem_ctlr(void)
 967 {
 968         if (da8xx_ddr2_ctlr_base)
 969                 return da8xx_ddr2_ctlr_base;
 970
 971         da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
 972         if (!da8xx_ddr2_ctlr_base)
 973                 pr_warn("%s: Unable to map DDR2 controller", __func__);
 974
 975         return da8xx_ddr2_ctlr_base;
 976 }
 977
 978 static struct resource da8xx_cpuidle_resources[] = {
 979         {
 980                 .start          = DA8XX_DDR2_CTL_BASE,
 981                 .end            = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
 982                 .flags          = IORESOURCE_MEM,
 983         },
 984 };
 985
 986 /* DA8XX devices support DDR2 power down */
 987 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
 988         .ddr2_pdown     = 1,
 989 };
 990
 991
 992 static struct platform_device da8xx_cpuidle_device = {
 993         .name                   = "cpuidle-davinci",
 994         .num_resources          = ARRAY_SIZE(da8xx_cpuidle_resources),
 995         .resource               = da8xx_cpuidle_resources,
 996         .dev = {
 997                 .platform_data  = &da8xx_cpuidle_pdata,
 998         },
 999 };
1000
1001 int __init da8xx_register_cpuidle(void)
1002 {
1003         da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1004
1005         return platform_device_register(&da8xx_cpuidle_device);
1006 }
1007
1008 static struct resource da8xx_spi0_resources[] = {
1009         [0] = {
1010                 .start  = DA8XX_SPI0_BASE,
1011                 .end    = DA8XX_SPI0_BASE + SZ_4K - 1,
1012                 .flags  = IORESOURCE_MEM,
1013         },
1014         [1] = {
1015                 .start  = IRQ_DA8XX_SPINT0,
1016                 .end    = IRQ_DA8XX_SPINT0,
1017                 .flags  = IORESOURCE_IRQ,
1018         },
1019 };
1020
1021 static struct resource da8xx_spi1_resources[] = {
1022         [0] = {
1023                 .start  = DA830_SPI1_BASE,
1024                 .end    = DA830_SPI1_BASE + SZ_4K - 1,
1025                 .flags  = IORESOURCE_MEM,
1026         },
1027         [1] = {
1028                 .start  = IRQ_DA8XX_SPINT1,
1029                 .end    = IRQ_DA8XX_SPINT1,
1030                 .flags  = IORESOURCE_IRQ,
1031         },
1032 };
1033
1034 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1035         [0] = {
1036                 .version        = SPI_VERSION_2,
1037                 .intr_line      = 1,
1038                 .dma_event_q    = EVENTQ_0,
1039                 .prescaler_limit = 2,
1040         },
1041         [1] = {
1042                 .version        = SPI_VERSION_2,
1043                 .intr_line      = 1,
1044                 .dma_event_q    = EVENTQ_0,
1045                 .prescaler_limit = 2,
1046         },
1047 };
1048
1049 static struct platform_device da8xx_spi_device[] = {
1050         [0] = {
1051                 .name           = "spi_davinci",
1052                 .id             = 0,
1053                 .num_resources  = ARRAY_SIZE(da8xx_spi0_resources),
1054                 .resource       = da8xx_spi0_resources,
1055                 .dev            = {
1056                         .platform_data = &da8xx_spi_pdata[0],
1057                 },
1058         },
1059         [1] = {
1060                 .name           = "spi_davinci",
1061                 .id             = 1,
1062                 .num_resources  = ARRAY_SIZE(da8xx_spi1_resources),
1063                 .resource       = da8xx_spi1_resources,
1064                 .dev            = {
1065                         .platform_data = &da8xx_spi_pdata[1],
1066                 },
1067         },
1068 };
1069
1070 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1071 {
1072         if (instance < 0 || instance > 1)
1073                 return -EINVAL;
1074
1075         da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1076
1077         if (instance == 1 && cpu_is_davinci_da850()) {
1078                 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1079                 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1080         }
1081
1082         return platform_device_register(&da8xx_spi_device[instance]);
1083 }
1084
1085 #ifdef CONFIG_ARCH_DAVINCI_DA850
1086 int __init da850_register_sata_refclk(int rate)
1087 {
1088         struct clk *clk;
1089
1090         clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
1091         if (IS_ERR(clk))
1092                 return PTR_ERR(clk);
1093
1094         return clk_register_clkdev(clk, "refclk", "ahci_da850");
1095 }
1096
1097 static struct resource da850_sata_resources[] = {
1098         {
1099                 .start  = DA850_SATA_BASE,
1100                 .end    = DA850_SATA_BASE + 0x1fff,
1101                 .flags  = IORESOURCE_MEM,
1102         },
1103         {
1104                 .start  = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1105                 .end    = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1106                 .flags  = IORESOURCE_MEM,
1107         },
1108         {
1109                 .start  = IRQ_DA850_SATAINT,
1110                 .flags  = IORESOURCE_IRQ,
1111         },
1112 };
1113
1114 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1115
1116 static struct platform_device da850_sata_device = {
1117         .name   = "ahci_da850",
1118         .id     = -1,
1119         .dev    = {
1120                 .dma_mask               = &da850_sata_dmamask,
1121                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1122         },
1123         .num_resources  = ARRAY_SIZE(da850_sata_resources),
1124         .resource       = da850_sata_resources,
1125 };
1126
1127 int __init da850_register_sata(unsigned long refclkpn)
1128 {
1129         int ret;
1130
1131         ret = da850_register_sata_refclk(refclkpn);
1132         if (ret)
1133                 return ret;
1134
1135         return platform_device_register(&da850_sata_device);
1136 }
1137 #endif
1138
1139 static struct regmap *da8xx_cfgchip;
1140
1141 static const struct regmap_config da8xx_cfgchip_config __initconst = {
1142         .name           = "cfgchip",
1143         .reg_bits       = 32,
1144         .val_bits       = 32,
1145         .reg_stride     = 4,
1146         .max_register   = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
1147 };
1148
1149 /**
1150  * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1151  *
1152  * This is for use on non-DT boards only. For DT boards, use
1153  * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1154  *
1155  * Returns: Pointer to the CFGCHIP regmap or negative error code.
1156  */
1157 struct regmap * __init da8xx_get_cfgchip(void)
1158 {
1159         if (IS_ERR_OR_NULL(da8xx_cfgchip))
1160                 da8xx_cfgchip = regmap_init_mmio(NULL,
1161                                         DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1162                                         &da8xx_cfgchip_config);
1163
1164         return da8xx_cfgchip;
1165 }