2 * Neuros Technologies OSD2 board support
4 * Modified from original 644X-EVM board support.
5 * 2008 (c) Neuros Technology, LLC.
6 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
7 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
9 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
10 * Internet Television Platform. Hardware is very close to TI
11 * DM644X-EVM board. It has:
12 * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
13 * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
14 * Additionally realtime clock, IR remote control receiver,
15 * IR Blaster based on MSP430 (firmware although is different
16 * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
17 * with PATA interface, two muxed red-green leds.
19 * For more information please refer to
20 * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
26 #include <linux/platform_device.h>
27 #include <linux/gpio.h>
28 #include <linux/leds.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/platform_data/gpio-davinci.h>
31 #include <linux/platform_data/i2c-davinci.h>
32 #include <linux/platform_data/mmc-davinci.h>
33 #include <linux/platform_data/mtd-davinci.h>
34 #include <linux/platform_data/usb-davinci.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
44 #define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
45 #define LXT971_PHY_ID 0x001378e2
46 #define LXT971_PHY_MASK 0xfffffff0
48 #define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
49 #define NTOSD2_MSP430_I2C_ADDR 0x59
50 #define NTOSD2_MSP430_IRQ 2
52 /* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
53 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
57 #define NAND_BLOCK_SIZE SZ_128K
59 static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
61 /* UBL (a few copies) plus U-Boot */
64 .size = 15 * NAND_BLOCK_SIZE,
65 .mask_flags = MTD_WRITEABLE, /* force read-only */
67 /* U-Boot environment */
69 .offset = MTDPART_OFS_APPEND,
70 .size = 1 * NAND_BLOCK_SIZE,
75 .offset = MTDPART_OFS_APPEND,
81 .offset = MTDPART_OFS_APPEND,
82 .size = MTDPART_SIZ_FULL,
85 /* A few blocks at end hold a flash Bad Block Table. */
88 static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
90 .parts = davinci_ntosd2_nandflash_partition,
91 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
92 .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
94 .bbt_options = NAND_BBT_USE_FLASH,
97 static struct resource davinci_ntosd2_nandflash_resource[] = {
99 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
100 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
101 .flags = IORESOURCE_MEM,
103 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
104 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
105 .flags = IORESOURCE_MEM,
109 static struct platform_device davinci_ntosd2_nandflash_device = {
110 .name = "davinci_nand",
113 .platform_data = &davinci_ntosd2_nandflash_data,
115 .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
116 .resource = davinci_ntosd2_nandflash_resource,
119 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
121 static struct platform_device davinci_fb_device = {
125 .dma_mask = &davinci_fb_dma_mask,
126 .coherent_dma_mask = DMA_BIT_MASK(32),
131 static const struct gpio_led ntosd2_leds[] = {
132 { .name = "led1_green", .gpio = 10, },
133 { .name = "led1_red", .gpio = 11, },
134 { .name = "led2_green", .gpio = 12, },
135 { .name = "led2_red", .gpio = 13, },
138 static struct gpio_led_platform_data ntosd2_leds_data = {
139 .num_leds = ARRAY_SIZE(ntosd2_leds),
143 static struct platform_device ntosd2_leds_dev = {
147 .platform_data = &ntosd2_leds_data,
152 static struct platform_device *davinci_ntosd2_devices[] __initdata = {
157 static void __init davinci_ntosd2_map_io(void)
162 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
166 #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
167 IS_ENABLED(CONFIG_PATA_BK3710))
169 #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
171 static __init void davinci_ntosd2_init(void)
174 struct clk *aemif_clk;
175 struct davinci_soc_info *soc_info = &davinci_soc_info;
177 dm644x_register_clocks();
179 dm644x_init_devices();
181 ret = dm644x_gpio_register();
183 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
185 aemif_clk = clk_get(NULL, "aemif");
186 clk_prepare_enable(aemif_clk);
190 pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
191 "\tDisable IDE for NAND/NOR support\n");
193 } else if (HAS_NAND) {
194 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
195 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
197 /* only one device will be jumpered and detected */
199 platform_device_register(
200 &davinci_ntosd2_nandflash_device);
203 platform_add_devices(davinci_ntosd2_devices,
204 ARRAY_SIZE(davinci_ntosd2_devices));
206 davinci_serial_init(dm644x_serial_device);
209 soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
211 davinci_setup_usb(1000, 8);
213 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
214 * The AEAWx are five new AEAW pins that can be muxed by separately.
215 * They are a bitmask for GPIO management. According TI
216 * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
217 * gpio(10,11,12,13) for leds any combination of bits works except
218 * four last. So we are to reset all five.
220 davinci_cfg_reg(DM644X_AEAW0);
221 davinci_cfg_reg(DM644X_AEAW1);
222 davinci_cfg_reg(DM644X_AEAW2);
223 davinci_cfg_reg(DM644X_AEAW3);
224 davinci_cfg_reg(DM644X_AEAW4);
226 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
229 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
230 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
231 .atag_offset = 0x100,
232 .map_io = davinci_ntosd2_map_io,
233 .init_irq = dm644x_init_irq,
234 .init_time = dm644x_init_time,
235 .init_machine = davinci_ntosd2_init,
236 .init_late = davinci_init_late,
237 .dma_zone_size = SZ_128M,