2 * Critical Link MityOMAP-L138 SoM
4 * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of
8 * any kind, whether express or implied.
11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/console.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/notifier.h>
20 #include <linux/nvmem-consumer.h>
21 #include <linux/nvmem-provider.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/i2c.h>
24 #include <linux/etherdevice.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/flash.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
36 #include <linux/platform_data/mtd-davinci.h>
37 #include <linux/platform_data/mtd-davinci-aemif.h>
38 #include <linux/platform_data/ti-aemif.h>
39 #include <linux/platform_data/spi-davinci.h>
41 #define MITYOMAPL138_PHY_ID ""
43 #define FACTORY_CONFIG_MAGIC 0x012C0138
44 #define FACTORY_CONFIG_VERSION 0x00010001
46 /* Data Held in On-Board I2C device */
47 struct factory_config {
57 static struct factory_config factory_config;
59 #ifdef CONFIG_CPU_FREQ
61 const char *part_no; /* part number string of interest */
62 int max_freq; /* khz */
65 static struct part_no_info mityomapl138_pn_info[] = {
96 static void mityomapl138_cpufreq_init(const char *partnum)
100 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
102 * the part number has additional characters beyond what is
103 * stored in the table. This information is not needed for
104 * determining the speed grade, and would require several
105 * more table entries. Only check the first N characters
108 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
109 strlen(mityomapl138_pn_info[i].part_no))) {
110 da850_max_speed = mityomapl138_pn_info[i].max_freq;
115 ret = da850_register_cpufreq("pll0_sysclk3");
117 pr_warn("cpufreq registration failed: %d\n", ret);
120 static void mityomapl138_cpufreq_init(const char *partnum) { }
123 static int read_factory_config(struct notifier_block *nb,
124 unsigned long event, void *data)
127 const char *partnum = NULL;
128 struct nvmem_device *nvmem = data;
130 if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
133 if (!IS_BUILTIN(CONFIG_NVMEM)) {
134 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
138 ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
140 if (ret != sizeof(struct factory_config)) {
141 pr_warn("Read Factory Config Failed: %d\n", ret);
145 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
146 pr_warn("Factory Config Magic Wrong (%X)\n",
147 factory_config.magic);
151 if (factory_config.version != FACTORY_CONFIG_VERSION) {
152 pr_warn("Factory Config Version Wrong (%X)\n",
153 factory_config.version);
157 partnum = factory_config.partnum;
158 pr_info("Part Number = %s\n", partnum);
161 /* default maximum speed is valid for all platforms */
162 mityomapl138_cpufreq_init(partnum);
167 static struct notifier_block mityomapl138_nvmem_notifier = {
168 .notifier_call = read_factory_config,
172 * We don't define a cell for factory config as it will be accessed from the
173 * board file using the nvmem notifier chain.
175 static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
183 static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
184 .nvmem_name = "1-00500",
185 .cells = mityomapl138_nvmem_cells,
186 .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
189 static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
190 .nvmem_name = "1-00500",
191 .cell_name = "macaddr",
192 .dev_id = "davinci_emac.1",
193 .con_id = "mac-address",
196 static const struct property_entry mityomapl138_fd_chip_properties[] = {
197 PROPERTY_ENTRY_U32("pagesize", 8),
198 PROPERTY_ENTRY_BOOL("read-only"),
202 static const struct software_node mityomapl138_fd_chip_node = {
203 .properties = mityomapl138_fd_chip_properties,
206 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
207 .bus_freq = 100, /* kHz */
208 .bus_delay = 0, /* usec */
211 /* TPS65023 voltage regulator support */
213 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
220 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
222 .supply = "usb0_vdda18",
225 .supply = "usb1_vdda18",
228 .supply = "ddr_dvdd18",
231 .supply = "sata_vddr",
236 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
238 .supply = "sata_vdd",
241 .supply = "usb_cvdd",
244 .supply = "pll0_vdda",
247 .supply = "pll1_vdda",
251 /* 1.8V Aux LDO, not used */
252 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
254 .supply = "1.8v_aux",
258 /* FPGA VCC Aux (2.5 or 3.3) LDO */
259 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
265 static struct regulator_init_data tps65023_regulator_data[] = {
271 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
272 REGULATOR_CHANGE_STATUS,
275 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
276 .consumer_supplies = tps65023_dcdc1_consumers,
283 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
286 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
287 .consumer_supplies = tps65023_dcdc2_consumers,
294 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
297 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
298 .consumer_supplies = tps65023_dcdc3_consumers,
305 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
308 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
309 .consumer_supplies = tps65023_ldo1_consumers,
316 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
317 REGULATOR_CHANGE_STATUS,
320 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
321 .consumer_supplies = tps65023_ldo2_consumers,
325 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
327 I2C_BOARD_INFO("tps65023", 0x48),
328 .platform_data = &tps65023_regulator_data[0],
331 I2C_BOARD_INFO("24c02", 0x50),
332 .swnode = &mityomapl138_fd_chip_node,
336 static int __init pmic_tps65023_init(void)
338 return i2c_register_board_info(1, mityomap_tps65023_info,
339 ARRAY_SIZE(mityomap_tps65023_info));
344 * SPI1_CS0: 8M Flash ST-M25P64-VME6G
346 static struct mtd_partition spi_flash_partitions[] = {
351 .mask_flags = MTD_WRITEABLE,
355 .offset = MTDPART_OFS_APPEND,
357 .mask_flags = MTD_WRITEABLE,
360 .name = "u-boot-env",
361 .offset = MTDPART_OFS_APPEND,
363 .mask_flags = MTD_WRITEABLE,
366 .name = "periph-config",
367 .offset = MTDPART_OFS_APPEND,
369 .mask_flags = MTD_WRITEABLE,
373 .offset = MTDPART_OFS_APPEND,
374 .size = SZ_256K + SZ_64K,
378 .offset = MTDPART_OFS_APPEND,
379 .size = SZ_2M + SZ_1M,
383 .offset = MTDPART_OFS_APPEND,
388 .offset = MTDPART_OFS_APPEND,
389 .size = MTDPART_SIZ_FULL,
393 static struct flash_platform_data mityomapl138_spi_flash_data = {
395 .parts = spi_flash_partitions,
396 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
400 static struct davinci_spi_config spi_eprom_config = {
401 .io_type = SPI_IO_TYPE_DMA,
406 static struct spi_board_info mityomapl138_spi_flash_info[] = {
408 .modalias = "m25p80",
409 .platform_data = &mityomapl138_spi_flash_data,
410 .controller_data = &spi_eprom_config,
412 .max_speed_hz = 30000000,
419 * MityDSP-L138 includes a 256 MByte large-page NAND flash
422 static struct mtd_partition mityomapl138_nandflash_partition[] = {
427 .mask_flags = 0, /* MTD_WRITEABLE, */
431 .offset = MTDPART_OFS_APPEND,
432 .size = MTDPART_SIZ_FULL,
437 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
439 .parts = mityomapl138_nandflash_partition,
440 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
441 .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
442 .bbt_options = NAND_BBT_USE_FLASH,
443 .options = NAND_BUSWIDTH_16,
444 .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
447 static struct resource mityomapl138_nandflash_resource[] = {
449 .start = DA8XX_AEMIF_CS3_BASE,
450 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
451 .flags = IORESOURCE_MEM,
454 .start = DA8XX_AEMIF_CTL_BASE,
455 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
456 .flags = IORESOURCE_MEM,
460 static struct platform_device mityomapl138_aemif_devices[] = {
462 .name = "davinci_nand",
465 .platform_data = &mityomapl138_nandflash_data,
467 .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
468 .resource = mityomapl138_nandflash_resource,
472 static struct resource mityomapl138_aemif_resources[] = {
474 .start = DA8XX_AEMIF_CTL_BASE,
475 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
476 .flags = IORESOURCE_MEM,
480 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
486 static struct aemif_platform_data mityomapl138_aemif_pdata = {
487 .abus_data = mityomapl138_aemif_abus_data,
488 .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
489 .sub_devices = mityomapl138_aemif_devices,
490 .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
493 static struct platform_device mityomapl138_aemif_device = {
497 .platform_data = &mityomapl138_aemif_pdata,
499 .resource = mityomapl138_aemif_resources,
500 .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
503 static void __init mityomapl138_setup_nand(void)
505 if (platform_device_register(&mityomapl138_aemif_device))
506 pr_warn("%s: Cannot register AEMIF device\n", __func__);
509 static const short mityomap_mii_pins[] = {
510 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
511 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
512 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
513 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
518 static const short mityomap_rmii_pins[] = {
519 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
520 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
521 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
526 static void __init mityomapl138_config_emac(void)
528 void __iomem *cfg_chip3_base;
531 struct davinci_soc_info *soc_info = &davinci_soc_info;
533 soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
535 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
536 val = __raw_readl(cfg_chip3_base);
538 if (soc_info->emac_pdata->rmii_en) {
540 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
541 pr_info("RMII PHY configured\n");
544 ret = davinci_cfg_reg_list(mityomap_mii_pins);
545 pr_info("MII PHY configured\n");
549 pr_warn("mii/rmii mux setup failed: %d\n", ret);
553 /* configure the CFGCHIP3 register for RMII or MII */
554 __raw_writel(val, cfg_chip3_base);
556 soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
558 ret = da8xx_register_emac();
560 pr_warn("emac registration failed: %d\n", ret);
563 static void __init mityomapl138_init(void)
567 da850_register_clocks();
569 /* for now, no special EDMA channels are reserved */
570 ret = da850_register_edma(NULL);
572 pr_warn("edma registration failed: %d\n", ret);
574 ret = da8xx_register_watchdog();
576 pr_warn("watchdog registration failed: %d\n", ret);
578 davinci_serial_init(da8xx_serial_device);
580 nvmem_register_notifier(&mityomapl138_nvmem_notifier);
581 nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
582 nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
584 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
586 pr_warn("i2c0 registration failed: %d\n", ret);
588 ret = pmic_tps65023_init();
590 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
592 mityomapl138_setup_nand();
594 ret = spi_register_board_info(mityomapl138_spi_flash_info,
595 ARRAY_SIZE(mityomapl138_spi_flash_info));
597 pr_warn("spi info registration failed: %d\n", ret);
599 ret = da8xx_register_spi_bus(1,
600 ARRAY_SIZE(mityomapl138_spi_flash_info));
602 pr_warn("spi 1 registration failed: %d\n", ret);
604 mityomapl138_config_emac();
606 ret = da8xx_register_rtc();
608 pr_warn("rtc setup failed: %d\n", ret);
610 ret = da8xx_register_cpuidle();
612 pr_warn("cpuidle registration failed: %d\n", ret);
617 #ifdef CONFIG_SERIAL_8250_CONSOLE
618 static int __init mityomapl138_console_init(void)
620 if (!machine_is_mityomapl138())
623 return add_preferred_console("ttyS", 1, "115200");
625 console_initcall(mityomapl138_console_init);
628 static void __init mityomapl138_map_io(void)
633 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
634 .atag_offset = 0x100,
635 .map_io = mityomapl138_map_io,
636 .init_irq = da850_init_irq,
637 .init_time = da850_init_time,
638 .init_machine = mityomapl138_init,
639 .init_late = davinci_init_late,
640 .dma_zone_size = SZ_128M,