arch/arm/mach-davinci/board-mityomapl138.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Critical Link MityOMAP-L138 SoM
   4  *
   5  * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
   6  */
   7
   8 #define pr_fmt(fmt) "MityOMAPL138: " fmt
   9
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/console.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/property.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/notifier.h>
  17 #include <linux/nvmem-consumer.h>
  18 #include <linux/nvmem-provider.h>
  19 #include <linux/regulator/machine.h>
  20 #include <linux/i2c.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/flash.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28
  29 #include "common.h"
  30 #include "da8xx.h"
  31 #include "mux.h"
  32
  33 #include <linux/platform_data/mtd-davinci.h>
  34 #include <linux/platform_data/mtd-davinci-aemif.h>
  35 #include <linux/platform_data/ti-aemif.h>
  36 #include <linux/platform_data/spi-davinci.h>
  37
  38 #define MITYOMAPL138_PHY_ID             ""
  39
  40 #define FACTORY_CONFIG_MAGIC    0x012C0138
  41 #define FACTORY_CONFIG_VERSION  0x00010001
  42
  43 /* Data Held in On-Board I2C device */
  44 struct factory_config {
  45         u32     magic;
  46         u32     version;
  47         u8      mac[6];
  48         u32     fpga_type;
  49         u32     spare;
  50         u32     serialnumber;
  51         char    partnum[32];
  52 };
  53
  54 static struct factory_config factory_config;
  55
  56 #ifdef CONFIG_CPU_FREQ
  57 struct part_no_info {
  58         const char      *part_no;       /* part number string of interest */
  59         int             max_freq;       /* khz */
  60 };
  61
  62 static struct part_no_info mityomapl138_pn_info[] = {
  63         {
  64                 .part_no        = "L138-C",
  65                 .max_freq       = 300000,
  66         },
  67         {
  68                 .part_no        = "L138-D",
  69                 .max_freq       = 375000,
  70         },
  71         {
  72                 .part_no        = "L138-F",
  73                 .max_freq       = 456000,
  74         },
  75         {
  76                 .part_no        = "1808-C",
  77                 .max_freq       = 300000,
  78         },
  79         {
  80                 .part_no        = "1808-D",
  81                 .max_freq       = 375000,
  82         },
  83         {
  84                 .part_no        = "1808-F",
  85                 .max_freq       = 456000,
  86         },
  87         {
  88                 .part_no        = "1810-D",
  89                 .max_freq       = 375000,
  90         },
  91 };
  92
  93 static void mityomapl138_cpufreq_init(const char *partnum)
  94 {
  95         int i, ret;
  96
  97         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  98                 /*
  99                  * the part number has additional characters beyond what is
 100                  * stored in the table.  This information is not needed for
 101                  * determining the speed grade, and would require several
 102                  * more table entries.  Only check the first N characters
 103                  * for a match.
 104                  */
 105                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 106                              strlen(mityomapl138_pn_info[i].part_no))) {
 107                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 108                         break;
 109                 }
 110         }
 111
 112         ret = da850_register_cpufreq("pll0_sysclk3");
 113         if (ret)
 114                 pr_warn("cpufreq registration failed: %d\n", ret);
 115 }
 116 #else
 117 static void mityomapl138_cpufreq_init(const char *partnum) { }
 118 #endif
 119
 120 static int read_factory_config(struct notifier_block *nb,
 121                                unsigned long event, void *data)
 122 {
 123         int ret;
 124         const char *partnum = NULL;
 125         struct nvmem_device *nvmem = data;
 126
 127         if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
 128                 return NOTIFY_DONE;
 129
 130         if (!IS_BUILTIN(CONFIG_NVMEM)) {
 131                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
 132                 goto bad_config;
 133         }
 134
 135         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
 136                                 &factory_config);
 137         if (ret != sizeof(struct factory_config)) {
 138                 pr_warn("Read Factory Config Failed: %d\n", ret);
 139                 goto bad_config;
 140         }
 141
 142         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 143                 pr_warn("Factory Config Magic Wrong (%X)\n",
 144                         factory_config.magic);
 145                 goto bad_config;
 146         }
 147
 148         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 149                 pr_warn("Factory Config Version Wrong (%X)\n",
 150                         factory_config.version);
 151                 goto bad_config;
 152         }
 153
 154         partnum = factory_config.partnum;
 155         pr_info("Part Number = %s\n", partnum);
 156
 157 bad_config:
 158         /* default maximum speed is valid for all platforms */
 159         mityomapl138_cpufreq_init(partnum);
 160
 161         return NOTIFY_STOP;
 162 }
 163
 164 static struct notifier_block mityomapl138_nvmem_notifier = {
 165         .notifier_call = read_factory_config,
 166 };
 167
 168 /*
 169  * We don't define a cell for factory config as it will be accessed from the
 170  * board file using the nvmem notifier chain.
 171  */
 172 static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
 173         {
 174                 .name           = "macaddr",
 175                 .offset         = 0x64,
 176                 .bytes          = ETH_ALEN,
 177         }
 178 };
 179
 180 static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
 181         .nvmem_name     = "1-00500",
 182         .cells          = mityomapl138_nvmem_cells,
 183         .ncells         = ARRAY_SIZE(mityomapl138_nvmem_cells),
 184 };
 185
 186 static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
 187         .nvmem_name     = "1-00500",
 188         .cell_name      = "macaddr",
 189         .dev_id         = "davinci_emac.1",
 190         .con_id         = "mac-address",
 191 };
 192
 193 static const struct property_entry mityomapl138_fd_chip_properties[] = {
 194         PROPERTY_ENTRY_U32("pagesize", 8),
 195         PROPERTY_ENTRY_BOOL("read-only"),
 196         { }
 197 };
 198
 199 static const struct software_node mityomapl138_fd_chip_node = {
 200         .properties = mityomapl138_fd_chip_properties,
 201 };
 202
 203 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 204         .bus_freq       = 100,  /* kHz */
 205         .bus_delay      = 0,    /* usec */
 206 };
 207
 208 /* TPS65023 voltage regulator support */
 209 /* 1.2V Core */
 210 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 211         {
 212                 .supply = "cvdd",
 213         },
 214 };
 215
 216 /* 1.8V */
 217 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 218         {
 219                 .supply = "usb0_vdda18",
 220         },
 221         {
 222                 .supply = "usb1_vdda18",
 223         },
 224         {
 225                 .supply = "ddr_dvdd18",
 226         },
 227         {
 228                 .supply = "sata_vddr",
 229         },
 230 };
 231
 232 /* 1.2V */
 233 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 234         {
 235                 .supply = "sata_vdd",
 236         },
 237         {
 238                 .supply = "usb_cvdd",
 239         },
 240         {
 241                 .supply = "pll0_vdda",
 242         },
 243         {
 244                 .supply = "pll1_vdda",
 245         },
 246 };
 247
 248 /* 1.8V Aux LDO, not used */
 249 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 250         {
 251                 .supply = "1.8v_aux",
 252         },
 253 };
 254
 255 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 256 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 257         {
 258                 .supply = "vccaux",
 259         },
 260 };
 261
 262 static struct regulator_init_data tps65023_regulator_data[] = {
 263         /* dcdc1 */
 264         {
 265                 .constraints = {
 266                         .min_uV = 1150000,
 267                         .max_uV = 1350000,
 268                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 269                                           REGULATOR_CHANGE_STATUS,
 270                         .boot_on = 1,
 271                 },
 272                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 273                 .consumer_supplies = tps65023_dcdc1_consumers,
 274         },
 275         /* dcdc2 */
 276         {
 277                 .constraints = {
 278                         .min_uV = 1800000,
 279                         .max_uV = 1800000,
 280                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 281                         .boot_on = 1,
 282                 },
 283                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 284                 .consumer_supplies = tps65023_dcdc2_consumers,
 285         },
 286         /* dcdc3 */
 287         {
 288                 .constraints = {
 289                         .min_uV = 1200000,
 290                         .max_uV = 1200000,
 291                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 292                         .boot_on = 1,
 293                 },
 294                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 295                 .consumer_supplies = tps65023_dcdc3_consumers,
 296         },
 297         /* ldo1 */
 298         {
 299                 .constraints = {
 300                         .min_uV = 1800000,
 301                         .max_uV = 1800000,
 302                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 303                         .boot_on = 1,
 304                 },
 305                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 306                 .consumer_supplies = tps65023_ldo1_consumers,
 307         },
 308         /* ldo2 */
 309         {
 310                 .constraints = {
 311                         .min_uV = 2500000,
 312                         .max_uV = 3300000,
 313                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 314                                           REGULATOR_CHANGE_STATUS,
 315                         .boot_on = 1,
 316                 },
 317                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 318                 .consumer_supplies = tps65023_ldo2_consumers,
 319         },
 320 };
 321
 322 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 323         {
 324                 I2C_BOARD_INFO("tps65023", 0x48),
 325                 .platform_data = &tps65023_regulator_data[0],
 326         },
 327         {
 328                 I2C_BOARD_INFO("24c02", 0x50),
 329                 .swnode = &mityomapl138_fd_chip_node,
 330         },
 331 };
 332
 333 static int __init pmic_tps65023_init(void)
 334 {
 335         return i2c_register_board_info(1, mityomap_tps65023_info,
 336                                         ARRAY_SIZE(mityomap_tps65023_info));
 337 }
 338
 339 /*
 340  * SPI Devices:
 341  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 342  */
 343 static struct mtd_partition spi_flash_partitions[] = {
 344         [0] = {
 345                 .name           = "ubl",
 346                 .offset         = 0,
 347                 .size           = SZ_64K,
 348                 .mask_flags     = MTD_WRITEABLE,
 349         },
 350         [1] = {
 351                 .name           = "u-boot",
 352                 .offset         = MTDPART_OFS_APPEND,
 353                 .size           = SZ_512K,
 354                 .mask_flags     = MTD_WRITEABLE,
 355         },
 356         [2] = {
 357                 .name           = "u-boot-env",
 358                 .offset         = MTDPART_OFS_APPEND,
 359                 .size           = SZ_64K,
 360                 .mask_flags     = MTD_WRITEABLE,
 361         },
 362         [3] = {
 363                 .name           = "periph-config",
 364                 .offset         = MTDPART_OFS_APPEND,
 365                 .size           = SZ_64K,
 366                 .mask_flags     = MTD_WRITEABLE,
 367         },
 368         [4] = {
 369                 .name           = "reserved",
 370                 .offset         = MTDPART_OFS_APPEND,
 371                 .size           = SZ_256K + SZ_64K,
 372         },
 373         [5] = {
 374                 .name           = "kernel",
 375                 .offset         = MTDPART_OFS_APPEND,
 376                 .size           = SZ_2M + SZ_1M,
 377         },
 378         [6] = {
 379                 .name           = "fpga",
 380                 .offset         = MTDPART_OFS_APPEND,
 381                 .size           = SZ_2M,
 382         },
 383         [7] = {
 384                 .name           = "spare",
 385                 .offset         = MTDPART_OFS_APPEND,
 386                 .size           = MTDPART_SIZ_FULL,
 387         },
 388 };
 389
 390 static struct flash_platform_data mityomapl138_spi_flash_data = {
 391         .name           = "m25p80",
 392         .parts          = spi_flash_partitions,
 393         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 394         .type           = "m24p64",
 395 };
 396
 397 static struct davinci_spi_config spi_eprom_config = {
 398         .io_type        = SPI_IO_TYPE_DMA,
 399         .c2tdelay       = 8,
 400         .t2cdelay       = 8,
 401 };
 402
 403 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 404         {
 405                 .modalias               = "m25p80",
 406                 .platform_data          = &mityomapl138_spi_flash_data,
 407                 .controller_data        = &spi_eprom_config,
 408                 .mode                   = SPI_MODE_0,
 409                 .max_speed_hz           = 30000000,
 410                 .bus_num                = 1,
 411                 .chip_select            = 0,
 412         },
 413 };
 414
 415 /*
 416  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 417  * (128K blocks).
 418  */
 419 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 420         {
 421                 .name           = "rootfs",
 422                 .offset         = 0,
 423                 .size           = SZ_128M,
 424                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 425         },
 426         {
 427                 .name           = "homefs",
 428                 .offset         = MTDPART_OFS_APPEND,
 429                 .size           = MTDPART_SIZ_FULL,
 430                 .mask_flags     = 0,
 431         },
 432 };
 433
 434 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 435         .core_chipsel   = 1,
 436         .parts          = mityomapl138_nandflash_partition,
 437         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 438         .engine_type    = NAND_ECC_ENGINE_TYPE_ON_HOST,
 439         .bbt_options    = NAND_BBT_USE_FLASH,
 440         .options        = NAND_BUSWIDTH_16,
 441         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 442 };
 443
 444 static struct resource mityomapl138_nandflash_resource[] = {
 445         {
 446                 .start  = DA8XX_AEMIF_CS3_BASE,
 447                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 448                 .flags  = IORESOURCE_MEM,
 449         },
 450         {
 451                 .start  = DA8XX_AEMIF_CTL_BASE,
 452                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 453                 .flags  = IORESOURCE_MEM,
 454         },
 455 };
 456
 457 static struct platform_device mityomapl138_aemif_devices[] = {
 458         {
 459                 .name           = "davinci_nand",
 460                 .id             = 1,
 461                 .dev            = {
 462                         .platform_data  = &mityomapl138_nandflash_data,
 463                 },
 464                 .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 465                 .resource       = mityomapl138_nandflash_resource,
 466         },
 467 };
 468
 469 static struct resource mityomapl138_aemif_resources[] = {
 470         {
 471                 .start  = DA8XX_AEMIF_CTL_BASE,
 472                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 473                 .flags  = IORESOURCE_MEM,
 474         },
 475 };
 476
 477 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
 478         {
 479                 .cs     = 1,
 480         },
 481 };
 482
 483 static struct aemif_platform_data mityomapl138_aemif_pdata = {
 484         .abus_data              = mityomapl138_aemif_abus_data,
 485         .num_abus_data          = ARRAY_SIZE(mityomapl138_aemif_abus_data),
 486         .sub_devices            = mityomapl138_aemif_devices,
 487         .num_sub_devices        = ARRAY_SIZE(mityomapl138_aemif_devices),
 488 };
 489
 490 static struct platform_device mityomapl138_aemif_device = {
 491         .name           = "ti-aemif",
 492         .id             = -1,
 493         .dev = {
 494                 .platform_data  = &mityomapl138_aemif_pdata,
 495         },
 496         .resource       = mityomapl138_aemif_resources,
 497         .num_resources  = ARRAY_SIZE(mityomapl138_aemif_resources),
 498 };
 499
 500 static void __init mityomapl138_setup_nand(void)
 501 {
 502         if (platform_device_register(&mityomapl138_aemif_device))
 503                 pr_warn("%s: Cannot register AEMIF device\n", __func__);
 504 }
 505
 506 static const short mityomap_mii_pins[] = {
 507         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 508         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 509         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 510         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 511         DA850_MDIO_D,
 512         -1
 513 };
 514
 515 static const short mityomap_rmii_pins[] = {
 516         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 517         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 518         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 519         DA850_MDIO_D,
 520         -1
 521 };
 522
 523 static void __init mityomapl138_config_emac(void)
 524 {
 525         void __iomem *cfg_chip3_base;
 526         int ret;
 527         u32 val;
 528         struct davinci_soc_info *soc_info = &davinci_soc_info;
 529
 530         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 531
 532         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 533         val = __raw_readl(cfg_chip3_base);
 534
 535         if (soc_info->emac_pdata->rmii_en) {
 536                 val |= BIT(8);
 537                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 538                 pr_info("RMII PHY configured\n");
 539         } else {
 540                 val &= ~BIT(8);
 541                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 542                 pr_info("MII PHY configured\n");
 543         }
 544
 545         if (ret) {
 546                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
 547                 return;
 548         }
 549
 550         /* configure the CFGCHIP3 register for RMII or MII */
 551         __raw_writel(val, cfg_chip3_base);
 552
 553         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 554
 555         ret = da8xx_register_emac();
 556         if (ret)
 557                 pr_warn("emac registration failed: %d\n", ret);
 558 }
 559
 560 static void __init mityomapl138_init(void)
 561 {
 562         int ret;
 563
 564         da850_register_clocks();
 565
 566         /* for now, no special EDMA channels are reserved */
 567         ret = da850_register_edma(NULL);
 568         if (ret)
 569                 pr_warn("edma registration failed: %d\n", ret);
 570
 571         ret = da8xx_register_watchdog();
 572         if (ret)
 573                 pr_warn("watchdog registration failed: %d\n", ret);
 574
 575         davinci_serial_init(da8xx_serial_device);
 576
 577         nvmem_register_notifier(&mityomapl138_nvmem_notifier);
 578         nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
 579         nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
 580
 581         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 582         if (ret)
 583                 pr_warn("i2c0 registration failed: %d\n", ret);
 584
 585         ret = pmic_tps65023_init();
 586         if (ret)
 587                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
 588
 589         mityomapl138_setup_nand();
 590
 591         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 592                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 593         if (ret)
 594                 pr_warn("spi info registration failed: %d\n", ret);
 595
 596         ret = da8xx_register_spi_bus(1,
 597                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 598         if (ret)
 599                 pr_warn("spi 1 registration failed: %d\n", ret);
 600
 601         mityomapl138_config_emac();
 602
 603         ret = da8xx_register_rtc();
 604         if (ret)
 605                 pr_warn("rtc setup failed: %d\n", ret);
 606
 607         ret = da8xx_register_cpuidle();
 608         if (ret)
 609                 pr_warn("cpuidle registration failed: %d\n", ret);
 610
 611         davinci_pm_init();
 612 }
 613
 614 #ifdef CONFIG_SERIAL_8250_CONSOLE
 615 static int __init mityomapl138_console_init(void)
 616 {
 617         if (!machine_is_mityomapl138())
 618                 return 0;
 619
 620         return add_preferred_console("ttyS", 1, "115200");
 621 }
 622 console_initcall(mityomapl138_console_init);
 623 #endif
 624
 625 static void __init mityomapl138_map_io(void)
 626 {
 627         da850_init();
 628 }
 629
 630 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 631         .atag_offset    = 0x100,
 632         .map_io         = mityomapl138_map_io,
 633         .init_irq       = da850_init_irq,
 634         .init_time      = da850_init_time,
 635         .init_machine   = mityomapl138_init,
 636         .init_late      = davinci_init_late,
 637         .dma_zone_size  = SZ_128M,
 638 MACHINE_END