arch/arm/mach-davinci/board-mityomapl138.c

   1 /*
   2  * Critical Link MityOMAP-L138 SoM
   3  *
   4  * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of
   8  * any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/notifier.h>
  20 #include <linux/nvmem-consumer.h>
  21 #include <linux/nvmem-provider.h>
  22 #include <linux/regulator/machine.h>
  23 #include <linux/i2c.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/spi/flash.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31
  32 #include "common.h"
  33 #include "da8xx.h"
  34 #include "mux.h"
  35
  36 #include <linux/platform_data/mtd-davinci.h>
  37 #include <linux/platform_data/mtd-davinci-aemif.h>
  38 #include <linux/platform_data/ti-aemif.h>
  39 #include <linux/platform_data/spi-davinci.h>
  40
  41 #define MITYOMAPL138_PHY_ID             ""
  42
  43 #define FACTORY_CONFIG_MAGIC    0x012C0138
  44 #define FACTORY_CONFIG_VERSION  0x00010001
  45
  46 /* Data Held in On-Board I2C device */
  47 struct factory_config {
  48         u32     magic;
  49         u32     version;
  50         u8      mac[6];
  51         u32     fpga_type;
  52         u32     spare;
  53         u32     serialnumber;
  54         char    partnum[32];
  55 };
  56
  57 static struct factory_config factory_config;
  58
  59 #ifdef CONFIG_CPU_FREQ
  60 struct part_no_info {
  61         const char      *part_no;       /* part number string of interest */
  62         int             max_freq;       /* khz */
  63 };
  64
  65 static struct part_no_info mityomapl138_pn_info[] = {
  66         {
  67                 .part_no        = "L138-C",
  68                 .max_freq       = 300000,
  69         },
  70         {
  71                 .part_no        = "L138-D",
  72                 .max_freq       = 375000,
  73         },
  74         {
  75                 .part_no        = "L138-F",
  76                 .max_freq       = 456000,
  77         },
  78         {
  79                 .part_no        = "1808-C",
  80                 .max_freq       = 300000,
  81         },
  82         {
  83                 .part_no        = "1808-D",
  84                 .max_freq       = 375000,
  85         },
  86         {
  87                 .part_no        = "1808-F",
  88                 .max_freq       = 456000,
  89         },
  90         {
  91                 .part_no        = "1810-D",
  92                 .max_freq       = 375000,
  93         },
  94 };
  95
  96 static void mityomapl138_cpufreq_init(const char *partnum)
  97 {
  98         int i, ret;
  99
 100         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
 101                 /*
 102                  * the part number has additional characters beyond what is
 103                  * stored in the table.  This information is not needed for
 104                  * determining the speed grade, and would require several
 105                  * more table entries.  Only check the first N characters
 106                  * for a match.
 107                  */
 108                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 109                              strlen(mityomapl138_pn_info[i].part_no))) {
 110                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 111                         break;
 112                 }
 113         }
 114
 115         ret = da850_register_cpufreq("pll0_sysclk3");
 116         if (ret)
 117                 pr_warn("cpufreq registration failed: %d\n", ret);
 118 }
 119 #else
 120 static void mityomapl138_cpufreq_init(const char *partnum) { }
 121 #endif
 122
 123 static int read_factory_config(struct notifier_block *nb,
 124                                unsigned long event, void *data)
 125 {
 126         int ret;
 127         const char *partnum = NULL;
 128         struct nvmem_device *nvmem = data;
 129
 130         if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
 131                 return NOTIFY_DONE;
 132
 133         if (!IS_BUILTIN(CONFIG_NVMEM)) {
 134                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
 135                 goto bad_config;
 136         }
 137
 138         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
 139                                 &factory_config);
 140         if (ret != sizeof(struct factory_config)) {
 141                 pr_warn("Read Factory Config Failed: %d\n", ret);
 142                 goto bad_config;
 143         }
 144
 145         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 146                 pr_warn("Factory Config Magic Wrong (%X)\n",
 147                         factory_config.magic);
 148                 goto bad_config;
 149         }
 150
 151         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 152                 pr_warn("Factory Config Version Wrong (%X)\n",
 153                         factory_config.version);
 154                 goto bad_config;
 155         }
 156
 157         partnum = factory_config.partnum;
 158         pr_info("Part Number = %s\n", partnum);
 159
 160 bad_config:
 161         /* default maximum speed is valid for all platforms */
 162         mityomapl138_cpufreq_init(partnum);
 163
 164         return NOTIFY_STOP;
 165 }
 166
 167 static struct notifier_block mityomapl138_nvmem_notifier = {
 168         .notifier_call = read_factory_config,
 169 };
 170
 171 /*
 172  * We don't define a cell for factory config as it will be accessed from the
 173  * board file using the nvmem notifier chain.
 174  */
 175 static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
 176         {
 177                 .name           = "macaddr",
 178                 .offset         = 0x64,
 179                 .bytes          = ETH_ALEN,
 180         }
 181 };
 182
 183 static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
 184         .nvmem_name     = "1-00500",
 185         .cells          = mityomapl138_nvmem_cells,
 186         .ncells         = ARRAY_SIZE(mityomapl138_nvmem_cells),
 187 };
 188
 189 static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
 190         .nvmem_name     = "1-00500",
 191         .cell_name      = "macaddr",
 192         .dev_id         = "davinci_emac.1",
 193         .con_id         = "mac-address",
 194 };
 195
 196 static const struct property_entry mityomapl138_fd_chip_properties[] = {
 197         PROPERTY_ENTRY_U32("pagesize", 8),
 198         PROPERTY_ENTRY_BOOL("read-only"),
 199         { }
 200 };
 201
 202 static const struct software_node mityomapl138_fd_chip_node = {
 203         .properties = mityomapl138_fd_chip_properties,
 204 };
 205
 206 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 207         .bus_freq       = 100,  /* kHz */
 208         .bus_delay      = 0,    /* usec */
 209 };
 210
 211 /* TPS65023 voltage regulator support */
 212 /* 1.2V Core */
 213 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 214         {
 215                 .supply = "cvdd",
 216         },
 217 };
 218
 219 /* 1.8V */
 220 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 221         {
 222                 .supply = "usb0_vdda18",
 223         },
 224         {
 225                 .supply = "usb1_vdda18",
 226         },
 227         {
 228                 .supply = "ddr_dvdd18",
 229         },
 230         {
 231                 .supply = "sata_vddr",
 232         },
 233 };
 234
 235 /* 1.2V */
 236 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 237         {
 238                 .supply = "sata_vdd",
 239         },
 240         {
 241                 .supply = "usb_cvdd",
 242         },
 243         {
 244                 .supply = "pll0_vdda",
 245         },
 246         {
 247                 .supply = "pll1_vdda",
 248         },
 249 };
 250
 251 /* 1.8V Aux LDO, not used */
 252 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 253         {
 254                 .supply = "1.8v_aux",
 255         },
 256 };
 257
 258 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 259 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 260         {
 261                 .supply = "vccaux",
 262         },
 263 };
 264
 265 static struct regulator_init_data tps65023_regulator_data[] = {
 266         /* dcdc1 */
 267         {
 268                 .constraints = {
 269                         .min_uV = 1150000,
 270                         .max_uV = 1350000,
 271                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 272                                           REGULATOR_CHANGE_STATUS,
 273                         .boot_on = 1,
 274                 },
 275                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 276                 .consumer_supplies = tps65023_dcdc1_consumers,
 277         },
 278         /* dcdc2 */
 279         {
 280                 .constraints = {
 281                         .min_uV = 1800000,
 282                         .max_uV = 1800000,
 283                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 284                         .boot_on = 1,
 285                 },
 286                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 287                 .consumer_supplies = tps65023_dcdc2_consumers,
 288         },
 289         /* dcdc3 */
 290         {
 291                 .constraints = {
 292                         .min_uV = 1200000,
 293                         .max_uV = 1200000,
 294                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 295                         .boot_on = 1,
 296                 },
 297                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 298                 .consumer_supplies = tps65023_dcdc3_consumers,
 299         },
 300         /* ldo1 */
 301         {
 302                 .constraints = {
 303                         .min_uV = 1800000,
 304                         .max_uV = 1800000,
 305                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 306                         .boot_on = 1,
 307                 },
 308                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 309                 .consumer_supplies = tps65023_ldo1_consumers,
 310         },
 311         /* ldo2 */
 312         {
 313                 .constraints = {
 314                         .min_uV = 2500000,
 315                         .max_uV = 3300000,
 316                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 317                                           REGULATOR_CHANGE_STATUS,
 318                         .boot_on = 1,
 319                 },
 320                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 321                 .consumer_supplies = tps65023_ldo2_consumers,
 322         },
 323 };
 324
 325 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 326         {
 327                 I2C_BOARD_INFO("tps65023", 0x48),
 328                 .platform_data = &tps65023_regulator_data[0],
 329         },
 330         {
 331                 I2C_BOARD_INFO("24c02", 0x50),
 332                 .swnode = &mityomapl138_fd_chip_node,
 333         },
 334 };
 335
 336 static int __init pmic_tps65023_init(void)
 337 {
 338         return i2c_register_board_info(1, mityomap_tps65023_info,
 339                                         ARRAY_SIZE(mityomap_tps65023_info));
 340 }
 341
 342 /*
 343  * SPI Devices:
 344  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 345  */
 346 static struct mtd_partition spi_flash_partitions[] = {
 347         [0] = {
 348                 .name           = "ubl",
 349                 .offset         = 0,
 350                 .size           = SZ_64K,
 351                 .mask_flags     = MTD_WRITEABLE,
 352         },
 353         [1] = {
 354                 .name           = "u-boot",
 355                 .offset         = MTDPART_OFS_APPEND,
 356                 .size           = SZ_512K,
 357                 .mask_flags     = MTD_WRITEABLE,
 358         },
 359         [2] = {
 360                 .name           = "u-boot-env",
 361                 .offset         = MTDPART_OFS_APPEND,
 362                 .size           = SZ_64K,
 363                 .mask_flags     = MTD_WRITEABLE,
 364         },
 365         [3] = {
 366                 .name           = "periph-config",
 367                 .offset         = MTDPART_OFS_APPEND,
 368                 .size           = SZ_64K,
 369                 .mask_flags     = MTD_WRITEABLE,
 370         },
 371         [4] = {
 372                 .name           = "reserved",
 373                 .offset         = MTDPART_OFS_APPEND,
 374                 .size           = SZ_256K + SZ_64K,
 375         },
 376         [5] = {
 377                 .name           = "kernel",
 378                 .offset         = MTDPART_OFS_APPEND,
 379                 .size           = SZ_2M + SZ_1M,
 380         },
 381         [6] = {
 382                 .name           = "fpga",
 383                 .offset         = MTDPART_OFS_APPEND,
 384                 .size           = SZ_2M,
 385         },
 386         [7] = {
 387                 .name           = "spare",
 388                 .offset         = MTDPART_OFS_APPEND,
 389                 .size           = MTDPART_SIZ_FULL,
 390         },
 391 };
 392
 393 static struct flash_platform_data mityomapl138_spi_flash_data = {
 394         .name           = "m25p80",
 395         .parts          = spi_flash_partitions,
 396         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 397         .type           = "m24p64",
 398 };
 399
 400 static struct davinci_spi_config spi_eprom_config = {
 401         .io_type        = SPI_IO_TYPE_DMA,
 402         .c2tdelay       = 8,
 403         .t2cdelay       = 8,
 404 };
 405
 406 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 407         {
 408                 .modalias               = "m25p80",
 409                 .platform_data          = &mityomapl138_spi_flash_data,
 410                 .controller_data        = &spi_eprom_config,
 411                 .mode                   = SPI_MODE_0,
 412                 .max_speed_hz           = 30000000,
 413                 .bus_num                = 1,
 414                 .chip_select            = 0,
 415         },
 416 };
 417
 418 /*
 419  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 420  * (128K blocks).
 421  */
 422 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 423         {
 424                 .name           = "rootfs",
 425                 .offset         = 0,
 426                 .size           = SZ_128M,
 427                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 428         },
 429         {
 430                 .name           = "homefs",
 431                 .offset         = MTDPART_OFS_APPEND,
 432                 .size           = MTDPART_SIZ_FULL,
 433                 .mask_flags     = 0,
 434         },
 435 };
 436
 437 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 438         .core_chipsel   = 1,
 439         .parts          = mityomapl138_nandflash_partition,
 440         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 441         .engine_type    = NAND_ECC_ENGINE_TYPE_ON_HOST,
 442         .bbt_options    = NAND_BBT_USE_FLASH,
 443         .options        = NAND_BUSWIDTH_16,
 444         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 445 };
 446
 447 static struct resource mityomapl138_nandflash_resource[] = {
 448         {
 449                 .start  = DA8XX_AEMIF_CS3_BASE,
 450                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 451                 .flags  = IORESOURCE_MEM,
 452         },
 453         {
 454                 .start  = DA8XX_AEMIF_CTL_BASE,
 455                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 456                 .flags  = IORESOURCE_MEM,
 457         },
 458 };
 459
 460 static struct platform_device mityomapl138_aemif_devices[] = {
 461         {
 462                 .name           = "davinci_nand",
 463                 .id             = 1,
 464                 .dev            = {
 465                         .platform_data  = &mityomapl138_nandflash_data,
 466                 },
 467                 .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 468                 .resource       = mityomapl138_nandflash_resource,
 469         },
 470 };
 471
 472 static struct resource mityomapl138_aemif_resources[] = {
 473         {
 474                 .start  = DA8XX_AEMIF_CTL_BASE,
 475                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 476                 .flags  = IORESOURCE_MEM,
 477         },
 478 };
 479
 480 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
 481         {
 482                 .cs     = 1,
 483         },
 484 };
 485
 486 static struct aemif_platform_data mityomapl138_aemif_pdata = {
 487         .abus_data              = mityomapl138_aemif_abus_data,
 488         .num_abus_data          = ARRAY_SIZE(mityomapl138_aemif_abus_data),
 489         .sub_devices            = mityomapl138_aemif_devices,
 490         .num_sub_devices        = ARRAY_SIZE(mityomapl138_aemif_devices),
 491 };
 492
 493 static struct platform_device mityomapl138_aemif_device = {
 494         .name           = "ti-aemif",
 495         .id             = -1,
 496         .dev = {
 497                 .platform_data  = &mityomapl138_aemif_pdata,
 498         },
 499         .resource       = mityomapl138_aemif_resources,
 500         .num_resources  = ARRAY_SIZE(mityomapl138_aemif_resources),
 501 };
 502
 503 static void __init mityomapl138_setup_nand(void)
 504 {
 505         if (platform_device_register(&mityomapl138_aemif_device))
 506                 pr_warn("%s: Cannot register AEMIF device\n", __func__);
 507 }
 508
 509 static const short mityomap_mii_pins[] = {
 510         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 511         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 512         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 513         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 514         DA850_MDIO_D,
 515         -1
 516 };
 517
 518 static const short mityomap_rmii_pins[] = {
 519         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 520         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 521         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 522         DA850_MDIO_D,
 523         -1
 524 };
 525
 526 static void __init mityomapl138_config_emac(void)
 527 {
 528         void __iomem *cfg_chip3_base;
 529         int ret;
 530         u32 val;
 531         struct davinci_soc_info *soc_info = &davinci_soc_info;
 532
 533         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 534
 535         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 536         val = __raw_readl(cfg_chip3_base);
 537
 538         if (soc_info->emac_pdata->rmii_en) {
 539                 val |= BIT(8);
 540                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 541                 pr_info("RMII PHY configured\n");
 542         } else {
 543                 val &= ~BIT(8);
 544                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 545                 pr_info("MII PHY configured\n");
 546         }
 547
 548         if (ret) {
 549                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
 550                 return;
 551         }
 552
 553         /* configure the CFGCHIP3 register for RMII or MII */
 554         __raw_writel(val, cfg_chip3_base);
 555
 556         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 557
 558         ret = da8xx_register_emac();
 559         if (ret)
 560                 pr_warn("emac registration failed: %d\n", ret);
 561 }
 562
 563 static void __init mityomapl138_init(void)
 564 {
 565         int ret;
 566
 567         da850_register_clocks();
 568
 569         /* for now, no special EDMA channels are reserved */
 570         ret = da850_register_edma(NULL);
 571         if (ret)
 572                 pr_warn("edma registration failed: %d\n", ret);
 573
 574         ret = da8xx_register_watchdog();
 575         if (ret)
 576                 pr_warn("watchdog registration failed: %d\n", ret);
 577
 578         davinci_serial_init(da8xx_serial_device);
 579
 580         nvmem_register_notifier(&mityomapl138_nvmem_notifier);
 581         nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
 582         nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
 583
 584         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 585         if (ret)
 586                 pr_warn("i2c0 registration failed: %d\n", ret);
 587
 588         ret = pmic_tps65023_init();
 589         if (ret)
 590                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
 591
 592         mityomapl138_setup_nand();
 593
 594         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 595                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 596         if (ret)
 597                 pr_warn("spi info registration failed: %d\n", ret);
 598
 599         ret = da8xx_register_spi_bus(1,
 600                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 601         if (ret)
 602                 pr_warn("spi 1 registration failed: %d\n", ret);
 603
 604         mityomapl138_config_emac();
 605
 606         ret = da8xx_register_rtc();
 607         if (ret)
 608                 pr_warn("rtc setup failed: %d\n", ret);
 609
 610         ret = da8xx_register_cpuidle();
 611         if (ret)
 612                 pr_warn("cpuidle registration failed: %d\n", ret);
 613
 614         davinci_pm_init();
 615 }
 616
 617 #ifdef CONFIG_SERIAL_8250_CONSOLE
 618 static int __init mityomapl138_console_init(void)
 619 {
 620         if (!machine_is_mityomapl138())
 621                 return 0;
 622
 623         return add_preferred_console("ttyS", 1, "115200");
 624 }
 625 console_initcall(mityomapl138_console_init);
 626 #endif
 627
 628 static void __init mityomapl138_map_io(void)
 629 {
 630         da850_init();
 631 }
 632
 633 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 634         .atag_offset    = 0x100,
 635         .map_io         = mityomapl138_map_io,
 636         .init_irq       = da850_init_irq,
 637         .init_time      = da850_init_time,
 638         .init_machine   = mityomapl138_init,
 639         .init_late      = davinci_init_late,
 640         .dma_zone_size  = SZ_128M,
 641 MACHINE_END