1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DaVinci DM365 EVM board support
5 * Copyright (C) 2009 Texas Instruments Incorporated
7 #include <linux/kernel.h>
8 #include <linux/init.h>
10 #include <linux/i2c.h>
12 #include <linux/clk.h>
13 #include <linux/property.h>
14 #include <linux/leds.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/slab.h>
18 #include <linux/mtd/rawnand.h>
19 #include <linux/nvmem-provider.h>
20 #include <linux/input.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/eeprom.h>
23 #include <linux/v4l2-dv-timings.h>
24 #include <linux/platform_data/ti-aemif.h>
25 #include <linux/regulator/fixed.h>
26 #include <linux/regulator/machine.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
31 #include <linux/platform_data/i2c-davinci.h>
32 #include <linux/platform_data/mmc-davinci.h>
33 #include <linux/platform_data/mtd-davinci.h>
34 #include <linux/platform_data/keyscan-davinci.h>
36 #include <media/i2c/ths7303.h>
37 #include <media/i2c/tvp514x.h>
44 static inline int have_imager(void)
46 /* REVISIT when it's supported, trigger via Kconfig */
50 static inline int have_tvp7002(void)
52 /* REVISIT when it's supported, trigger via Kconfig */
56 #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
58 * A MAX-II CPLD is used for various board control functions.
60 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
62 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
63 #define CPLD_TEST CPLD_OFFSET(0,1)
64 #define CPLD_LEDS CPLD_OFFSET(0,2)
65 #define CPLD_MUX CPLD_OFFSET(0,3)
66 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
67 #define CPLD_POWER CPLD_OFFSET(1,1)
68 #define CPLD_VIDEO CPLD_OFFSET(1,2)
69 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
71 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
72 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
74 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
75 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
76 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
77 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
78 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
79 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
80 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
81 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
82 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
84 #define CPLD_RESETS CPLD_OFFSET(4,3)
86 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
87 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
88 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
89 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
90 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
91 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
93 static void __iomem *cpld;
96 /* NOTE: this is geared for the standard config, with a socketed
97 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
98 * swap chips with a different block size, partitioning will
99 * need to be changed. This NAND chip MT29F16G08FAA is the default
100 * NAND shipped with the Spectrum Digital DM365 EVM
102 #define NAND_BLOCK_SIZE SZ_128K
104 static struct mtd_partition davinci_nand_partitions[] = {
106 /* UBL (a few copies) plus U-Boot */
107 .name = "bootloader",
109 .size = 30 * NAND_BLOCK_SIZE,
110 .mask_flags = MTD_WRITEABLE, /* force read-only */
112 /* U-Boot environment */
114 .offset = MTDPART_OFS_APPEND,
115 .size = 2 * NAND_BLOCK_SIZE,
119 .offset = MTDPART_OFS_APPEND,
123 .name = "filesystem1",
124 .offset = MTDPART_OFS_APPEND,
128 .name = "filesystem2",
129 .offset = MTDPART_OFS_APPEND,
130 .size = MTDPART_SIZ_FULL,
133 /* two blocks with bad block table (and mirror) at the end */
136 static struct davinci_nand_pdata davinci_nand_data = {
138 .mask_chipsel = BIT(14),
139 .parts = davinci_nand_partitions,
140 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
141 .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
142 .bbt_options = NAND_BBT_USE_FLASH,
146 static struct resource davinci_nand_resources[] = {
148 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
149 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
150 .flags = IORESOURCE_MEM,
152 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
153 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
154 .flags = IORESOURCE_MEM,
158 static struct platform_device davinci_aemif_devices[] = {
160 .name = "davinci_nand",
162 .num_resources = ARRAY_SIZE(davinci_nand_resources),
163 .resource = davinci_nand_resources,
165 .platform_data = &davinci_nand_data,
170 static struct resource davinci_aemif_resources[] = {
172 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
173 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
174 .flags = IORESOURCE_MEM,
178 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
184 static struct aemif_platform_data davinci_aemif_pdata = {
185 .abus_data = da850_evm_aemif_abus_data,
186 .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
187 .sub_devices = davinci_aemif_devices,
188 .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
191 static struct platform_device davinci_aemif_device = {
195 .platform_data = &davinci_aemif_pdata,
197 .resource = davinci_aemif_resources,
198 .num_resources = ARRAY_SIZE(davinci_aemif_resources),
201 static struct nvmem_cell_info davinci_nvmem_cells[] = {
209 static struct nvmem_cell_table davinci_nvmem_cell_table = {
210 .nvmem_name = "1-00500",
211 .cells = davinci_nvmem_cells,
212 .ncells = ARRAY_SIZE(davinci_nvmem_cells),
215 static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
216 .nvmem_name = "1-00500",
217 .cell_name = "macaddr",
218 .dev_id = "davinci_emac.1",
219 .con_id = "mac-address",
222 static const struct property_entry eeprom_properties[] = {
223 PROPERTY_ENTRY_U32("pagesize", 64),
227 static const struct software_node eeprom_node = {
228 .properties = eeprom_properties,
231 static struct i2c_board_info i2c_info[] = {
233 I2C_BOARD_INFO("24c256", 0x50),
234 .swnode = &eeprom_node,
237 I2C_BOARD_INFO("tlv320aic3x", 0x18),
241 static struct davinci_i2c_platform_data i2c_pdata = {
242 .bus_freq = 400 /* kHz */,
243 .bus_delay = 0 /* usec */,
246 /* Fixed regulator support */
247 static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
248 /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
249 REGULATOR_SUPPLY("AVDD", "1-0018"),
250 REGULATOR_SUPPLY("DRVDD", "1-0018"),
251 REGULATOR_SUPPLY("IOVDD", "1-0018"),
254 static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
255 /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
256 REGULATOR_SUPPLY("DVDD", "1-0018"),
259 static int dm365evm_keyscan_enable(struct device *dev)
261 return davinci_cfg_reg(DM365_KEYSCAN);
264 static unsigned short dm365evm_keymap[] = {
284 static struct davinci_ks_platform_data dm365evm_ks_data = {
285 .device_enable = dm365evm_keyscan_enable,
286 .keymap = dm365evm_keymap,
287 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
289 /* Scan period = strobe + interval */
292 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
295 static int cpld_mmc_get_cd(int module)
300 /* low == card present */
301 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
304 static int cpld_mmc_get_ro(int module)
309 /* high == card's write protect switch active */
310 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
313 static struct davinci_mmc_config dm365evm_mmc_config = {
314 .get_cd = cpld_mmc_get_cd,
315 .get_ro = cpld_mmc_get_ro,
317 .max_freq = 50000000,
318 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
321 static void dm365evm_emac_configure(void)
324 * EMAC pins are multiplexed with GPIO and UART
325 * Further details are available at the DM365 ARM
326 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
328 davinci_cfg_reg(DM365_EMAC_TX_EN);
329 davinci_cfg_reg(DM365_EMAC_TX_CLK);
330 davinci_cfg_reg(DM365_EMAC_COL);
331 davinci_cfg_reg(DM365_EMAC_TXD3);
332 davinci_cfg_reg(DM365_EMAC_TXD2);
333 davinci_cfg_reg(DM365_EMAC_TXD1);
334 davinci_cfg_reg(DM365_EMAC_TXD0);
335 davinci_cfg_reg(DM365_EMAC_RXD3);
336 davinci_cfg_reg(DM365_EMAC_RXD2);
337 davinci_cfg_reg(DM365_EMAC_RXD1);
338 davinci_cfg_reg(DM365_EMAC_RXD0);
339 davinci_cfg_reg(DM365_EMAC_RX_CLK);
340 davinci_cfg_reg(DM365_EMAC_RX_DV);
341 davinci_cfg_reg(DM365_EMAC_RX_ER);
342 davinci_cfg_reg(DM365_EMAC_CRS);
343 davinci_cfg_reg(DM365_EMAC_MDIO);
344 davinci_cfg_reg(DM365_EMAC_MDCLK);
347 * EMAC interrupts are multiplexed with GPIO interrupts
348 * Details are available at the DM365 ARM
349 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
351 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
352 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
353 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
354 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
357 static void dm365evm_mmc_configure(void)
360 * MMC/SD pins are multiplexed with GPIO and EMIF
361 * Further details are available at the DM365 ARM
362 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
364 davinci_cfg_reg(DM365_SD1_CLK);
365 davinci_cfg_reg(DM365_SD1_CMD);
366 davinci_cfg_reg(DM365_SD1_DATA3);
367 davinci_cfg_reg(DM365_SD1_DATA2);
368 davinci_cfg_reg(DM365_SD1_DATA1);
369 davinci_cfg_reg(DM365_SD1_DATA0);
372 static struct tvp514x_platform_data tvp5146_pdata = {
378 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
379 /* Inputs available at the TVP5146 */
380 static struct v4l2_input tvp5146_inputs[] = {
384 .type = V4L2_INPUT_TYPE_CAMERA,
385 .std = TVP514X_STD_ALL,
390 .type = V4L2_INPUT_TYPE_CAMERA,
391 .std = TVP514X_STD_ALL,
396 * this is the route info for connecting each input to decoder
397 * ouput that goes to vpfe. There is a one to one correspondence
398 * with tvp5146_inputs
400 static struct vpfe_route tvp5146_routes[] = {
402 .input = INPUT_CVBS_VI2B,
403 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
406 .input = INPUT_SVIDEO_VI2C_VI1C,
407 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
411 static struct vpfe_subdev_info vpfe_sub_devs[] = {
415 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
416 .inputs = tvp5146_inputs,
417 .routes = tvp5146_routes,
420 .if_type = VPFE_BT656,
421 .hdpol = VPFE_PINPOL_POSITIVE,
422 .vdpol = VPFE_PINPOL_POSITIVE,
425 I2C_BOARD_INFO("tvp5146", 0x5d),
426 .platform_data = &tvp5146_pdata,
431 static struct vpfe_config vpfe_cfg = {
432 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
433 .sub_devs = vpfe_sub_devs,
435 .card_name = "DM365 EVM",
439 /* venc standards timings */
440 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
443 .timings_type = VPBE_ENC_STD,
444 .std_id = V4L2_STD_NTSC,
449 .fps = {30000, 1001},
451 .upper_margin = 0x10,
455 .timings_type = VPBE_ENC_STD,
456 .std_id = V4L2_STD_PAL,
463 .upper_margin = 0x16,
467 /* venc dv timings */
468 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
471 .timings_type = VPBE_ENC_DV_TIMINGS,
472 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
479 .upper_margin = 0x2D,
483 .timings_type = VPBE_ENC_DV_TIMINGS,
484 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
491 .upper_margin = 0x36,
495 .timings_type = VPBE_ENC_DV_TIMINGS,
496 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
502 .left_margin = 0x117,
511 .timings_type = VPBE_ENC_DV_TIMINGS,
512 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
527 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
530 * The outputs available from VPBE + ecnoders. Keep the
531 * the order same as that of encoders. First those from venc followed by that
532 * from encoders. Index in the output refers to index on a particular
533 * encoder.Driver uses this index to pass it to encoder when it supports more
534 * than one output. Application uses index of the array to set an output.
536 static struct vpbe_output dm365evm_vpbe_outputs[] = {
541 .type = V4L2_OUTPUT_TYPE_ANALOG,
543 .capabilities = V4L2_OUT_CAP_STD,
545 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
546 .default_mode = "ntsc",
547 .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
548 .modes = dm365evm_enc_std_timing,
549 .if_params = MEDIA_BUS_FMT_FIXED,
555 .type = V4L2_OUTPUT_TYPE_ANALOG,
556 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
558 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
559 .default_mode = "480p59_94",
560 .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
561 .modes = dm365evm_enc_preset_timing,
562 .if_params = MEDIA_BUS_FMT_FIXED,
567 * Amplifiers on the board
569 static struct ths7303_platform_data ths7303_pdata = {
575 static struct amp_config_info vpbe_amp = {
576 .module_name = "ths7303",
579 I2C_BOARD_INFO("ths7303", 0x2c),
580 .platform_data = &ths7303_pdata,
584 static struct vpbe_config dm365evm_display_cfg = {
585 .module_name = "dm365-vpbe-display",
589 .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
592 .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
594 .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
595 .outputs = dm365evm_vpbe_outputs,
598 static void __init evm_init_i2c(void)
600 davinci_init_i2c(&i2c_pdata);
601 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
604 static inline int have_leds(void)
606 #ifdef CONFIG_LEDS_CLASS
614 struct led_classdev cdev;
618 static const struct {
622 { "dm365evm::ds2", },
623 { "dm365evm::ds3", },
624 { "dm365evm::ds4", },
625 { "dm365evm::ds5", },
626 { "dm365evm::ds6", "nand-disk", },
627 { "dm365evm::ds7", "mmc1", },
628 { "dm365evm::ds8", "mmc0", },
629 { "dm365evm::ds9", "heartbeat", },
632 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
634 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
635 u8 reg = __raw_readb(cpld + CPLD_LEDS);
641 __raw_writeb(reg, cpld + CPLD_LEDS);
644 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
646 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
647 u8 reg = __raw_readb(cpld + CPLD_LEDS);
649 return (reg & led->mask) ? LED_OFF : LED_FULL;
652 static int __init cpld_leds_init(void)
656 if (!have_leds() || !cpld)
660 __raw_writeb(0xff, cpld + CPLD_LEDS);
661 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
662 struct cpld_led *led;
664 led = kzalloc(sizeof(*led), GFP_KERNEL);
668 led->cdev.name = cpld_leds[i].name;
669 led->cdev.brightness_set = cpld_led_set;
670 led->cdev.brightness_get = cpld_led_get;
671 led->cdev.default_trigger = cpld_leds[i].trigger;
674 if (led_classdev_register(NULL, &led->cdev) < 0) {
682 /* run after subsys_initcall() for LEDs */
683 fs_initcall(cpld_leds_init);
686 static void __init evm_init_cpld(void)
690 struct clk *aemif_clk;
693 /* Make sure we can configure the CPLD through CS1. Then
694 * leave it on for later access to MMC and LED registers.
696 aemif_clk = clk_get(NULL, "aemif");
697 if (IS_ERR(aemif_clk))
699 clk_prepare_enable(aemif_clk);
701 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
704 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
706 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
709 pr_err("ERROR: can't map CPLD\n");
710 clk_disable_unprepare(aemif_clk);
714 /* External muxing for some signals */
717 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
718 * NOTE: SW4 bus width setting must match!
720 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
721 /* external keypad mux */
724 rc = platform_device_register(&davinci_aemif_device);
726 pr_warn("%s(): error registering the aemif device: %d\n",
729 /* no OneNAND support yet */
732 /* Leave external chips in reset when unused. */
733 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
735 /* Static video input config with SN74CBT16214 1-of-3 mux:
736 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
737 * - port b2 == imager (mux lowbits == 2 or 7)
738 * - port b3 == tvp5146 (mux lowbits == 5)
740 * Runtime switching could work too, with limitations.
746 /* externally mux MMC1/ENET/AIC33 to imager */
747 mux |= BIT(6) | BIT(5) | BIT(3);
749 struct davinci_soc_info *soc_info = &davinci_soc_info;
751 /* we can use MMC1 ... */
752 dm365evm_mmc_configure();
753 davinci_setup_mmc(1, &dm365evm_mmc_config);
755 /* ... and ENET ... */
756 dm365evm_emac_configure();
757 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
763 if (have_tvp7002()) {
766 label = "tvp7002 HD";
768 /* default to tvp5146 */
771 label = "tvp5146 SD";
774 __raw_writeb(mux, cpld + CPLD_MUX);
775 __raw_writeb(resets, cpld + CPLD_RESETS);
776 pr_info("EVM: %s video input\n", label);
778 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
781 static void __init dm365_evm_map_io(void)
786 static struct spi_eeprom at25640 = {
787 .byte_len = SZ_64K / 8,
793 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
796 .platform_data = &at25640,
797 .max_speed_hz = 10 * 1000 * 1000,
804 static __init void dm365_evm_init(void)
808 dm365_register_clocks();
810 ret = dm365_gpio_register();
812 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
814 regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
815 ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
816 regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
817 ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
819 nvmem_add_cell_table(&davinci_nvmem_cell_table);
820 nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
823 davinci_serial_init(dm365_serial_device);
825 dm365evm_emac_configure();
826 dm365evm_mmc_configure();
828 davinci_setup_mmc(0, &dm365evm_mmc_config);
830 dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
832 /* maybe setup mmc1/etc ... _after_ mmc0 */
835 #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
837 #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
841 dm365_init_ks(&dm365evm_ks_data);
843 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
844 ARRAY_SIZE(dm365_evm_spi_info));
847 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
848 .atag_offset = 0x100,
849 .map_io = dm365_evm_map_io,
850 .init_irq = dm365_init_irq,
851 .init_time = dm365_init_time,
852 .init_machine = dm365_evm_init,
853 .init_late = davinci_init_late,
854 .dma_zone_size = SZ_128M,