2 * TI DaVinci DM365 EVM board support
4 * Copyright (C) 2009 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
20 #include <linux/clk.h>
21 #include <linux/platform_data/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/rawnand.h>
27 #include <linux/input.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/eeprom.h>
30 #include <linux/v4l2-dv-timings.h>
31 #include <linux/platform_data/ti-aemif.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
37 #include <mach/common.h>
38 #include <linux/platform_data/i2c-davinci.h>
39 #include <mach/serial.h>
40 #include <linux/platform_data/mmc-davinci.h>
41 #include <linux/platform_data/mtd-davinci.h>
42 #include <linux/platform_data/keyscan-davinci.h>
44 #include <media/i2c/ths7303.h>
45 #include <media/i2c/tvp514x.h>
49 static inline int have_imager(void)
51 /* REVISIT when it's supported, trigger via Kconfig */
55 static inline int have_tvp7002(void)
57 /* REVISIT when it's supported, trigger via Kconfig */
61 #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
63 * A MAX-II CPLD is used for various board control functions.
65 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
67 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
68 #define CPLD_TEST CPLD_OFFSET(0,1)
69 #define CPLD_LEDS CPLD_OFFSET(0,2)
70 #define CPLD_MUX CPLD_OFFSET(0,3)
71 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
72 #define CPLD_POWER CPLD_OFFSET(1,1)
73 #define CPLD_VIDEO CPLD_OFFSET(1,2)
74 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
76 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
77 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
79 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
80 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
81 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
82 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
83 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
84 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
85 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
86 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
87 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
89 #define CPLD_RESETS CPLD_OFFSET(4,3)
91 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
92 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
93 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
94 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
95 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
96 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
98 static void __iomem *cpld;
101 /* NOTE: this is geared for the standard config, with a socketed
102 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
103 * swap chips with a different block size, partitioning will
104 * need to be changed. This NAND chip MT29F16G08FAA is the default
105 * NAND shipped with the Spectrum Digital DM365 EVM
107 #define NAND_BLOCK_SIZE SZ_128K
109 static struct mtd_partition davinci_nand_partitions[] = {
111 /* UBL (a few copies) plus U-Boot */
112 .name = "bootloader",
114 .size = 30 * NAND_BLOCK_SIZE,
115 .mask_flags = MTD_WRITEABLE, /* force read-only */
117 /* U-Boot environment */
119 .offset = MTDPART_OFS_APPEND,
120 .size = 2 * NAND_BLOCK_SIZE,
124 .offset = MTDPART_OFS_APPEND,
128 .name = "filesystem1",
129 .offset = MTDPART_OFS_APPEND,
133 .name = "filesystem2",
134 .offset = MTDPART_OFS_APPEND,
135 .size = MTDPART_SIZ_FULL,
138 /* two blocks with bad block table (and mirror) at the end */
141 static struct davinci_nand_pdata davinci_nand_data = {
143 .mask_chipsel = BIT(14),
144 .parts = davinci_nand_partitions,
145 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
146 .ecc_mode = NAND_ECC_HW,
147 .bbt_options = NAND_BBT_USE_FLASH,
151 static struct resource davinci_nand_resources[] = {
153 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
154 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
155 .flags = IORESOURCE_MEM,
157 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
158 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
159 .flags = IORESOURCE_MEM,
163 static struct platform_device davinci_aemif_devices[] = {
165 .name = "davinci_nand",
167 .num_resources = ARRAY_SIZE(davinci_nand_resources),
168 .resource = davinci_nand_resources,
170 .platform_data = &davinci_nand_data,
175 static struct resource davinci_aemif_resources[] = {
177 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
178 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
179 .flags = IORESOURCE_MEM,
183 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
189 static struct aemif_platform_data davinci_aemif_pdata = {
190 .abus_data = da850_evm_aemif_abus_data,
191 .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
192 .sub_devices = davinci_aemif_devices,
193 .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
196 static struct platform_device davinci_aemif_device = {
200 .platform_data = &davinci_aemif_pdata,
202 .resource = davinci_aemif_resources,
203 .num_resources = ARRAY_SIZE(davinci_aemif_resources),
206 static struct at24_platform_data eeprom_info = {
207 .byte_len = (256*1024) / 8,
209 .flags = AT24_FLAG_ADDR16,
210 .setup = davinci_get_mac_addr,
211 .context = (void *)0x7f00,
214 static struct i2c_board_info i2c_info[] = {
216 I2C_BOARD_INFO("24c256", 0x50),
217 .platform_data = &eeprom_info,
220 I2C_BOARD_INFO("tlv320aic3x", 0x18),
224 static struct davinci_i2c_platform_data i2c_pdata = {
225 .bus_freq = 400 /* kHz */,
226 .bus_delay = 0 /* usec */,
229 static int dm365evm_keyscan_enable(struct device *dev)
231 return davinci_cfg_reg(DM365_KEYSCAN);
234 static unsigned short dm365evm_keymap[] = {
254 static struct davinci_ks_platform_data dm365evm_ks_data = {
255 .device_enable = dm365evm_keyscan_enable,
256 .keymap = dm365evm_keymap,
257 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
259 /* Scan period = strobe + interval */
262 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
265 static int cpld_mmc_get_cd(int module)
270 /* low == card present */
271 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
274 static int cpld_mmc_get_ro(int module)
279 /* high == card's write protect switch active */
280 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
283 static struct davinci_mmc_config dm365evm_mmc_config = {
284 .get_cd = cpld_mmc_get_cd,
285 .get_ro = cpld_mmc_get_ro,
287 .max_freq = 50000000,
288 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
291 static void dm365evm_emac_configure(void)
294 * EMAC pins are multiplexed with GPIO and UART
295 * Further details are available at the DM365 ARM
296 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
298 davinci_cfg_reg(DM365_EMAC_TX_EN);
299 davinci_cfg_reg(DM365_EMAC_TX_CLK);
300 davinci_cfg_reg(DM365_EMAC_COL);
301 davinci_cfg_reg(DM365_EMAC_TXD3);
302 davinci_cfg_reg(DM365_EMAC_TXD2);
303 davinci_cfg_reg(DM365_EMAC_TXD1);
304 davinci_cfg_reg(DM365_EMAC_TXD0);
305 davinci_cfg_reg(DM365_EMAC_RXD3);
306 davinci_cfg_reg(DM365_EMAC_RXD2);
307 davinci_cfg_reg(DM365_EMAC_RXD1);
308 davinci_cfg_reg(DM365_EMAC_RXD0);
309 davinci_cfg_reg(DM365_EMAC_RX_CLK);
310 davinci_cfg_reg(DM365_EMAC_RX_DV);
311 davinci_cfg_reg(DM365_EMAC_RX_ER);
312 davinci_cfg_reg(DM365_EMAC_CRS);
313 davinci_cfg_reg(DM365_EMAC_MDIO);
314 davinci_cfg_reg(DM365_EMAC_MDCLK);
317 * EMAC interrupts are multiplexed with GPIO interrupts
318 * Details are available at the DM365 ARM
319 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
321 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
322 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
323 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
324 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
327 static void dm365evm_mmc_configure(void)
330 * MMC/SD pins are multiplexed with GPIO and EMIF
331 * Further details are available at the DM365 ARM
332 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
334 davinci_cfg_reg(DM365_SD1_CLK);
335 davinci_cfg_reg(DM365_SD1_CMD);
336 davinci_cfg_reg(DM365_SD1_DATA3);
337 davinci_cfg_reg(DM365_SD1_DATA2);
338 davinci_cfg_reg(DM365_SD1_DATA1);
339 davinci_cfg_reg(DM365_SD1_DATA0);
342 static struct tvp514x_platform_data tvp5146_pdata = {
348 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
349 /* Inputs available at the TVP5146 */
350 static struct v4l2_input tvp5146_inputs[] = {
354 .type = V4L2_INPUT_TYPE_CAMERA,
355 .std = TVP514X_STD_ALL,
360 .type = V4L2_INPUT_TYPE_CAMERA,
361 .std = TVP514X_STD_ALL,
366 * this is the route info for connecting each input to decoder
367 * ouput that goes to vpfe. There is a one to one correspondence
368 * with tvp5146_inputs
370 static struct vpfe_route tvp5146_routes[] = {
372 .input = INPUT_CVBS_VI2B,
373 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
376 .input = INPUT_SVIDEO_VI2C_VI1C,
377 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
381 static struct vpfe_subdev_info vpfe_sub_devs[] = {
385 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
386 .inputs = tvp5146_inputs,
387 .routes = tvp5146_routes,
390 .if_type = VPFE_BT656,
391 .hdpol = VPFE_PINPOL_POSITIVE,
392 .vdpol = VPFE_PINPOL_POSITIVE,
395 I2C_BOARD_INFO("tvp5146", 0x5d),
396 .platform_data = &tvp5146_pdata,
401 static struct vpfe_config vpfe_cfg = {
402 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
403 .sub_devs = vpfe_sub_devs,
405 .card_name = "DM365 EVM",
409 /* venc standards timings */
410 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
413 .timings_type = VPBE_ENC_STD,
414 .std_id = V4L2_STD_NTSC,
419 .fps = {30000, 1001},
421 .upper_margin = 0x10,
425 .timings_type = VPBE_ENC_STD,
426 .std_id = V4L2_STD_PAL,
433 .upper_margin = 0x16,
437 /* venc dv timings */
438 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
441 .timings_type = VPBE_ENC_DV_TIMINGS,
442 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
449 .upper_margin = 0x2D,
453 .timings_type = VPBE_ENC_DV_TIMINGS,
454 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
461 .upper_margin = 0x36,
465 .timings_type = VPBE_ENC_DV_TIMINGS,
466 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
472 .left_margin = 0x117,
481 .timings_type = VPBE_ENC_DV_TIMINGS,
482 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
497 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
500 * The outputs available from VPBE + ecnoders. Keep the
501 * the order same as that of encoders. First those from venc followed by that
502 * from encoders. Index in the output refers to index on a particular
503 * encoder.Driver uses this index to pass it to encoder when it supports more
504 * than one output. Application uses index of the array to set an output.
506 static struct vpbe_output dm365evm_vpbe_outputs[] = {
511 .type = V4L2_OUTPUT_TYPE_ANALOG,
513 .capabilities = V4L2_OUT_CAP_STD,
515 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
516 .default_mode = "ntsc",
517 .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
518 .modes = dm365evm_enc_std_timing,
519 .if_params = MEDIA_BUS_FMT_FIXED,
525 .type = V4L2_OUTPUT_TYPE_ANALOG,
526 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
528 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
529 .default_mode = "480p59_94",
530 .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
531 .modes = dm365evm_enc_preset_timing,
532 .if_params = MEDIA_BUS_FMT_FIXED,
537 * Amplifiers on the board
539 static struct ths7303_platform_data ths7303_pdata = {
545 static struct amp_config_info vpbe_amp = {
546 .module_name = "ths7303",
549 I2C_BOARD_INFO("ths7303", 0x2c),
550 .platform_data = &ths7303_pdata,
554 static struct vpbe_config dm365evm_display_cfg = {
555 .module_name = "dm365-vpbe-display",
559 .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
562 .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
564 .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
565 .outputs = dm365evm_vpbe_outputs,
568 static void __init evm_init_i2c(void)
570 davinci_init_i2c(&i2c_pdata);
571 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
574 static inline int have_leds(void)
576 #ifdef CONFIG_LEDS_CLASS
584 struct led_classdev cdev;
588 static const struct {
592 { "dm365evm::ds2", },
593 { "dm365evm::ds3", },
594 { "dm365evm::ds4", },
595 { "dm365evm::ds5", },
596 { "dm365evm::ds6", "nand-disk", },
597 { "dm365evm::ds7", "mmc1", },
598 { "dm365evm::ds8", "mmc0", },
599 { "dm365evm::ds9", "heartbeat", },
602 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
604 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
605 u8 reg = __raw_readb(cpld + CPLD_LEDS);
611 __raw_writeb(reg, cpld + CPLD_LEDS);
614 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
616 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
617 u8 reg = __raw_readb(cpld + CPLD_LEDS);
619 return (reg & led->mask) ? LED_OFF : LED_FULL;
622 static int __init cpld_leds_init(void)
626 if (!have_leds() || !cpld)
630 __raw_writeb(0xff, cpld + CPLD_LEDS);
631 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
632 struct cpld_led *led;
634 led = kzalloc(sizeof(*led), GFP_KERNEL);
638 led->cdev.name = cpld_leds[i].name;
639 led->cdev.brightness_set = cpld_led_set;
640 led->cdev.brightness_get = cpld_led_get;
641 led->cdev.default_trigger = cpld_leds[i].trigger;
644 if (led_classdev_register(NULL, &led->cdev) < 0) {
652 /* run after subsys_initcall() for LEDs */
653 fs_initcall(cpld_leds_init);
656 static void __init evm_init_cpld(void)
660 struct clk *aemif_clk;
663 /* Make sure we can configure the CPLD through CS1. Then
664 * leave it on for later access to MMC and LED registers.
666 aemif_clk = clk_get(NULL, "aemif");
667 if (IS_ERR(aemif_clk))
669 clk_prepare_enable(aemif_clk);
671 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
674 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
676 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
679 pr_err("ERROR: can't map CPLD\n");
680 clk_disable_unprepare(aemif_clk);
684 /* External muxing for some signals */
687 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
688 * NOTE: SW4 bus width setting must match!
690 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
691 /* external keypad mux */
694 rc = platform_device_register(&davinci_aemif_device);
696 pr_warn("%s(): error registering the aemif device: %d\n",
699 /* no OneNAND support yet */
702 /* Leave external chips in reset when unused. */
703 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
705 /* Static video input config with SN74CBT16214 1-of-3 mux:
706 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
707 * - port b2 == imager (mux lowbits == 2 or 7)
708 * - port b3 == tvp5146 (mux lowbits == 5)
710 * Runtime switching could work too, with limitations.
716 /* externally mux MMC1/ENET/AIC33 to imager */
717 mux |= BIT(6) | BIT(5) | BIT(3);
719 struct davinci_soc_info *soc_info = &davinci_soc_info;
721 /* we can use MMC1 ... */
722 dm365evm_mmc_configure();
723 davinci_setup_mmc(1, &dm365evm_mmc_config);
725 /* ... and ENET ... */
726 dm365evm_emac_configure();
727 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
733 if (have_tvp7002()) {
736 label = "tvp7002 HD";
738 /* default to tvp5146 */
741 label = "tvp5146 SD";
744 __raw_writeb(mux, cpld + CPLD_MUX);
745 __raw_writeb(resets, cpld + CPLD_RESETS);
746 pr_info("EVM: %s video input\n", label);
748 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
751 static void __init dm365_evm_map_io(void)
756 static struct spi_eeprom at25640 = {
757 .byte_len = SZ_64K / 8,
763 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
766 .platform_data = &at25640,
767 .max_speed_hz = 10 * 1000 * 1000,
774 static __init void dm365_evm_init(void)
778 dm365_register_clocks();
780 ret = dm365_gpio_register();
782 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
785 davinci_serial_init(dm365_serial_device);
787 dm365evm_emac_configure();
788 dm365evm_mmc_configure();
790 davinci_setup_mmc(0, &dm365evm_mmc_config);
792 dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
794 /* maybe setup mmc1/etc ... _after_ mmc0 */
797 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
799 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
803 dm365_init_ks(&dm365evm_ks_data);
805 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
806 ARRAY_SIZE(dm365_evm_spi_info));
809 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
810 .atag_offset = 0x100,
811 .map_io = dm365_evm_map_io,
812 .init_irq = davinci_irq_init,
813 .init_time = dm365_init_time,
814 .init_machine = dm365_evm_init,
815 .init_late = davinci_init_late,
816 .dma_zone_size = SZ_128M,