2 * TI DaVinci DM365 EVM board support
4 * Copyright (C) 2009 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
20 #include <linux/clk.h>
21 #include <linux/property.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/rawnand.h>
27 #include <linux/nvmem-provider.h>
28 #include <linux/input.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/eeprom.h>
31 #include <linux/v4l2-dv-timings.h>
32 #include <linux/platform_data/ti-aemif.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
38 #include <mach/common.h>
39 #include <linux/platform_data/i2c-davinci.h>
40 #include <mach/serial.h>
41 #include <linux/platform_data/mmc-davinci.h>
42 #include <linux/platform_data/mtd-davinci.h>
43 #include <linux/platform_data/keyscan-davinci.h>
45 #include <media/i2c/ths7303.h>
46 #include <media/i2c/tvp514x.h>
50 static inline int have_imager(void)
52 /* REVISIT when it's supported, trigger via Kconfig */
56 static inline int have_tvp7002(void)
58 /* REVISIT when it's supported, trigger via Kconfig */
62 #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
64 * A MAX-II CPLD is used for various board control functions.
66 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
68 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
69 #define CPLD_TEST CPLD_OFFSET(0,1)
70 #define CPLD_LEDS CPLD_OFFSET(0,2)
71 #define CPLD_MUX CPLD_OFFSET(0,3)
72 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
73 #define CPLD_POWER CPLD_OFFSET(1,1)
74 #define CPLD_VIDEO CPLD_OFFSET(1,2)
75 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
77 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
78 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
80 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
81 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
82 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
83 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
84 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
85 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
86 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
87 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
88 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
90 #define CPLD_RESETS CPLD_OFFSET(4,3)
92 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
93 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
94 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
95 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
96 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
97 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
99 static void __iomem *cpld;
102 /* NOTE: this is geared for the standard config, with a socketed
103 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
104 * swap chips with a different block size, partitioning will
105 * need to be changed. This NAND chip MT29F16G08FAA is the default
106 * NAND shipped with the Spectrum Digital DM365 EVM
108 #define NAND_BLOCK_SIZE SZ_128K
110 static struct mtd_partition davinci_nand_partitions[] = {
112 /* UBL (a few copies) plus U-Boot */
113 .name = "bootloader",
115 .size = 30 * NAND_BLOCK_SIZE,
116 .mask_flags = MTD_WRITEABLE, /* force read-only */
118 /* U-Boot environment */
120 .offset = MTDPART_OFS_APPEND,
121 .size = 2 * NAND_BLOCK_SIZE,
125 .offset = MTDPART_OFS_APPEND,
129 .name = "filesystem1",
130 .offset = MTDPART_OFS_APPEND,
134 .name = "filesystem2",
135 .offset = MTDPART_OFS_APPEND,
136 .size = MTDPART_SIZ_FULL,
139 /* two blocks with bad block table (and mirror) at the end */
142 static struct davinci_nand_pdata davinci_nand_data = {
144 .mask_chipsel = BIT(14),
145 .parts = davinci_nand_partitions,
146 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
147 .ecc_mode = NAND_ECC_HW,
148 .bbt_options = NAND_BBT_USE_FLASH,
152 static struct resource davinci_nand_resources[] = {
154 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
155 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
156 .flags = IORESOURCE_MEM,
158 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
159 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
160 .flags = IORESOURCE_MEM,
164 static struct platform_device davinci_aemif_devices[] = {
166 .name = "davinci_nand",
168 .num_resources = ARRAY_SIZE(davinci_nand_resources),
169 .resource = davinci_nand_resources,
171 .platform_data = &davinci_nand_data,
176 static struct resource davinci_aemif_resources[] = {
178 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
179 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
180 .flags = IORESOURCE_MEM,
184 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
190 static struct aemif_platform_data davinci_aemif_pdata = {
191 .abus_data = da850_evm_aemif_abus_data,
192 .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
193 .sub_devices = davinci_aemif_devices,
194 .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
197 static struct platform_device davinci_aemif_device = {
201 .platform_data = &davinci_aemif_pdata,
203 .resource = davinci_aemif_resources,
204 .num_resources = ARRAY_SIZE(davinci_aemif_resources),
207 static struct nvmem_cell_info davinci_nvmem_cells[] = {
215 static struct nvmem_cell_table davinci_nvmem_cell_table = {
216 .nvmem_name = "1-00500",
217 .cells = davinci_nvmem_cells,
218 .ncells = ARRAY_SIZE(davinci_nvmem_cells),
221 static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
222 .nvmem_name = "1-00500",
223 .cell_name = "macaddr",
224 .dev_id = "davinci_emac.1",
225 .con_id = "mac-address",
228 static const struct property_entry eeprom_properties[] = {
229 PROPERTY_ENTRY_U32("pagesize", 64),
233 static struct i2c_board_info i2c_info[] = {
235 I2C_BOARD_INFO("24c256", 0x50),
236 .properties = eeprom_properties,
239 I2C_BOARD_INFO("tlv320aic3x", 0x18),
243 static struct davinci_i2c_platform_data i2c_pdata = {
244 .bus_freq = 400 /* kHz */,
245 .bus_delay = 0 /* usec */,
248 static int dm365evm_keyscan_enable(struct device *dev)
250 return davinci_cfg_reg(DM365_KEYSCAN);
253 static unsigned short dm365evm_keymap[] = {
273 static struct davinci_ks_platform_data dm365evm_ks_data = {
274 .device_enable = dm365evm_keyscan_enable,
275 .keymap = dm365evm_keymap,
276 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
278 /* Scan period = strobe + interval */
281 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
284 static int cpld_mmc_get_cd(int module)
289 /* low == card present */
290 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
293 static int cpld_mmc_get_ro(int module)
298 /* high == card's write protect switch active */
299 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
302 static struct davinci_mmc_config dm365evm_mmc_config = {
303 .get_cd = cpld_mmc_get_cd,
304 .get_ro = cpld_mmc_get_ro,
306 .max_freq = 50000000,
307 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
310 static void dm365evm_emac_configure(void)
313 * EMAC pins are multiplexed with GPIO and UART
314 * Further details are available at the DM365 ARM
315 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
317 davinci_cfg_reg(DM365_EMAC_TX_EN);
318 davinci_cfg_reg(DM365_EMAC_TX_CLK);
319 davinci_cfg_reg(DM365_EMAC_COL);
320 davinci_cfg_reg(DM365_EMAC_TXD3);
321 davinci_cfg_reg(DM365_EMAC_TXD2);
322 davinci_cfg_reg(DM365_EMAC_TXD1);
323 davinci_cfg_reg(DM365_EMAC_TXD0);
324 davinci_cfg_reg(DM365_EMAC_RXD3);
325 davinci_cfg_reg(DM365_EMAC_RXD2);
326 davinci_cfg_reg(DM365_EMAC_RXD1);
327 davinci_cfg_reg(DM365_EMAC_RXD0);
328 davinci_cfg_reg(DM365_EMAC_RX_CLK);
329 davinci_cfg_reg(DM365_EMAC_RX_DV);
330 davinci_cfg_reg(DM365_EMAC_RX_ER);
331 davinci_cfg_reg(DM365_EMAC_CRS);
332 davinci_cfg_reg(DM365_EMAC_MDIO);
333 davinci_cfg_reg(DM365_EMAC_MDCLK);
336 * EMAC interrupts are multiplexed with GPIO interrupts
337 * Details are available at the DM365 ARM
338 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
340 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
341 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
342 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
343 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
346 static void dm365evm_mmc_configure(void)
349 * MMC/SD pins are multiplexed with GPIO and EMIF
350 * Further details are available at the DM365 ARM
351 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
353 davinci_cfg_reg(DM365_SD1_CLK);
354 davinci_cfg_reg(DM365_SD1_CMD);
355 davinci_cfg_reg(DM365_SD1_DATA3);
356 davinci_cfg_reg(DM365_SD1_DATA2);
357 davinci_cfg_reg(DM365_SD1_DATA1);
358 davinci_cfg_reg(DM365_SD1_DATA0);
361 static struct tvp514x_platform_data tvp5146_pdata = {
367 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
368 /* Inputs available at the TVP5146 */
369 static struct v4l2_input tvp5146_inputs[] = {
373 .type = V4L2_INPUT_TYPE_CAMERA,
374 .std = TVP514X_STD_ALL,
379 .type = V4L2_INPUT_TYPE_CAMERA,
380 .std = TVP514X_STD_ALL,
385 * this is the route info for connecting each input to decoder
386 * ouput that goes to vpfe. There is a one to one correspondence
387 * with tvp5146_inputs
389 static struct vpfe_route tvp5146_routes[] = {
391 .input = INPUT_CVBS_VI2B,
392 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
395 .input = INPUT_SVIDEO_VI2C_VI1C,
396 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
400 static struct vpfe_subdev_info vpfe_sub_devs[] = {
404 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
405 .inputs = tvp5146_inputs,
406 .routes = tvp5146_routes,
409 .if_type = VPFE_BT656,
410 .hdpol = VPFE_PINPOL_POSITIVE,
411 .vdpol = VPFE_PINPOL_POSITIVE,
414 I2C_BOARD_INFO("tvp5146", 0x5d),
415 .platform_data = &tvp5146_pdata,
420 static struct vpfe_config vpfe_cfg = {
421 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
422 .sub_devs = vpfe_sub_devs,
424 .card_name = "DM365 EVM",
428 /* venc standards timings */
429 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
432 .timings_type = VPBE_ENC_STD,
433 .std_id = V4L2_STD_NTSC,
438 .fps = {30000, 1001},
440 .upper_margin = 0x10,
444 .timings_type = VPBE_ENC_STD,
445 .std_id = V4L2_STD_PAL,
452 .upper_margin = 0x16,
456 /* venc dv timings */
457 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
460 .timings_type = VPBE_ENC_DV_TIMINGS,
461 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
468 .upper_margin = 0x2D,
472 .timings_type = VPBE_ENC_DV_TIMINGS,
473 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
480 .upper_margin = 0x36,
484 .timings_type = VPBE_ENC_DV_TIMINGS,
485 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
491 .left_margin = 0x117,
500 .timings_type = VPBE_ENC_DV_TIMINGS,
501 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
516 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
519 * The outputs available from VPBE + ecnoders. Keep the
520 * the order same as that of encoders. First those from venc followed by that
521 * from encoders. Index in the output refers to index on a particular
522 * encoder.Driver uses this index to pass it to encoder when it supports more
523 * than one output. Application uses index of the array to set an output.
525 static struct vpbe_output dm365evm_vpbe_outputs[] = {
530 .type = V4L2_OUTPUT_TYPE_ANALOG,
532 .capabilities = V4L2_OUT_CAP_STD,
534 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
535 .default_mode = "ntsc",
536 .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
537 .modes = dm365evm_enc_std_timing,
538 .if_params = MEDIA_BUS_FMT_FIXED,
544 .type = V4L2_OUTPUT_TYPE_ANALOG,
545 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
547 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
548 .default_mode = "480p59_94",
549 .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
550 .modes = dm365evm_enc_preset_timing,
551 .if_params = MEDIA_BUS_FMT_FIXED,
556 * Amplifiers on the board
558 static struct ths7303_platform_data ths7303_pdata = {
564 static struct amp_config_info vpbe_amp = {
565 .module_name = "ths7303",
568 I2C_BOARD_INFO("ths7303", 0x2c),
569 .platform_data = &ths7303_pdata,
573 static struct vpbe_config dm365evm_display_cfg = {
574 .module_name = "dm365-vpbe-display",
578 .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
581 .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
583 .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
584 .outputs = dm365evm_vpbe_outputs,
587 static void __init evm_init_i2c(void)
589 davinci_init_i2c(&i2c_pdata);
590 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
593 static inline int have_leds(void)
595 #ifdef CONFIG_LEDS_CLASS
603 struct led_classdev cdev;
607 static const struct {
611 { "dm365evm::ds2", },
612 { "dm365evm::ds3", },
613 { "dm365evm::ds4", },
614 { "dm365evm::ds5", },
615 { "dm365evm::ds6", "nand-disk", },
616 { "dm365evm::ds7", "mmc1", },
617 { "dm365evm::ds8", "mmc0", },
618 { "dm365evm::ds9", "heartbeat", },
621 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
623 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
624 u8 reg = __raw_readb(cpld + CPLD_LEDS);
630 __raw_writeb(reg, cpld + CPLD_LEDS);
633 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
635 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
636 u8 reg = __raw_readb(cpld + CPLD_LEDS);
638 return (reg & led->mask) ? LED_OFF : LED_FULL;
641 static int __init cpld_leds_init(void)
645 if (!have_leds() || !cpld)
649 __raw_writeb(0xff, cpld + CPLD_LEDS);
650 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
651 struct cpld_led *led;
653 led = kzalloc(sizeof(*led), GFP_KERNEL);
657 led->cdev.name = cpld_leds[i].name;
658 led->cdev.brightness_set = cpld_led_set;
659 led->cdev.brightness_get = cpld_led_get;
660 led->cdev.default_trigger = cpld_leds[i].trigger;
663 if (led_classdev_register(NULL, &led->cdev) < 0) {
671 /* run after subsys_initcall() for LEDs */
672 fs_initcall(cpld_leds_init);
675 static void __init evm_init_cpld(void)
679 struct clk *aemif_clk;
682 /* Make sure we can configure the CPLD through CS1. Then
683 * leave it on for later access to MMC and LED registers.
685 aemif_clk = clk_get(NULL, "aemif");
686 if (IS_ERR(aemif_clk))
688 clk_prepare_enable(aemif_clk);
690 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
693 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
695 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
698 pr_err("ERROR: can't map CPLD\n");
699 clk_disable_unprepare(aemif_clk);
703 /* External muxing for some signals */
706 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
707 * NOTE: SW4 bus width setting must match!
709 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
710 /* external keypad mux */
713 rc = platform_device_register(&davinci_aemif_device);
715 pr_warn("%s(): error registering the aemif device: %d\n",
718 /* no OneNAND support yet */
721 /* Leave external chips in reset when unused. */
722 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
724 /* Static video input config with SN74CBT16214 1-of-3 mux:
725 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
726 * - port b2 == imager (mux lowbits == 2 or 7)
727 * - port b3 == tvp5146 (mux lowbits == 5)
729 * Runtime switching could work too, with limitations.
735 /* externally mux MMC1/ENET/AIC33 to imager */
736 mux |= BIT(6) | BIT(5) | BIT(3);
738 struct davinci_soc_info *soc_info = &davinci_soc_info;
740 /* we can use MMC1 ... */
741 dm365evm_mmc_configure();
742 davinci_setup_mmc(1, &dm365evm_mmc_config);
744 /* ... and ENET ... */
745 dm365evm_emac_configure();
746 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
752 if (have_tvp7002()) {
755 label = "tvp7002 HD";
757 /* default to tvp5146 */
760 label = "tvp5146 SD";
763 __raw_writeb(mux, cpld + CPLD_MUX);
764 __raw_writeb(resets, cpld + CPLD_RESETS);
765 pr_info("EVM: %s video input\n", label);
767 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
770 static void __init dm365_evm_map_io(void)
775 static struct spi_eeprom at25640 = {
776 .byte_len = SZ_64K / 8,
782 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
785 .platform_data = &at25640,
786 .max_speed_hz = 10 * 1000 * 1000,
793 static __init void dm365_evm_init(void)
797 dm365_register_clocks();
799 ret = dm365_gpio_register();
801 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
803 nvmem_add_cell_table(&davinci_nvmem_cell_table);
804 nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
807 davinci_serial_init(dm365_serial_device);
809 dm365evm_emac_configure();
810 dm365evm_mmc_configure();
812 davinci_setup_mmc(0, &dm365evm_mmc_config);
814 dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
816 /* maybe setup mmc1/etc ... _after_ mmc0 */
819 #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
821 #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
825 dm365_init_ks(&dm365evm_ks_data);
827 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
828 ARRAY_SIZE(dm365_evm_spi_info));
831 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
832 .atag_offset = 0x100,
833 .map_io = dm365_evm_map_io,
834 .init_irq = dm365_init_irq,
835 .init_time = dm365_init_time,
836 .init_machine = dm365_evm_init,
837 .init_late = davinci_init_late,
838 .dma_zone_size = SZ_128M,