1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
4 * Copyright 2014 Linaro Limited
7 #include <linux/cpumask.h>
8 #include <linux/delay.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
12 #include <linux/irqchip/irq-bcm2836.h>
13 #include <linux/jiffies.h>
15 #include <linux/of_address.h>
16 #include <linux/sched.h>
17 #include <linux/sched/clock.h>
18 #include <linux/smp.h>
20 #include <asm/cacheflush.h>
22 #include <asm/smp_plat.h>
23 #include <asm/smp_scu.h>
25 /* Size of mapped Cortex A9 SCU address space */
26 #define CORTEX_A9_SCU_SIZE 0x58
28 #define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
29 #define BOOT_ADDR_CPUID_MASK 0x3
31 /* Name of device node property defining secondary boot register location */
32 #define OF_SECONDARY_BOOT "secondary-boot-reg"
33 #define MPIDR_CPUID_BITMASK 0x3
36 * Enable the Cortex A9 Snoop Control Unit
38 * By the time this is called we already know there are multiple
39 * cores present. We assume we're running on a Cortex A9 processor,
40 * so any trouble getting the base address register or getting the
41 * SCU base is a problem.
43 * Return 0 if successful or an error code otherwise.
45 static int __init scu_a9_enable(void)
47 unsigned long config_base;
48 void __iomem *scu_base;
50 if (!scu_a9_has_base()) {
51 pr_err("no configuration base address register!\n");
55 /* Config base address register value is zero for uniprocessor */
56 config_base = scu_a9_get_base();
58 pr_err("hardware reports only one core\n");
62 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
64 pr_err("failed to remap config base (%lu/%u) for SCU\n",
65 config_base, CORTEX_A9_SCU_SIZE);
71 iounmap(scu_base); /* That's the last we'll need of this */
76 static u32 secondary_boot_addr_for(unsigned int cpu)
78 u32 secondary_boot_addr = 0;
79 struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
82 pr_err("Failed to find device tree node for CPU%u\n", cpu);
86 if (of_property_read_u32(cpu_node,
88 &secondary_boot_addr))
89 pr_err("required secondary boot register not specified for CPU%u\n",
92 of_node_put(cpu_node);
94 return secondary_boot_addr;
97 static int nsp_write_lut(unsigned int cpu)
99 void __iomem *sku_rom_lut;
100 phys_addr_t secondary_startup_phy;
101 const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
103 if (!secondary_boot_addr)
106 sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
107 sizeof(phys_addr_t));
109 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
113 secondary_startup_phy = __pa_symbol(secondary_startup);
114 BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
116 writel_relaxed(secondary_startup_phy, sku_rom_lut);
118 /* Ensure the write is visible to the secondary core */
121 iounmap(sku_rom_lut);
126 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
128 const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
130 /* Enable the SCU on Cortex A9 based SoCs */
131 if (scu_a9_enable()) {
132 /* Update the CPU present map to reflect uniprocessor mode */
133 pr_warn("failed to enable A9 SCU - disabling SMP\n");
134 init_cpu_present(&only_cpu_0);
139 * The ROM code has the secondary cores looping, waiting for an event.
140 * When an event occurs each core examines the bottom two bits of the
141 * secondary boot register. When a core finds those bits contain its
142 * own core id, it performs initialization, including computing its boot
143 * address by clearing the boot register value's bottom two bits. The
144 * core signals that it is beginning its execution by writing its boot
145 * address back to the secondary boot register, and finally jumps to
148 * So to start a core executing we need to:
149 * - Encode the (hardware) CPU id with the bottom bits of the secondary
151 * - Write that value into the secondary boot register.
152 * - Generate an event to wake up the secondary CPU(s).
153 * - Wait for the secondary boot register to be re-written, which
154 * indicates the secondary core has started.
156 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
158 void __iomem *boot_reg;
159 phys_addr_t boot_func;
163 bool timeout = false;
164 const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
166 cpu_id = cpu_logical_map(cpu);
167 if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
168 pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
172 if (!secondary_boot_addr)
175 boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
176 sizeof(phys_addr_t));
178 pr_err("unable to map boot register for cpu %u\n", cpu_id);
183 * Secondary cores will start in secondary_startup(),
184 * defined in "arch/arm/kernel/head.S"
186 boot_func = __pa_symbol(secondary_startup);
187 BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
188 BUG_ON(boot_func > (phys_addr_t)U32_MAX);
190 /* The core to start is encoded in the low bits */
191 boot_val = (u32)boot_func | cpu_id;
192 writel_relaxed(boot_val, boot_reg);
196 /* The low bits will be cleared once the core has started */
197 start_clock = local_clock();
198 while (!timeout && readl_relaxed(boot_reg) == boot_val)
199 timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
206 pr_err("timeout waiting for cpu %u to start\n", cpu_id);
211 /* Cluster Dormant Control command to bring CPU into a running state */
213 #define CDC_CMD_OFFSET 0
214 #define CDC_CMD_REG(cpu) (CDC_CMD_OFFSET + 4*(cpu))
217 * BCM23550 has a Cluster Dormant Control block that keeps the core in
218 * idle state. A command needs to be sent to the block to bring the CPU
219 * into running state.
221 static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle)
223 void __iomem *cdc_base;
224 struct device_node *dn;
228 /* Make sure a CDC node exists before booting the
231 name = "brcm,bcm23550-cdc";
232 dn = of_find_compatible_node(NULL, NULL, name);
234 pr_err("unable to find cdc node\n");
238 cdc_base = of_iomap(dn, 0);
242 pr_err("unable to remap cdc base register\n");
246 /* Boot the secondary core */
247 ret = kona_boot_secondary(cpu, idle);
251 /* Bring this CPU to RUN state so that nIRQ nFIQ
252 * signals are unblocked.
254 writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
262 static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
267 * After wake up, secondary core branches to the startup
268 * address programmed at SKU ROM LUT location.
270 ret = nsp_write_lut(cpu);
272 pr_err("unable to write startup addr to SKU ROM LUT\n");
276 /* Send a CPU wakeup interrupt to the secondary core */
277 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
283 static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle)
285 void __iomem *intc_base;
286 struct device_node *dn;
289 name = "brcm,bcm2836-l1-intc";
290 dn = of_find_compatible_node(NULL, NULL, name);
292 pr_err("unable to find intc node\n");
296 intc_base = of_iomap(dn, 0);
300 pr_err("unable to remap intc base register\n");
304 writel(virt_to_phys(secondary_startup),
305 intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
315 static const struct smp_operations kona_smp_ops __initconst = {
316 .smp_prepare_cpus = bcm_smp_prepare_cpus,
317 .smp_boot_secondary = kona_boot_secondary,
319 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
322 static const struct smp_operations bcm23550_smp_ops __initconst = {
323 .smp_boot_secondary = bcm23550_boot_secondary,
325 CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
328 static const struct smp_operations nsp_smp_ops __initconst = {
329 .smp_prepare_cpus = bcm_smp_prepare_cpus,
330 .smp_boot_secondary = nsp_boot_secondary,
332 CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
334 const struct smp_operations bcm2836_smp_ops __initconst = {
335 .smp_boot_secondary = bcm2836_boot_secondary,
337 CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);