1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/parser.h>
15 #include <linux/suspend.h>
17 #include <linux/clk/at91_pmc.h>
18 #include <linux/platform_data/atmel.h>
20 #include <asm/cacheflush.h>
21 #include <asm/fncpy.h>
22 #include <asm/system_misc.h>
23 #include <asm/suspend.h>
29 * FIXME: this is needed to communicate between the pinctrl driver and
30 * the PM implementation in the machine. Possibly part of the PM
31 * implementation should be moved down into the pinctrl driver and get
32 * called as part of the generic suspend/resume path.
34 #ifdef CONFIG_PINCTRL_AT91
35 extern void at91_pinctrl_gpio_suspend(void);
36 extern void at91_pinctrl_gpio_resume(void);
40 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
41 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
42 const struct of_device_id *ws_ids;
43 struct at91_pm_data data;
46 static struct at91_soc_pm soc_pm = {
48 .standby_mode = AT91_PM_STANDBY,
49 .suspend_mode = AT91_PM_ULP0,
53 static const match_table_t pm_modes __initconst = {
54 { AT91_PM_STANDBY, "standby" },
55 { AT91_PM_ULP0, "ulp0" },
56 { AT91_PM_ULP0_FAST, "ulp0-fast" },
57 { AT91_PM_ULP1, "ulp1" },
58 { AT91_PM_BACKUP, "backup" },
62 #define at91_ramc_read(id, field) \
63 __raw_readl(soc_pm.data.ramc[id] + field)
65 #define at91_ramc_write(id, field, value) \
66 __raw_writel(value, soc_pm.data.ramc[id] + field)
68 static int at91_pm_valid_state(suspend_state_t state)
72 case PM_SUSPEND_STANDBY:
81 static int canary = 0xA5A5A5A5;
83 static struct at91_pm_bu {
85 unsigned long reserved;
90 struct wakeup_source_info {
91 unsigned int pmc_fsmr_bit;
92 unsigned int shdwc_mr_bit;
96 static const struct wakeup_source_info ws_info[] = {
97 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
98 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
99 { .pmc_fsmr_bit = AT91_PMC_USBAL },
100 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
101 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
102 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
105 static const struct of_device_id sama5d2_ws_ids[] = {
106 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
107 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
108 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
109 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
110 { .compatible = "usb-ohci", .data = &ws_info[2] },
111 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
112 { .compatible = "usb-ehci", .data = &ws_info[2] },
113 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
117 static const struct of_device_id sam9x60_ws_ids[] = {
118 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
119 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
120 { .compatible = "usb-ohci", .data = &ws_info[2] },
121 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
122 { .compatible = "usb-ehci", .data = &ws_info[2] },
123 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
124 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
128 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
130 const struct wakeup_source_info *wsi;
131 const struct of_device_id *match;
132 struct platform_device *pdev;
133 struct device_node *np;
134 unsigned int mode = 0, polarity = 0, val = 0;
136 if (pm_mode != AT91_PM_ULP1)
139 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
143 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
147 if (soc_pm.config_shdwc_ws)
148 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
151 val = readl(soc_pm.data.shdwc + 0x04);
153 /* Loop through defined wakeup sources. */
154 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
155 pdev = of_find_device_by_node(np);
159 if (device_may_wakeup(&pdev->dev)) {
162 /* Check if enabled on SHDWC. */
163 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
166 mode |= wsi->pmc_fsmr_bit;
167 if (wsi->set_polarity)
168 polarity |= wsi->pmc_fsmr_bit;
172 put_device(&pdev->dev);
176 if (soc_pm.config_pmc_ws)
177 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
179 pr_err("AT91: PM: no ULP1 wakeup sources found!");
182 return mode ? 0 : -EPERM;
185 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
191 val = readl(shdwc + 0x0c);
192 *mode |= (val & 0x3ff);
193 *polarity |= ((val >> 16) & 0x3ff);
198 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
200 writel(mode, pmc + AT91_PMC_FSMR);
201 writel(polarity, pmc + AT91_PMC_FSPR);
206 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
208 writel(mode, pmc + AT91_PMC_FSMR);
214 * Called after processes are frozen, but before we shutdown devices.
216 static int at91_pm_begin(suspend_state_t state)
220 soc_pm.data.mode = soc_pm.data.suspend_mode;
223 case PM_SUSPEND_STANDBY:
224 soc_pm.data.mode = soc_pm.data.standby_mode;
228 soc_pm.data.mode = -1;
231 return at91_pm_config_ws(soc_pm.data.mode, true);
235 * Verify that all the clocks are correct before entering
238 static int at91_pm_verify_clocks(void)
243 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
245 /* USB must not be using PLLB */
246 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
247 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
251 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
252 for (i = 0; i < 4; i++) {
255 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
257 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
258 if (css != AT91_PMC_CSS_SLOW) {
259 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
268 * Call this from platform driver suspend() to see how deeply to suspend.
269 * For example, some controllers (like OHCI) need one of the PLL clocks
270 * in order to act as a wakeup source, and those are not available when
271 * going into slow clock mode.
273 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
274 * the very same problem (but not using at91 main_clk), and it'd be better
275 * to add one generic API rather than lots of platform-specific ones.
277 int at91_suspend_entering_slow_clock(void)
279 return (soc_pm.data.mode >= AT91_PM_ULP0);
281 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
283 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
284 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
285 extern u32 at91_pm_suspend_in_sram_sz;
287 static int at91_suspend_finish(unsigned long val)
292 at91_suspend_sram_fn(&soc_pm.data);
297 static void at91_pm_suspend(suspend_state_t state)
299 if (soc_pm.data.mode == AT91_PM_BACKUP) {
300 pm_bu->suspended = 1;
302 cpu_suspend(0, at91_suspend_finish);
304 /* The SRAM is lost between suspend cycles */
305 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
306 &at91_pm_suspend_in_sram,
307 at91_pm_suspend_in_sram_sz);
309 at91_suspend_finish(0);
316 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
317 * event sources; and reduces DRAM power. But otherwise it's identical to
318 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
320 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
321 * suspend more deeply, the master clock switches to the clk32k and turns off
322 * the main oscillator
324 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
326 static int at91_pm_enter(suspend_state_t state)
328 #ifdef CONFIG_PINCTRL_AT91
329 at91_pinctrl_gpio_suspend();
334 case PM_SUSPEND_STANDBY:
336 * Ensure that clocks are in a valid state.
338 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
339 !at91_pm_verify_clocks())
342 at91_pm_suspend(state);
351 pr_debug("AT91: PM - bogus suspend state %d\n", state);
356 #ifdef CONFIG_PINCTRL_AT91
357 at91_pinctrl_gpio_resume();
363 * Called right prior to thawing processes.
365 static void at91_pm_end(void)
367 at91_pm_config_ws(soc_pm.data.mode, false);
371 static const struct platform_suspend_ops at91_pm_ops = {
372 .valid = at91_pm_valid_state,
373 .begin = at91_pm_begin,
374 .enter = at91_pm_enter,
378 static struct platform_device at91_cpuidle_device = {
379 .name = "cpuidle-at91",
383 * The AT91RM9200 goes into self-refresh mode with this command, and will
384 * terminate self-refresh automatically on the next SDRAM access.
386 * Self-refresh mode is exited as soon as a memory access is made, but we don't
387 * know for sure when that happens. However, we need to restore the low-power
388 * mode if it was enabled before going idle. Restoring low-power mode while
389 * still in self-refresh is "not recommended", but seems to work.
391 static void at91rm9200_standby(void)
396 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
397 " str %2, [%1, %3]\n\t"
398 " mcr p15, 0, %0, c7, c0, 4\n\t"
400 : "r" (0), "r" (soc_pm.data.ramc[0]),
401 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
404 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
407 static void at91_ddr_standby(void)
409 /* Those two values allow us to delay self-refresh activation
412 u32 mdr, saved_mdr0, saved_mdr1 = 0;
413 u32 saved_lpr0, saved_lpr1 = 0;
415 /* LPDDR1 --> force DDR2 mode during self-refresh */
416 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
417 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
418 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
419 mdr |= AT91_DDRSDRC_MD_DDR2;
420 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
423 if (soc_pm.data.ramc[1]) {
424 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
425 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
426 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
427 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
428 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
429 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
430 mdr |= AT91_DDRSDRC_MD_DDR2;
431 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
435 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
436 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
437 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
439 /* self-refresh mode now */
440 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
441 if (soc_pm.data.ramc[1])
442 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
446 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
447 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
448 if (soc_pm.data.ramc[1]) {
449 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
450 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
454 static void sama5d3_ddr_standby(void)
459 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
460 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
461 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
463 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
467 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
470 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
473 static void at91sam9_sdram_standby(void)
476 u32 saved_lpr0, saved_lpr1 = 0;
478 if (soc_pm.data.ramc[1]) {
479 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
480 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
481 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
484 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
485 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
486 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
488 /* self-refresh mode now */
489 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
490 if (soc_pm.data.ramc[1])
491 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
495 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
496 if (soc_pm.data.ramc[1])
497 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
502 unsigned int memctrl;
505 static const struct ramc_info ramc_infos[] __initconst = {
506 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
507 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
508 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
509 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
512 static const struct of_device_id ramc_ids[] __initconst = {
513 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
514 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
515 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
516 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
520 static __init int at91_dt_ramc(void)
522 struct device_node *np;
523 const struct of_device_id *of_id;
525 void *standby = NULL;
526 const struct ramc_info *ramc;
529 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
530 soc_pm.data.ramc[idx] = of_iomap(np, 0);
531 if (!soc_pm.data.ramc[idx]) {
532 pr_err("unable to map ramc[%d] cpu registers\n", idx);
539 standby = ramc->idle;
540 soc_pm.data.memctrl = ramc->memctrl;
546 pr_err("unable to find compatible ram controller node in dtb\n");
552 pr_warn("ramc no standby function available\n");
556 at91_cpuidle_device.dev.platform_data = standby;
562 iounmap(soc_pm.data.ramc[--idx]);
567 static void at91rm9200_idle(void)
570 * Disable the processor clock. The processor will be automatically
571 * re-enabled by an interrupt or by a reset.
573 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
576 static void at91sam9_idle(void)
578 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
582 static void __init at91_pm_sram_init(void)
584 struct gen_pool *sram_pool;
585 phys_addr_t sram_pbase;
586 unsigned long sram_base;
587 struct device_node *node;
588 struct platform_device *pdev = NULL;
590 for_each_compatible_node(node, NULL, "mmio-sram") {
591 pdev = of_find_device_by_node(node);
599 pr_warn("%s: failed to find sram device!\n", __func__);
603 sram_pool = gen_pool_get(&pdev->dev, NULL);
605 pr_warn("%s: sram pool unavailable!\n", __func__);
609 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
611 pr_warn("%s: unable to alloc sram!\n", __func__);
615 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
616 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
617 at91_pm_suspend_in_sram_sz, false);
618 if (!at91_suspend_sram_fn) {
619 pr_warn("SRAM: Could not map\n");
623 /* Copy the pm suspend handler to SRAM */
624 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
625 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
629 put_device(&pdev->dev);
633 static bool __init at91_is_pm_mode_active(int pm_mode)
635 return (soc_pm.data.standby_mode == pm_mode ||
636 soc_pm.data.suspend_mode == pm_mode);
639 static int __init at91_pm_backup_init(void)
641 struct gen_pool *sram_pool;
642 struct device_node *np;
643 struct platform_device *pdev = NULL;
646 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
649 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
652 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
654 pr_warn("%s: failed to find sfrbu!\n", __func__);
658 soc_pm.data.sfrbu = of_iomap(np, 0);
661 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
663 goto securam_fail_no_ref_dev;
665 pdev = of_find_device_by_node(np);
668 pr_warn("%s: failed to find securam device!\n", __func__);
669 goto securam_fail_no_ref_dev;
672 sram_pool = gen_pool_get(&pdev->dev, NULL);
674 pr_warn("%s: securam pool unavailable!\n", __func__);
678 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
680 pr_warn("%s: unable to alloc securam!\n", __func__);
685 pm_bu->suspended = 0;
686 pm_bu->canary = __pa_symbol(&canary);
687 pm_bu->resume = __pa_symbol(cpu_resume);
692 put_device(&pdev->dev);
693 securam_fail_no_ref_dev:
694 iounmap(soc_pm.data.sfrbu);
695 soc_pm.data.sfrbu = NULL;
699 static void __init at91_pm_use_default_mode(int pm_mode)
701 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
704 if (soc_pm.data.standby_mode == pm_mode)
705 soc_pm.data.standby_mode = AT91_PM_ULP0;
706 if (soc_pm.data.suspend_mode == pm_mode)
707 soc_pm.data.suspend_mode = AT91_PM_ULP0;
710 static const struct of_device_id atmel_shdwc_ids[] = {
711 { .compatible = "atmel,sama5d2-shdwc" },
712 { .compatible = "microchip,sam9x60-shdwc" },
716 static void __init at91_pm_modes_init(void)
718 struct device_node *np;
721 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
722 !at91_is_pm_mode_active(AT91_PM_ULP1))
725 np = of_find_matching_node(NULL, atmel_shdwc_ids);
727 pr_warn("%s: failed to find shdwc!\n", __func__);
731 soc_pm.data.shdwc = of_iomap(np, 0);
734 ret = at91_pm_backup_init();
736 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
745 iounmap(soc_pm.data.shdwc);
746 soc_pm.data.shdwc = NULL;
748 at91_pm_use_default_mode(AT91_PM_ULP1);
750 at91_pm_use_default_mode(AT91_PM_BACKUP);
754 unsigned long uhp_udp_mask;
756 unsigned long version;
759 static const struct pmc_info pmc_infos[] __initconst = {
761 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
763 .version = AT91_PMC_V1,
767 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
769 .version = AT91_PMC_V1,
772 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
774 .version = AT91_PMC_V1,
778 .version = AT91_PMC_V1,
781 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
783 .version = AT91_PMC_V2,
787 static const struct of_device_id atmel_pmc_ids[] __initconst = {
788 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
789 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
790 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
791 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
792 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
793 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
794 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
795 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
796 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
797 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
798 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
799 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
803 static void __init at91_pm_modes_validate(const int *modes, int len)
805 u8 i, standby = 0, suspend = 0;
808 for (i = 0; i < len; i++) {
809 if (standby && suspend)
812 if (modes[i] == soc_pm.data.standby_mode && !standby) {
817 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
824 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
827 mode = AT91_PM_STANDBY;
829 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
830 pm_modes[soc_pm.data.standby_mode].pattern,
831 pm_modes[mode].pattern);
832 soc_pm.data.standby_mode = mode;
836 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
837 mode = AT91_PM_STANDBY;
841 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
842 pm_modes[soc_pm.data.suspend_mode].pattern,
843 pm_modes[mode].pattern);
844 soc_pm.data.suspend_mode = mode;
848 static void __init at91_pm_init(void (*pm_idle)(void))
850 struct device_node *pmc_np;
851 const struct of_device_id *of_id;
852 const struct pmc_info *pmc;
854 if (at91_cpuidle_device.dev.platform_data)
855 platform_device_register(&at91_cpuidle_device);
857 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
858 soc_pm.data.pmc = of_iomap(pmc_np, 0);
860 if (!soc_pm.data.pmc) {
861 pr_err("AT91: PM not supported, PMC not found\n");
866 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
867 soc_pm.data.pmc_mckr_offset = pmc->mckr;
868 soc_pm.data.pmc_version = pmc->version;
871 arm_pm_idle = pm_idle;
875 if (at91_suspend_sram_fn) {
876 suspend_set_ops(&at91_pm_ops);
877 pr_info("AT91: PM: standby: %s, suspend: %s\n",
878 pm_modes[soc_pm.data.standby_mode].pattern,
879 pm_modes[soc_pm.data.suspend_mode].pattern);
881 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
885 void __init at91rm9200_pm_init(void)
889 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
893 * Force STANDBY and ULP0 mode to avoid calling
894 * at91_pm_modes_validate() which may increase booting time.
895 * Platform supports anyway only STANDBY and ULP0 modes.
897 soc_pm.data.standby_mode = AT91_PM_STANDBY;
898 soc_pm.data.suspend_mode = AT91_PM_ULP0;
900 ret = at91_dt_ramc();
905 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
907 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
909 at91_pm_init(at91rm9200_idle);
912 void __init sam9x60_pm_init(void)
914 static const int modes[] __initconst = {
915 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
919 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
922 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
923 at91_pm_modes_init();
924 ret = at91_dt_ramc();
930 soc_pm.ws_ids = sam9x60_ws_ids;
931 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
934 void __init at91sam9_pm_init(void)
938 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
942 * Force STANDBY and ULP0 mode to avoid calling
943 * at91_pm_modes_validate() which may increase booting time.
944 * Platform supports anyway only STANDBY and ULP0 modes.
946 soc_pm.data.standby_mode = AT91_PM_STANDBY;
947 soc_pm.data.suspend_mode = AT91_PM_ULP0;
949 ret = at91_dt_ramc();
953 at91_pm_init(at91sam9_idle);
956 void __init sama5_pm_init(void)
958 static const int modes[] __initconst = {
959 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
963 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
966 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
967 ret = at91_dt_ramc();
974 void __init sama5d2_pm_init(void)
976 static const int modes[] __initconst = {
977 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
982 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
985 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
986 at91_pm_modes_init();
987 ret = at91_dt_ramc();
993 soc_pm.ws_ids = sama5d2_ws_ids;
994 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
995 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
998 static int __init at91_pm_modes_select(char *str)
1001 substring_t args[MAX_OPT_ARGS];
1002 int standby, suspend;
1007 s = strsep(&str, ",");
1008 standby = match_token(s, pm_modes, args);
1012 suspend = match_token(str, pm_modes, args);
1016 soc_pm.data.standby_mode = standby;
1017 soc_pm.data.suspend_mode = suspend;
1021 early_param("atmel.pm_modes", at91_pm_modes_select);