1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/parser.h>
15 #include <linux/suspend.h>
17 #include <linux/clk/at91_pmc.h>
18 #include <linux/platform_data/atmel.h>
20 #include <asm/cacheflush.h>
21 #include <asm/fncpy.h>
22 #include <asm/system_misc.h>
23 #include <asm/suspend.h>
29 * FIXME: this is needed to communicate between the pinctrl driver and
30 * the PM implementation in the machine. Possibly part of the PM
31 * implementation should be moved down into the pinctrl driver and get
32 * called as part of the generic suspend/resume path.
34 #ifdef CONFIG_PINCTRL_AT91
35 extern void at91_pinctrl_gpio_suspend(void);
36 extern void at91_pinctrl_gpio_resume(void);
40 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
41 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
42 const struct of_device_id *ws_ids;
43 struct at91_pm_data data;
46 static struct at91_soc_pm soc_pm = {
48 .standby_mode = AT91_PM_STANDBY,
49 .suspend_mode = AT91_PM_ULP0,
53 static const match_table_t pm_modes __initconst = {
54 { AT91_PM_STANDBY, "standby" },
55 { AT91_PM_ULP0, "ulp0" },
56 { AT91_PM_ULP1, "ulp1" },
57 { AT91_PM_BACKUP, "backup" },
61 #define at91_ramc_read(id, field) \
62 __raw_readl(soc_pm.data.ramc[id] + field)
64 #define at91_ramc_write(id, field, value) \
65 __raw_writel(value, soc_pm.data.ramc[id] + field)
67 static int at91_pm_valid_state(suspend_state_t state)
71 case PM_SUSPEND_STANDBY:
80 static int canary = 0xA5A5A5A5;
82 static struct at91_pm_bu {
84 unsigned long reserved;
89 struct wakeup_source_info {
90 unsigned int pmc_fsmr_bit;
91 unsigned int shdwc_mr_bit;
95 static const struct wakeup_source_info ws_info[] = {
96 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
97 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
98 { .pmc_fsmr_bit = AT91_PMC_USBAL },
99 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
100 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
101 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
104 static const struct of_device_id sama5d2_ws_ids[] = {
105 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
106 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
107 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
108 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
109 { .compatible = "usb-ohci", .data = &ws_info[2] },
110 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
111 { .compatible = "usb-ehci", .data = &ws_info[2] },
112 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
116 static const struct of_device_id sam9x60_ws_ids[] = {
117 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
118 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
119 { .compatible = "usb-ohci", .data = &ws_info[2] },
120 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
121 { .compatible = "usb-ehci", .data = &ws_info[2] },
122 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
123 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
127 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
129 const struct wakeup_source_info *wsi;
130 const struct of_device_id *match;
131 struct platform_device *pdev;
132 struct device_node *np;
133 unsigned int mode = 0, polarity = 0, val = 0;
135 if (pm_mode != AT91_PM_ULP1)
138 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
142 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
146 if (soc_pm.config_shdwc_ws)
147 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
150 val = readl(soc_pm.data.shdwc + 0x04);
152 /* Loop through defined wakeup sources. */
153 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
154 pdev = of_find_device_by_node(np);
158 if (device_may_wakeup(&pdev->dev)) {
161 /* Check if enabled on SHDWC. */
162 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
165 mode |= wsi->pmc_fsmr_bit;
166 if (wsi->set_polarity)
167 polarity |= wsi->pmc_fsmr_bit;
171 put_device(&pdev->dev);
175 if (soc_pm.config_pmc_ws)
176 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
178 pr_err("AT91: PM: no ULP1 wakeup sources found!");
181 return mode ? 0 : -EPERM;
184 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
190 val = readl(shdwc + 0x0c);
191 *mode |= (val & 0x3ff);
192 *polarity |= ((val >> 16) & 0x3ff);
197 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
199 writel(mode, pmc + AT91_PMC_FSMR);
200 writel(polarity, pmc + AT91_PMC_FSPR);
205 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
207 writel(mode, pmc + AT91_PMC_FSMR);
213 * Called after processes are frozen, but before we shutdown devices.
215 static int at91_pm_begin(suspend_state_t state)
219 soc_pm.data.mode = soc_pm.data.suspend_mode;
222 case PM_SUSPEND_STANDBY:
223 soc_pm.data.mode = soc_pm.data.standby_mode;
227 soc_pm.data.mode = -1;
230 return at91_pm_config_ws(soc_pm.data.mode, true);
234 * Verify that all the clocks are correct before entering
237 static int at91_pm_verify_clocks(void)
242 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
244 /* USB must not be using PLLB */
245 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
246 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
250 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
251 for (i = 0; i < 4; i++) {
254 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
256 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
257 if (css != AT91_PMC_CSS_SLOW) {
258 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
267 * Call this from platform driver suspend() to see how deeply to suspend.
268 * For example, some controllers (like OHCI) need one of the PLL clocks
269 * in order to act as a wakeup source, and those are not available when
270 * going into slow clock mode.
272 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
273 * the very same problem (but not using at91 main_clk), and it'd be better
274 * to add one generic API rather than lots of platform-specific ones.
276 int at91_suspend_entering_slow_clock(void)
278 return (soc_pm.data.mode >= AT91_PM_ULP0);
280 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
282 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
283 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
284 extern u32 at91_pm_suspend_in_sram_sz;
286 static int at91_suspend_finish(unsigned long val)
291 at91_suspend_sram_fn(&soc_pm.data);
296 static void at91_pm_suspend(suspend_state_t state)
298 if (soc_pm.data.mode == AT91_PM_BACKUP) {
299 pm_bu->suspended = 1;
301 cpu_suspend(0, at91_suspend_finish);
303 /* The SRAM is lost between suspend cycles */
304 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
305 &at91_pm_suspend_in_sram,
306 at91_pm_suspend_in_sram_sz);
308 at91_suspend_finish(0);
315 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
316 * event sources; and reduces DRAM power. But otherwise it's identical to
317 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
319 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
320 * suspend more deeply, the master clock switches to the clk32k and turns off
321 * the main oscillator
323 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
325 static int at91_pm_enter(suspend_state_t state)
327 #ifdef CONFIG_PINCTRL_AT91
328 at91_pinctrl_gpio_suspend();
333 case PM_SUSPEND_STANDBY:
335 * Ensure that clocks are in a valid state.
337 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
338 !at91_pm_verify_clocks())
341 at91_pm_suspend(state);
350 pr_debug("AT91: PM - bogus suspend state %d\n", state);
355 #ifdef CONFIG_PINCTRL_AT91
356 at91_pinctrl_gpio_resume();
362 * Called right prior to thawing processes.
364 static void at91_pm_end(void)
366 at91_pm_config_ws(soc_pm.data.mode, false);
370 static const struct platform_suspend_ops at91_pm_ops = {
371 .valid = at91_pm_valid_state,
372 .begin = at91_pm_begin,
373 .enter = at91_pm_enter,
377 static struct platform_device at91_cpuidle_device = {
378 .name = "cpuidle-at91",
382 * The AT91RM9200 goes into self-refresh mode with this command, and will
383 * terminate self-refresh automatically on the next SDRAM access.
385 * Self-refresh mode is exited as soon as a memory access is made, but we don't
386 * know for sure when that happens. However, we need to restore the low-power
387 * mode if it was enabled before going idle. Restoring low-power mode while
388 * still in self-refresh is "not recommended", but seems to work.
390 static void at91rm9200_standby(void)
395 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
396 " str %2, [%1, %3]\n\t"
397 " mcr p15, 0, %0, c7, c0, 4\n\t"
399 : "r" (0), "r" (soc_pm.data.ramc[0]),
400 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
403 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
406 static void at91_ddr_standby(void)
408 /* Those two values allow us to delay self-refresh activation
411 u32 mdr, saved_mdr0, saved_mdr1 = 0;
412 u32 saved_lpr0, saved_lpr1 = 0;
414 /* LPDDR1 --> force DDR2 mode during self-refresh */
415 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
416 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
417 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
418 mdr |= AT91_DDRSDRC_MD_DDR2;
419 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
422 if (soc_pm.data.ramc[1]) {
423 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
424 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
425 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
426 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
427 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
428 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
429 mdr |= AT91_DDRSDRC_MD_DDR2;
430 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
434 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
435 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
436 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
438 /* self-refresh mode now */
439 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
440 if (soc_pm.data.ramc[1])
441 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
445 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
446 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
447 if (soc_pm.data.ramc[1]) {
448 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
449 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
453 static void sama5d3_ddr_standby(void)
458 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
459 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
460 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
462 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
466 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
469 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
472 static void at91sam9_sdram_standby(void)
475 u32 saved_lpr0, saved_lpr1 = 0;
477 if (soc_pm.data.ramc[1]) {
478 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
479 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
480 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
483 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
484 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
485 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
487 /* self-refresh mode now */
488 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
489 if (soc_pm.data.ramc[1])
490 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
494 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
495 if (soc_pm.data.ramc[1])
496 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
501 unsigned int memctrl;
504 static const struct ramc_info ramc_infos[] __initconst = {
505 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
506 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
507 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
508 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
511 static const struct of_device_id ramc_ids[] __initconst = {
512 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
513 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
514 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
515 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
519 static __init void at91_dt_ramc(void)
521 struct device_node *np;
522 const struct of_device_id *of_id;
524 void *standby = NULL;
525 const struct ramc_info *ramc;
527 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
528 soc_pm.data.ramc[idx] = of_iomap(np, 0);
529 if (!soc_pm.data.ramc[idx])
530 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
534 standby = ramc->idle;
535 soc_pm.data.memctrl = ramc->memctrl;
541 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
544 pr_warn("ramc no standby function available\n");
548 at91_cpuidle_device.dev.platform_data = standby;
551 static void at91rm9200_idle(void)
554 * Disable the processor clock. The processor will be automatically
555 * re-enabled by an interrupt or by a reset.
557 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
560 static void at91sam9x60_idle(void)
565 static void at91sam9_idle(void)
567 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
571 static void __init at91_pm_sram_init(void)
573 struct gen_pool *sram_pool;
574 phys_addr_t sram_pbase;
575 unsigned long sram_base;
576 struct device_node *node;
577 struct platform_device *pdev = NULL;
579 for_each_compatible_node(node, NULL, "mmio-sram") {
580 pdev = of_find_device_by_node(node);
588 pr_warn("%s: failed to find sram device!\n", __func__);
592 sram_pool = gen_pool_get(&pdev->dev, NULL);
594 pr_warn("%s: sram pool unavailable!\n", __func__);
598 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
600 pr_warn("%s: unable to alloc sram!\n", __func__);
604 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
605 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
606 at91_pm_suspend_in_sram_sz, false);
607 if (!at91_suspend_sram_fn) {
608 pr_warn("SRAM: Could not map\n");
612 /* Copy the pm suspend handler to SRAM */
613 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
614 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
618 put_device(&pdev->dev);
622 static bool __init at91_is_pm_mode_active(int pm_mode)
624 return (soc_pm.data.standby_mode == pm_mode ||
625 soc_pm.data.suspend_mode == pm_mode);
628 static int __init at91_pm_backup_init(void)
630 struct gen_pool *sram_pool;
631 struct device_node *np;
632 struct platform_device *pdev = NULL;
635 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
638 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
641 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
643 pr_warn("%s: failed to find sfrbu!\n", __func__);
647 soc_pm.data.sfrbu = of_iomap(np, 0);
650 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
652 goto securam_fail_no_ref_dev;
654 pdev = of_find_device_by_node(np);
657 pr_warn("%s: failed to find securam device!\n", __func__);
658 goto securam_fail_no_ref_dev;
661 sram_pool = gen_pool_get(&pdev->dev, NULL);
663 pr_warn("%s: securam pool unavailable!\n", __func__);
667 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
669 pr_warn("%s: unable to alloc securam!\n", __func__);
674 pm_bu->suspended = 0;
675 pm_bu->canary = __pa_symbol(&canary);
676 pm_bu->resume = __pa_symbol(cpu_resume);
681 put_device(&pdev->dev);
682 securam_fail_no_ref_dev:
683 iounmap(soc_pm.data.sfrbu);
684 soc_pm.data.sfrbu = NULL;
688 static void __init at91_pm_use_default_mode(int pm_mode)
690 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
693 if (soc_pm.data.standby_mode == pm_mode)
694 soc_pm.data.standby_mode = AT91_PM_ULP0;
695 if (soc_pm.data.suspend_mode == pm_mode)
696 soc_pm.data.suspend_mode = AT91_PM_ULP0;
699 static const struct of_device_id atmel_shdwc_ids[] = {
700 { .compatible = "atmel,sama5d2-shdwc" },
701 { .compatible = "microchip,sam9x60-shdwc" },
705 static void __init at91_pm_modes_init(void)
707 struct device_node *np;
710 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
711 !at91_is_pm_mode_active(AT91_PM_ULP1))
714 np = of_find_matching_node(NULL, atmel_shdwc_ids);
716 pr_warn("%s: failed to find shdwc!\n", __func__);
720 soc_pm.data.shdwc = of_iomap(np, 0);
723 ret = at91_pm_backup_init();
725 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
734 iounmap(soc_pm.data.shdwc);
735 soc_pm.data.shdwc = NULL;
737 at91_pm_use_default_mode(AT91_PM_ULP1);
739 at91_pm_use_default_mode(AT91_PM_BACKUP);
743 unsigned long uhp_udp_mask;
746 static const struct pmc_info pmc_infos[] __initconst = {
747 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
748 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
749 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
750 { .uhp_udp_mask = 0 },
753 static const struct of_device_id atmel_pmc_ids[] __initconst = {
754 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
755 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
756 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
757 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
758 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
759 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
760 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
761 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
762 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
763 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
764 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
765 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[1] },
769 static void __init at91_pm_init(void (*pm_idle)(void))
771 struct device_node *pmc_np;
772 const struct of_device_id *of_id;
773 const struct pmc_info *pmc;
775 if (at91_cpuidle_device.dev.platform_data)
776 platform_device_register(&at91_cpuidle_device);
778 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
779 soc_pm.data.pmc = of_iomap(pmc_np, 0);
781 if (!soc_pm.data.pmc) {
782 pr_err("AT91: PM not supported, PMC not found\n");
787 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
790 arm_pm_idle = pm_idle;
794 if (at91_suspend_sram_fn) {
795 suspend_set_ops(&at91_pm_ops);
796 pr_info("AT91: PM: standby: %s, suspend: %s\n",
797 pm_modes[soc_pm.data.standby_mode].pattern,
798 pm_modes[soc_pm.data.suspend_mode].pattern);
800 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
804 void __init at91rm9200_pm_init(void)
806 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
812 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
814 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
816 at91_pm_init(at91rm9200_idle);
819 void __init sam9x60_pm_init(void)
821 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
824 at91_pm_modes_init();
826 at91_pm_init(at91sam9x60_idle);
828 soc_pm.ws_ids = sam9x60_ws_ids;
829 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
832 void __init at91sam9_pm_init(void)
834 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
838 at91_pm_init(at91sam9_idle);
841 void __init sama5_pm_init(void)
843 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
850 void __init sama5d2_pm_init(void)
852 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
855 at91_pm_modes_init();
858 soc_pm.ws_ids = sama5d2_ws_ids;
859 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
860 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
863 static int __init at91_pm_modes_select(char *str)
866 substring_t args[MAX_OPT_ARGS];
867 int standby, suspend;
872 s = strsep(&str, ",");
873 standby = match_token(s, pm_modes, args);
877 suspend = match_token(str, pm_modes, args);
881 soc_pm.data.standby_mode = standby;
882 soc_pm.data.suspend_mode = suspend;
886 early_param("atmel.pm_modes", at91_pm_modes_select);