1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/parser.h>
16 #include <linux/suspend.h>
18 #include <linux/clk.h>
19 #include <linux/clk/at91_pmc.h>
20 #include <linux/platform_data/atmel.h>
22 #include <asm/cacheflush.h>
23 #include <asm/fncpy.h>
24 #include <asm/system_misc.h>
25 #include <asm/suspend.h>
29 #include "sam_secure.h"
31 #define BACKUP_DDR_PHY_CALIBRATION (9)
34 * struct at91_pm_bu - AT91 power management backup unit data structure
35 * @suspended: true if suspended to backup mode
37 * @canary: canary data for memory checking after exit from backup mode
39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
44 unsigned long reserved;
47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
51 * struct at91_pm_sfrbu_regs - registers mapping for SFRBU
52 * @pswbu: power switch BU control registers
54 struct at91_pm_sfrbu_regs {
64 * enum at91_pm_eth_clk - Ethernet clock indexes
65 * @AT91_PM_ETH_PCLK: pclk index
66 * @AT91_PM_ETH_HCLK: hclk index
67 * @AT91_PM_ETH_MAX_CLK: max index
69 enum at91_pm_eth_clk {
76 * enum at91_pm_eth - Ethernet controller indexes
77 * @AT91_PM_G_ETH: gigabit Ethernet controller index
78 * @AT91_PM_E_ETH: megabit Ethernet controller index
79 * @AT91_PM_MAX_ETH: max index
88 * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
89 * @dev: Ethernet device
90 * @np: Ethernet device node
91 * @clks: Ethernet clocks
92 * @modes: power management mode that this quirk applies to
93 * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured
94 * as wakeup source but buggy and no other wakeup source is
97 struct at91_pm_quirk_eth {
99 struct device_node *np;
100 struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK];
106 * struct at91_pm_quirks - AT91 PM quirks
107 * @eth: Ethernet quirks
109 struct at91_pm_quirks {
110 struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH];
114 * struct at91_soc_pm - AT91 SoC power management data structure
115 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
116 * @config_pmc_ws: wakeup srouces configuration function for PMC
117 * @ws_ids: wakup sources of_device_id array
118 * @bu: backup unit mapped data (for backup mode)
120 * @data: PM data to be used on last phase of suspend
121 * @sfrbu_regs: SFRBU registers mapping
122 * @memcs: memory chip select
125 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
126 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
127 const struct of_device_id *ws_ids;
128 struct at91_pm_bu *bu;
129 struct at91_pm_quirks quirks;
130 struct at91_pm_data data;
131 struct at91_pm_sfrbu_regs sfrbu_regs;
136 * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes
137 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
138 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
139 * @AT91_PM_IOMAP_ETHC: Ethernet controller
141 enum at91_pm_iomaps {
147 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
149 static struct at91_soc_pm soc_pm = {
151 .standby_mode = AT91_PM_STANDBY,
152 .suspend_mode = AT91_PM_ULP0,
156 static const match_table_t pm_modes __initconst = {
157 { AT91_PM_STANDBY, "standby" },
158 { AT91_PM_ULP0, "ulp0" },
159 { AT91_PM_ULP0_FAST, "ulp0-fast" },
160 { AT91_PM_ULP1, "ulp1" },
161 { AT91_PM_BACKUP, "backup" },
165 #define at91_ramc_read(id, field) \
166 __raw_readl(soc_pm.data.ramc[id] + field)
168 #define at91_ramc_write(id, field, value) \
169 __raw_writel(value, soc_pm.data.ramc[id] + field)
171 static int at91_pm_valid_state(suspend_state_t state)
175 case PM_SUSPEND_STANDBY:
184 static int canary = 0xA5A5A5A5;
186 struct wakeup_source_info {
187 unsigned int pmc_fsmr_bit;
188 unsigned int shdwc_mr_bit;
192 static const struct wakeup_source_info ws_info[] = {
193 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
194 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
195 { .pmc_fsmr_bit = AT91_PMC_USBAL },
196 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
197 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
198 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
201 static const struct of_device_id sama5d2_ws_ids[] = {
202 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
203 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
204 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
205 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
206 { .compatible = "usb-ohci", .data = &ws_info[2] },
207 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
208 { .compatible = "usb-ehci", .data = &ws_info[2] },
209 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
213 static const struct of_device_id sam9x60_ws_ids[] = {
214 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
215 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
216 { .compatible = "usb-ohci", .data = &ws_info[2] },
217 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
218 { .compatible = "usb-ehci", .data = &ws_info[2] },
219 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
220 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
224 static const struct of_device_id sama7g5_ws_ids[] = {
225 { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
226 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
227 { .compatible = "usb-ohci", .data = &ws_info[2] },
228 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
229 { .compatible = "usb-ehci", .data = &ws_info[2] },
230 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
231 { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
235 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
237 const struct wakeup_source_info *wsi;
238 const struct of_device_id *match;
239 struct platform_device *pdev;
240 struct device_node *np;
241 unsigned int mode = 0, polarity = 0, val = 0;
243 if (pm_mode != AT91_PM_ULP1)
246 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
250 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
254 if (soc_pm.config_shdwc_ws)
255 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
258 val = readl(soc_pm.data.shdwc + 0x04);
260 /* Loop through defined wakeup sources. */
261 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
262 pdev = of_find_device_by_node(np);
266 if (device_may_wakeup(&pdev->dev)) {
269 /* Check if enabled on SHDWC. */
270 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
273 mode |= wsi->pmc_fsmr_bit;
274 if (wsi->set_polarity)
275 polarity |= wsi->pmc_fsmr_bit;
279 put_device(&pdev->dev);
283 if (soc_pm.config_pmc_ws)
284 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
286 pr_err("AT91: PM: no ULP1 wakeup sources found!");
289 return mode ? 0 : -EPERM;
292 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
298 val = readl(shdwc + 0x0c);
299 *mode |= (val & 0x3ff);
300 *polarity |= ((val >> 16) & 0x3ff);
305 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
307 writel(mode, pmc + AT91_PMC_FSMR);
308 writel(polarity, pmc + AT91_PMC_FSPR);
313 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
315 writel(mode, pmc + AT91_PMC_FSMR);
320 static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
322 struct platform_device *pdev;
324 /* Interface NA in DT. */
328 /* No quirks for this interface and current suspend mode. */
329 if (!(eth->modes & BIT(soc_pm.data.mode)))
333 /* Driver not probed. */
334 pdev = of_find_device_by_node(eth->np);
337 /* put_device(eth->dev) is called at the end of suspend. */
338 eth->dev = &pdev->dev;
341 /* No quirks if device isn't a wakeup source. */
342 if (!device_may_wakeup(eth->dev))
348 static int at91_pm_config_quirks(bool suspend)
350 struct at91_pm_quirk_eth *eth;
354 * Ethernet IPs who's device_node pointers are stored into
355 * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
356 * or both due to a hardware bug. If they receive WoL packets while in
357 * ULP0 or ULP1 IPs could stop working or the whole system could stop
358 * working. We cannot handle this scenario in the ethernet driver itself
359 * as the driver is common to multiple vendors and also we only know
360 * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle
361 * these scenarios here, as quirks.
363 for (i = 0; i < AT91_PM_MAX_ETH; i++) {
364 eth = &soc_pm.quirks.eth[i];
366 if (!at91_pm_eth_quirk_is_valid(eth))
370 * For modes in dns_modes mask the system blocks if quirk is not
371 * applied but if applied the interface doesn't act at WoL
372 * events. Thus take care to avoid suspending if this interface
373 * is the only configured wakeup source.
375 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
377 #ifdef CONFIG_PM_SLEEP
378 struct wakeup_source *ws;
380 for_each_wakeup_source(ws) {
381 if (ws->dev == eth->dev)
390 * Checking !ws is good for all platforms with issues
391 * even when both G_ETH and E_ETH are available as dns_modes
392 * is populated only on G_ETH interface.
395 pr_err("AT91: PM: Ethernet cannot resume from WoL!");
397 put_device(eth->dev);
399 /* No need to revert clock settings for this eth. */
401 goto clk_unconfigure;
406 clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks);
408 ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK,
411 goto clk_unconfigure;
413 * Release the reference to eth->dev taken in
414 * at91_pm_eth_quirk_is_valid().
416 put_device(eth->dev);
425 * In case of resume we reach this point if clk_prepare_enable() failed.
426 * we don't want to revert the previous clk_prepare_enable() for the
429 for (j = i; j >= 0; j--) {
430 eth = &soc_pm.quirks.eth[j];
432 if (!at91_pm_eth_quirk_is_valid(eth))
435 tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks);
437 pr_err("AT91: PM: failed to enable %s clocks\n",
438 j == AT91_PM_G_ETH ? "geth" : "eth");
443 * Release the reference to eth->dev taken in
444 * at91_pm_eth_quirk_is_valid().
446 put_device(eth->dev);
454 * Called after processes are frozen, but before we shutdown devices.
456 static int at91_pm_begin(suspend_state_t state)
462 soc_pm.data.mode = soc_pm.data.suspend_mode;
465 case PM_SUSPEND_STANDBY:
466 soc_pm.data.mode = soc_pm.data.standby_mode;
470 soc_pm.data.mode = -1;
473 ret = at91_pm_config_ws(soc_pm.data.mode, true);
477 if (soc_pm.data.mode == AT91_PM_BACKUP)
478 soc_pm.bu->suspended = 1;
480 soc_pm.bu->suspended = 0;
486 * Verify that all the clocks are correct before entering
489 static int at91_pm_verify_clocks(void)
494 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
496 /* USB must not be using PLLB */
497 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
498 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
502 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
503 for (i = 0; i < 4; i++) {
506 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
508 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
509 if (css != AT91_PMC_CSS_SLOW) {
510 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
519 * Call this from platform driver suspend() to see how deeply to suspend.
520 * For example, some controllers (like OHCI) need one of the PLL clocks
521 * in order to act as a wakeup source, and those are not available when
522 * going into slow clock mode.
524 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
525 * the very same problem (but not using at91 main_clk), and it'd be better
526 * to add one generic API rather than lots of platform-specific ones.
528 int at91_suspend_entering_slow_clock(void)
530 return (soc_pm.data.mode >= AT91_PM_ULP0);
532 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
534 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
535 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
536 extern u32 at91_pm_suspend_in_sram_sz;
538 static int at91_suspend_finish(unsigned long val)
540 unsigned char modified_gray_code[] = {
541 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
542 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
543 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
546 unsigned int tmp, index;
549 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
551 * Bootloader will perform DDR recalibration and will try to
552 * restore the ZQ0SR0 with the value saved here. But the
553 * calibration is buggy and restoring some values from ZQ0SR0
554 * is forbidden and risky thus we need to provide processed
555 * values for these (modified gray code values).
557 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
559 /* Store pull-down output impedance select. */
560 index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
561 soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
563 /* Store pull-up output impedance select. */
564 index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
565 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
567 /* Store pull-down on-die termination impedance select. */
568 index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
569 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
571 /* Store pull-up on-die termination impedance select. */
572 index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
573 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
576 * The 1st 8 words of memory might get corrupted in the process
577 * of DDR PHY recalibration; it is saved here in securam and it
578 * will be restored later, after recalibration, by bootloader
580 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
581 soc_pm.bu->ddr_phy_calibration[i] =
582 *((unsigned int *)soc_pm.memcs + (i - 1));
588 at91_suspend_sram_fn(&soc_pm.data);
593 static void at91_pm_switch_ba_to_vbat(void)
595 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
598 /* Just for safety. */
599 if (!soc_pm.data.sfrbu)
602 val = readl(soc_pm.data.sfrbu + offset);
604 /* Already on VBAT. */
605 if (!(val & soc_pm.sfrbu_regs.pswbu.state))
608 val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
609 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
610 writel(val, soc_pm.data.sfrbu + offset);
612 /* Wait for update. */
613 val = readl(soc_pm.data.sfrbu + offset);
614 while (val & soc_pm.sfrbu_regs.pswbu.state)
615 val = readl(soc_pm.data.sfrbu + offset);
618 static void at91_pm_suspend(suspend_state_t state)
620 if (soc_pm.data.mode == AT91_PM_BACKUP) {
621 at91_pm_switch_ba_to_vbat();
623 cpu_suspend(0, at91_suspend_finish);
625 /* The SRAM is lost between suspend cycles */
626 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
627 &at91_pm_suspend_in_sram,
628 at91_pm_suspend_in_sram_sz);
630 at91_suspend_finish(0);
637 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
638 * event sources; and reduces DRAM power. But otherwise it's identical to
639 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
641 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
642 * suspend more deeply, the master clock switches to the clk32k and turns off
643 * the main oscillator
645 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
647 static int at91_pm_enter(suspend_state_t state)
651 ret = at91_pm_config_quirks(true);
657 case PM_SUSPEND_STANDBY:
659 * Ensure that clocks are in a valid state.
661 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
662 !at91_pm_verify_clocks())
665 at91_pm_suspend(state);
674 pr_debug("AT91: PM - bogus suspend state %d\n", state);
679 at91_pm_config_quirks(false);
684 * Called right prior to thawing processes.
686 static void at91_pm_end(void)
688 at91_pm_config_ws(soc_pm.data.mode, false);
692 static const struct platform_suspend_ops at91_pm_ops = {
693 .valid = at91_pm_valid_state,
694 .begin = at91_pm_begin,
695 .enter = at91_pm_enter,
699 static struct platform_device at91_cpuidle_device = {
700 .name = "cpuidle-at91",
704 * The AT91RM9200 goes into self-refresh mode with this command, and will
705 * terminate self-refresh automatically on the next SDRAM access.
707 * Self-refresh mode is exited as soon as a memory access is made, but we don't
708 * know for sure when that happens. However, we need to restore the low-power
709 * mode if it was enabled before going idle. Restoring low-power mode while
710 * still in self-refresh is "not recommended", but seems to work.
712 static void at91rm9200_standby(void)
717 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
718 " str %2, [%1, %3]\n\t"
719 " mcr p15, 0, %0, c7, c0, 4\n\t"
721 : "r" (0), "r" (soc_pm.data.ramc[0]),
722 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
725 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
728 static void at91_ddr_standby(void)
730 /* Those two values allow us to delay self-refresh activation
733 u32 mdr, saved_mdr0, saved_mdr1 = 0;
734 u32 saved_lpr0, saved_lpr1 = 0;
736 /* LPDDR1 --> force DDR2 mode during self-refresh */
737 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
738 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
739 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
740 mdr |= AT91_DDRSDRC_MD_DDR2;
741 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
744 if (soc_pm.data.ramc[1]) {
745 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
746 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
747 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
748 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
749 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
750 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
751 mdr |= AT91_DDRSDRC_MD_DDR2;
752 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
756 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
757 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
758 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
760 /* self-refresh mode now */
761 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
762 if (soc_pm.data.ramc[1])
763 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
767 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
768 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
769 if (soc_pm.data.ramc[1]) {
770 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
771 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
775 static void sama5d3_ddr_standby(void)
780 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
781 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
782 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
784 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
788 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
791 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
794 static void at91sam9_sdram_standby(void)
797 u32 saved_lpr0, saved_lpr1 = 0;
799 if (soc_pm.data.ramc[1]) {
800 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
801 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
802 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
805 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
806 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
807 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
809 /* self-refresh mode now */
810 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
811 if (soc_pm.data.ramc[1])
812 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
816 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
817 if (soc_pm.data.ramc[1])
818 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
821 static void sama7g5_standby(void)
825 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
826 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
829 * Place RAM into self-refresh after a maximum idle clocks. The maximum
830 * idle clocks is configured by bootloader in
831 * UDDRC_PWRMGT.SELFREF_TO_X32.
833 writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
834 soc_pm.data.ramc[0] + UDDRC_PWRCTL);
835 /* Divide CPU clock by 16. */
836 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
840 /* Restore previous configuration. */
841 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
842 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
847 unsigned int memctrl;
850 static const struct ramc_info ramc_infos[] __initconst = {
851 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
852 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
853 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
854 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
855 { .idle = sama7g5_standby, },
858 static const struct of_device_id ramc_ids[] __initconst = {
859 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
860 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
861 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
862 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
863 { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
867 static const struct of_device_id ramc_phy_ids[] __initconst = {
868 { .compatible = "microchip,sama7g5-ddr3phy", },
872 static __init int at91_dt_ramc(bool phy_mandatory)
874 struct device_node *np;
875 const struct of_device_id *of_id;
877 void *standby = NULL;
878 const struct ramc_info *ramc;
881 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
882 soc_pm.data.ramc[idx] = of_iomap(np, 0);
883 if (!soc_pm.data.ramc[idx]) {
884 pr_err("unable to map ramc[%d] cpu registers\n", idx);
893 standby = ramc->idle;
894 soc_pm.data.memctrl = ramc->memctrl;
901 pr_err("unable to find compatible ram controller node in dtb\n");
906 /* Lookup for DDR PHY node, if any. */
907 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
908 soc_pm.data.ramc_phy = of_iomap(np, 0);
909 if (!soc_pm.data.ramc_phy) {
910 pr_err("unable to map ramc phy cpu registers\n");
917 if (phy_mandatory && !soc_pm.data.ramc_phy) {
918 pr_err("DDR PHY is mandatory!\n");
924 pr_warn("ramc no standby function available\n");
928 at91_cpuidle_device.dev.platform_data = standby;
934 iounmap(soc_pm.data.ramc[--idx]);
939 static void at91rm9200_idle(void)
942 * Disable the processor clock. The processor will be automatically
943 * re-enabled by an interrupt or by a reset.
945 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
948 static void at91sam9_idle(void)
950 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
954 static void __init at91_pm_sram_init(void)
956 struct gen_pool *sram_pool;
957 phys_addr_t sram_pbase;
958 unsigned long sram_base;
959 struct device_node *node;
960 struct platform_device *pdev = NULL;
962 for_each_compatible_node(node, NULL, "mmio-sram") {
963 pdev = of_find_device_by_node(node);
971 pr_warn("%s: failed to find sram device!\n", __func__);
975 sram_pool = gen_pool_get(&pdev->dev, NULL);
977 pr_warn("%s: sram pool unavailable!\n", __func__);
981 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
983 pr_warn("%s: unable to alloc sram!\n", __func__);
987 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
988 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
989 at91_pm_suspend_in_sram_sz, false);
990 if (!at91_suspend_sram_fn) {
991 pr_warn("SRAM: Could not map\n");
995 /* Copy the pm suspend handler to SRAM */
996 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
997 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
1001 put_device(&pdev->dev);
1005 static bool __init at91_is_pm_mode_active(int pm_mode)
1007 return (soc_pm.data.standby_mode == pm_mode ||
1008 soc_pm.data.suspend_mode == pm_mode);
1011 static int __init at91_pm_backup_scan_memcs(unsigned long node,
1012 const char *uname, int depth,
1017 int *located = data;
1020 /* Memory node already located. */
1024 type = of_get_flat_dt_prop(node, "device_type", NULL);
1026 /* We are scanning "memory" nodes only. */
1027 if (!type || strcmp(type, "memory"))
1030 reg = of_get_flat_dt_prop(node, "reg", &size);
1032 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
1039 static int __init at91_pm_backup_init(void)
1041 struct gen_pool *sram_pool;
1042 struct device_node *np;
1043 struct platform_device *pdev;
1044 int ret = -ENODEV, located = 0;
1046 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
1047 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
1050 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
1053 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
1057 pdev = of_find_device_by_node(np);
1060 pr_warn("%s: failed to find securam device!\n", __func__);
1064 sram_pool = gen_pool_get(&pdev->dev, NULL);
1066 pr_warn("%s: securam pool unavailable!\n", __func__);
1070 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
1072 pr_warn("%s: unable to alloc securam!\n", __func__);
1077 soc_pm.bu->suspended = 0;
1078 soc_pm.bu->canary = __pa_symbol(&canary);
1079 soc_pm.bu->resume = __pa_symbol(cpu_resume);
1080 if (soc_pm.data.ramc_phy) {
1081 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
1089 put_device(&pdev->dev);
1093 static void __init at91_pm_secure_init(void)
1096 struct arm_smccc_res res;
1098 suspend_mode = soc_pm.data.suspend_mode;
1100 res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE,
1103 pr_info("AT91: Secure PM: suspend mode set to %s\n",
1104 pm_modes[suspend_mode].pattern);
1108 pr_warn("AT91: Secure PM: %s mode not supported !\n",
1109 pm_modes[suspend_mode].pattern);
1111 res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
1113 pr_warn("AT91: Secure PM: failed to get default mode\n");
1117 pr_info("AT91: Secure PM: using default suspend mode %s\n",
1118 pm_modes[suspend_mode].pattern);
1120 soc_pm.data.suspend_mode = res.a1;
1122 static const struct of_device_id atmel_shdwc_ids[] = {
1123 { .compatible = "atmel,sama5d2-shdwc" },
1124 { .compatible = "microchip,sam9x60-shdwc" },
1125 { .compatible = "microchip,sama7g5-shdwc" },
1129 static const struct of_device_id gmac_ids[] __initconst = {
1130 { .compatible = "atmel,sama5d3-gem" },
1131 { .compatible = "atmel,sama5d2-gem" },
1132 { .compatible = "atmel,sama5d29-gem" },
1133 { .compatible = "microchip,sama7g5-gem" },
1137 static const struct of_device_id emac_ids[] __initconst = {
1138 { .compatible = "atmel,sama5d3-macb" },
1139 { .compatible = "microchip,sama7g5-emac" },
1144 * Replaces _mode_to_replace with a supported mode that doesn't depend
1145 * on controller pointed by _map_bitmask
1146 * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91
1148 * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on
1149 * controller represented by _map_bitmask, _mode_to_replace needs to be
1151 * @_mode_to_replace: standby_mode or suspend_mode that need to be
1153 * @_mode_to_check: standby_mode or suspend_mode; this is needed here
1154 * to avoid having standby_mode and suspend_mode set with the same AT91
1157 #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \
1160 if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \
1161 int _mode_to_use, _mode_complementary; \
1162 /* Use ULP0 if it doesn't need _map_bitmask. */ \
1163 if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\
1164 _mode_to_use = AT91_PM_ULP0; \
1165 _mode_complementary = AT91_PM_STANDBY; \
1167 _mode_to_use = AT91_PM_STANDBY; \
1168 _mode_complementary = AT91_PM_STANDBY; \
1171 if ((_mode_to_check) != _mode_to_use) \
1172 (_mode_to_replace) = _mode_to_use; \
1174 (_mode_to_replace) = _mode_complementary;\
1179 * Replaces standby and suspend modes with default supported modes:
1181 * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP()
1183 * @_map: controller specific name; standby and suspend mode need to be
1184 * replaced in order to not depend on this controller
1186 #define AT91_PM_REPLACE_MODES(_maps, _map) \
1188 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
1189 (soc_pm.data.standby_mode), \
1190 (soc_pm.data.suspend_mode)); \
1191 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
1192 (soc_pm.data.suspend_mode), \
1193 (soc_pm.data.standby_mode)); \
1196 static int __init at91_pm_get_eth_clks(struct device_node *np,
1197 struct clk_bulk_data *clks)
1199 clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk");
1200 if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk))
1201 return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk);
1203 clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk");
1204 if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk))
1205 return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk);
1210 static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks)
1212 return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) ||
1213 IS_ERR(clks[AT91_PM_ETH_HCLK].clk);
1216 static void __init at91_pm_modes_init(const u32 *maps, int len)
1218 struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
1219 struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
1220 struct device_node *np;
1223 ret = at91_pm_backup_init();
1225 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
1226 soc_pm.data.standby_mode = AT91_PM_ULP0;
1227 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
1228 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1231 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1232 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
1233 np = of_find_matching_node(NULL, atmel_shdwc_ids);
1235 pr_warn("%s: failed to find shdwc!\n", __func__);
1236 AT91_PM_REPLACE_MODES(maps, SHDWC);
1238 soc_pm.data.shdwc = of_iomap(np, 0);
1243 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1244 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
1245 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
1247 pr_warn("%s: failed to find sfrbu!\n", __func__);
1248 AT91_PM_REPLACE_MODES(maps, SFRBU);
1250 soc_pm.data.sfrbu = of_iomap(np, 0);
1255 if ((at91_is_pm_mode_active(AT91_PM_ULP1) ||
1256 at91_is_pm_mode_active(AT91_PM_ULP0) ||
1257 at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) &&
1258 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
1259 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
1260 np = of_find_matching_node(NULL, gmac_ids);
1262 np = of_find_matching_node(NULL, emac_ids);
1265 AT91_PM_REPLACE_MODES(maps, ETHC);
1266 goto unmap_unused_nodes;
1269 at91_pm_get_eth_clks(np, gmac->clks);
1272 np = of_find_matching_node(NULL, emac_ids);
1274 if (at91_pm_eth_clks_empty(gmac->clks))
1275 AT91_PM_REPLACE_MODES(maps, ETHC);
1279 ret = at91_pm_get_eth_clks(np, emac->clks);
1280 if (ret && at91_pm_eth_clks_empty(gmac->clks)) {
1281 of_node_put(gmac->np);
1282 of_node_put(emac->np);
1290 /* Unmap all unnecessary. */
1291 if (soc_pm.data.shdwc &&
1292 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1293 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
1294 iounmap(soc_pm.data.shdwc);
1295 soc_pm.data.shdwc = NULL;
1298 if (soc_pm.data.sfrbu &&
1299 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1300 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
1301 iounmap(soc_pm.data.sfrbu);
1302 soc_pm.data.sfrbu = NULL;
1309 unsigned long uhp_udp_mask;
1311 unsigned long version;
1314 static const struct pmc_info pmc_infos[] __initconst = {
1316 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
1318 .version = AT91_PMC_V1,
1322 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1324 .version = AT91_PMC_V1,
1327 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
1329 .version = AT91_PMC_V1,
1331 { .uhp_udp_mask = 0,
1333 .version = AT91_PMC_V1,
1336 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1338 .version = AT91_PMC_V2,
1342 .version = AT91_PMC_V2,
1347 static const struct of_device_id atmel_pmc_ids[] __initconst = {
1348 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
1349 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
1350 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
1351 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
1352 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
1353 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
1354 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
1355 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
1356 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
1357 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
1358 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
1359 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
1360 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
1364 static void __init at91_pm_modes_validate(const int *modes, int len)
1366 u8 i, standby = 0, suspend = 0;
1369 for (i = 0; i < len; i++) {
1370 if (standby && suspend)
1373 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1378 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1385 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1386 mode = AT91_PM_ULP0;
1388 mode = AT91_PM_STANDBY;
1390 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1391 pm_modes[soc_pm.data.standby_mode].pattern,
1392 pm_modes[mode].pattern);
1393 soc_pm.data.standby_mode = mode;
1397 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1398 mode = AT91_PM_STANDBY;
1400 mode = AT91_PM_ULP0;
1402 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1403 pm_modes[soc_pm.data.suspend_mode].pattern,
1404 pm_modes[mode].pattern);
1405 soc_pm.data.suspend_mode = mode;
1409 static void __init at91_pm_init(void (*pm_idle)(void))
1411 struct device_node *pmc_np;
1412 const struct of_device_id *of_id;
1413 const struct pmc_info *pmc;
1415 if (at91_cpuidle_device.dev.platform_data)
1416 platform_device_register(&at91_cpuidle_device);
1418 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
1419 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1420 of_node_put(pmc_np);
1421 if (!soc_pm.data.pmc) {
1422 pr_err("AT91: PM not supported, PMC not found\n");
1427 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1428 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1429 soc_pm.data.pmc_version = pmc->version;
1432 arm_pm_idle = pm_idle;
1434 at91_pm_sram_init();
1436 if (at91_suspend_sram_fn) {
1437 suspend_set_ops(&at91_pm_ops);
1438 pr_info("AT91: PM: standby: %s, suspend: %s\n",
1439 pm_modes[soc_pm.data.standby_mode].pattern,
1440 pm_modes[soc_pm.data.suspend_mode].pattern);
1442 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1446 void __init at91rm9200_pm_init(void)
1450 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1454 * Force STANDBY and ULP0 mode to avoid calling
1455 * at91_pm_modes_validate() which may increase booting time.
1456 * Platform supports anyway only STANDBY and ULP0 modes.
1458 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1459 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1461 ret = at91_dt_ramc(false);
1466 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1468 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1470 at91_pm_init(at91rm9200_idle);
1473 void __init sam9x60_pm_init(void)
1475 static const int modes[] __initconst = {
1476 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1478 static const int iomaps[] __initconst = {
1479 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1483 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1486 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1487 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1488 ret = at91_dt_ramc(false);
1494 soc_pm.ws_ids = sam9x60_ws_ids;
1495 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1498 void __init at91sam9_pm_init(void)
1502 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1506 * Force STANDBY and ULP0 mode to avoid calling
1507 * at91_pm_modes_validate() which may increase booting time.
1508 * Platform supports anyway only STANDBY and ULP0 modes.
1510 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1511 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1513 ret = at91_dt_ramc(false);
1517 at91_pm_init(at91sam9_idle);
1520 void __init sama5_pm_init(void)
1522 static const int modes[] __initconst = {
1523 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1525 static const u32 iomaps[] __initconst = {
1526 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
1527 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
1531 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1534 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1535 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1536 ret = at91_dt_ramc(false);
1542 /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */
1543 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1544 BIT(AT91_PM_ULP0_FAST) |
1546 /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */
1547 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1548 BIT(AT91_PM_ULP0_FAST);
1551 void __init sama5d2_pm_init(void)
1553 static const int modes[] __initconst = {
1554 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1557 static const u32 iomaps[] __initconst = {
1558 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
1559 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
1560 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) |
1561 AT91_PM_IOMAP(ETHC),
1562 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1563 AT91_PM_IOMAP(SFRBU),
1567 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1570 if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) {
1571 pr_warn("AT91: Secure PM: ignoring standby mode\n");
1572 at91_pm_secure_init();
1576 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1577 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1578 ret = at91_dt_ramc(false);
1584 soc_pm.ws_ids = sama5d2_ws_ids;
1585 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1586 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1588 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1589 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1590 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1591 soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1593 /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */
1594 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1595 BIT(AT91_PM_ULP0_FAST) |
1598 * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup
1601 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1602 BIT(AT91_PM_ULP0_FAST);
1605 void __init sama7_pm_init(void)
1607 static const int modes[] __initconst = {
1608 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1610 static const u32 iomaps[] __initconst = {
1611 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
1612 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
1613 AT91_PM_IOMAP(SHDWC) |
1614 AT91_PM_IOMAP(ETHC),
1615 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
1616 AT91_PM_IOMAP(SHDWC),
1620 if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1623 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1625 ret = at91_dt_ramc(true);
1629 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1632 soc_pm.ws_ids = sama7g5_ws_ids;
1633 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1635 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1636 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1637 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1638 soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1640 /* Quirks applies to ULP1 for both Ethernet interfaces. */
1641 soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
1642 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
1645 static int __init at91_pm_modes_select(char *str)
1648 substring_t args[MAX_OPT_ARGS];
1649 int standby, suspend;
1654 s = strsep(&str, ",");
1655 standby = match_token(s, pm_modes, args);
1659 suspend = match_token(str, pm_modes, args);
1663 soc_pm.data.standby_mode = standby;
1664 soc_pm.data.suspend_mode = suspend;
1668 early_param("atmel.pm_modes", at91_pm_modes_select);