1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/parser.h>
17 #include <linux/suspend.h>
19 #include <linux/clk.h>
20 #include <linux/clk/at91_pmc.h>
21 #include <linux/platform_data/atmel.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
30 #include "sam_secure.h"
32 #define BACKUP_DDR_PHY_CALIBRATION (9)
35 * struct at91_pm_bu - AT91 power management backup unit data structure
36 * @suspended: true if suspended to backup mode
38 * @canary: canary data for memory checking after exit from backup mode
40 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
45 unsigned long reserved;
48 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
52 * struct at91_pm_sfrbu_regs - registers mapping for SFRBU
53 * @pswbu: power switch BU control registers
55 struct at91_pm_sfrbu_regs {
65 * enum at91_pm_eth_clk - Ethernet clock indexes
66 * @AT91_PM_ETH_PCLK: pclk index
67 * @AT91_PM_ETH_HCLK: hclk index
68 * @AT91_PM_ETH_MAX_CLK: max index
70 enum at91_pm_eth_clk {
77 * enum at91_pm_eth - Ethernet controller indexes
78 * @AT91_PM_G_ETH: gigabit Ethernet controller index
79 * @AT91_PM_E_ETH: megabit Ethernet controller index
80 * @AT91_PM_MAX_ETH: max index
89 * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
90 * @dev: Ethernet device
91 * @np: Ethernet device node
92 * @clks: Ethernet clocks
93 * @modes: power management mode that this quirk applies to
94 * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured
95 * as wakeup source but buggy and no other wakeup source is
98 struct at91_pm_quirk_eth {
100 struct device_node *np;
101 struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK];
107 * struct at91_pm_quirks - AT91 PM quirks
108 * @eth: Ethernet quirks
110 struct at91_pm_quirks {
111 struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH];
115 * struct at91_soc_pm - AT91 SoC power management data structure
116 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
117 * @config_pmc_ws: wakeup srouces configuration function for PMC
118 * @ws_ids: wakup sources of_device_id array
119 * @bu: backup unit mapped data (for backup mode)
121 * @data: PM data to be used on last phase of suspend
122 * @sfrbu_regs: SFRBU registers mapping
123 * @memcs: memory chip select
126 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
127 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
128 const struct of_device_id *ws_ids;
129 struct at91_pm_bu *bu;
130 struct at91_pm_quirks quirks;
131 struct at91_pm_data data;
132 struct at91_pm_sfrbu_regs sfrbu_regs;
137 * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes
138 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
139 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
140 * @AT91_PM_IOMAP_ETHC: Ethernet controller
142 enum at91_pm_iomaps {
148 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
150 static struct at91_soc_pm soc_pm = {
152 .standby_mode = AT91_PM_STANDBY,
153 .suspend_mode = AT91_PM_ULP0,
157 static const match_table_t pm_modes __initconst = {
158 { AT91_PM_STANDBY, "standby" },
159 { AT91_PM_ULP0, "ulp0" },
160 { AT91_PM_ULP0_FAST, "ulp0-fast" },
161 { AT91_PM_ULP1, "ulp1" },
162 { AT91_PM_BACKUP, "backup" },
166 #define at91_ramc_read(id, field) \
167 __raw_readl(soc_pm.data.ramc[id] + field)
169 #define at91_ramc_write(id, field, value) \
170 __raw_writel(value, soc_pm.data.ramc[id] + field)
172 static int at91_pm_valid_state(suspend_state_t state)
176 case PM_SUSPEND_STANDBY:
185 static int canary = 0xA5A5A5A5;
187 struct wakeup_source_info {
188 unsigned int pmc_fsmr_bit;
189 unsigned int shdwc_mr_bit;
193 static const struct wakeup_source_info ws_info[] = {
194 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
195 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
196 { .pmc_fsmr_bit = AT91_PMC_USBAL },
197 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
198 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
199 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
202 static const struct of_device_id sama5d2_ws_ids[] = {
203 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
204 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
205 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
206 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
207 { .compatible = "usb-ohci", .data = &ws_info[2] },
208 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
209 { .compatible = "usb-ehci", .data = &ws_info[2] },
210 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
214 static const struct of_device_id sam9x60_ws_ids[] = {
215 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
216 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
217 { .compatible = "usb-ohci", .data = &ws_info[2] },
218 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
219 { .compatible = "usb-ehci", .data = &ws_info[2] },
220 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
221 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
225 static const struct of_device_id sama7g5_ws_ids[] = {
226 { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
227 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
228 { .compatible = "usb-ohci", .data = &ws_info[2] },
229 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
230 { .compatible = "usb-ehci", .data = &ws_info[2] },
231 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
232 { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
236 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
238 const struct wakeup_source_info *wsi;
239 const struct of_device_id *match;
240 struct platform_device *pdev;
241 struct device_node *np;
242 unsigned int mode = 0, polarity = 0, val = 0;
244 if (pm_mode != AT91_PM_ULP1)
247 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
251 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
255 if (soc_pm.config_shdwc_ws)
256 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
259 val = readl(soc_pm.data.shdwc + 0x04);
261 /* Loop through defined wakeup sources. */
262 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
263 pdev = of_find_device_by_node(np);
267 if (device_may_wakeup(&pdev->dev)) {
270 /* Check if enabled on SHDWC. */
271 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
274 mode |= wsi->pmc_fsmr_bit;
275 if (wsi->set_polarity)
276 polarity |= wsi->pmc_fsmr_bit;
280 put_device(&pdev->dev);
284 if (soc_pm.config_pmc_ws)
285 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
287 pr_err("AT91: PM: no ULP1 wakeup sources found!");
290 return mode ? 0 : -EPERM;
293 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
299 val = readl(shdwc + 0x0c);
300 *mode |= (val & 0x3ff);
301 *polarity |= ((val >> 16) & 0x3ff);
306 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
308 writel(mode, pmc + AT91_PMC_FSMR);
309 writel(polarity, pmc + AT91_PMC_FSPR);
314 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
316 writel(mode, pmc + AT91_PMC_FSMR);
321 static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
323 struct platform_device *pdev;
325 /* Interface NA in DT. */
329 /* No quirks for this interface and current suspend mode. */
330 if (!(eth->modes & BIT(soc_pm.data.mode)))
334 /* Driver not probed. */
335 pdev = of_find_device_by_node(eth->np);
338 /* put_device(eth->dev) is called at the end of suspend. */
339 eth->dev = &pdev->dev;
342 /* No quirks if device isn't a wakeup source. */
343 if (!device_may_wakeup(eth->dev))
349 static int at91_pm_config_quirks(bool suspend)
351 struct at91_pm_quirk_eth *eth;
355 * Ethernet IPs who's device_node pointers are stored into
356 * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
357 * or both due to a hardware bug. If they receive WoL packets while in
358 * ULP0 or ULP1 IPs could stop working or the whole system could stop
359 * working. We cannot handle this scenario in the ethernet driver itself
360 * as the driver is common to multiple vendors and also we only know
361 * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle
362 * these scenarios here, as quirks.
364 for (i = 0; i < AT91_PM_MAX_ETH; i++) {
365 eth = &soc_pm.quirks.eth[i];
367 if (!at91_pm_eth_quirk_is_valid(eth))
371 * For modes in dns_modes mask the system blocks if quirk is not
372 * applied but if applied the interface doesn't act at WoL
373 * events. Thus take care to avoid suspending if this interface
374 * is the only configured wakeup source.
376 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
378 #ifdef CONFIG_PM_SLEEP
379 struct wakeup_source *ws;
381 for_each_wakeup_source(ws) {
382 if (ws->dev == eth->dev)
391 * Checking !ws is good for all platforms with issues
392 * even when both G_ETH and E_ETH are available as dns_modes
393 * is populated only on G_ETH interface.
396 pr_err("AT91: PM: Ethernet cannot resume from WoL!");
398 put_device(eth->dev);
400 /* No need to revert clock settings for this eth. */
402 goto clk_unconfigure;
407 clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks);
409 ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK,
412 goto clk_unconfigure;
414 * Release the reference to eth->dev taken in
415 * at91_pm_eth_quirk_is_valid().
417 put_device(eth->dev);
426 * In case of resume we reach this point if clk_prepare_enable() failed.
427 * we don't want to revert the previous clk_prepare_enable() for the
430 for (j = i; j >= 0; j--) {
431 eth = &soc_pm.quirks.eth[j];
433 if (!at91_pm_eth_quirk_is_valid(eth))
436 tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks);
438 pr_err("AT91: PM: failed to enable %s clocks\n",
439 j == AT91_PM_G_ETH ? "geth" : "eth");
444 * Release the reference to eth->dev taken in
445 * at91_pm_eth_quirk_is_valid().
447 put_device(eth->dev);
455 * Called after processes are frozen, but before we shutdown devices.
457 static int at91_pm_begin(suspend_state_t state)
463 soc_pm.data.mode = soc_pm.data.suspend_mode;
466 case PM_SUSPEND_STANDBY:
467 soc_pm.data.mode = soc_pm.data.standby_mode;
471 soc_pm.data.mode = -1;
474 ret = at91_pm_config_ws(soc_pm.data.mode, true);
478 if (soc_pm.data.mode == AT91_PM_BACKUP)
479 soc_pm.bu->suspended = 1;
481 soc_pm.bu->suspended = 0;
487 * Verify that all the clocks are correct before entering
490 static int at91_pm_verify_clocks(void)
495 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
497 /* USB must not be using PLLB */
498 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
499 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
503 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
504 for (i = 0; i < 4; i++) {
507 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
509 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
510 if (css != AT91_PMC_CSS_SLOW) {
511 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
520 * Call this from platform driver suspend() to see how deeply to suspend.
521 * For example, some controllers (like OHCI) need one of the PLL clocks
522 * in order to act as a wakeup source, and those are not available when
523 * going into slow clock mode.
525 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
526 * the very same problem (but not using at91 main_clk), and it'd be better
527 * to add one generic API rather than lots of platform-specific ones.
529 int at91_suspend_entering_slow_clock(void)
531 return (soc_pm.data.mode >= AT91_PM_ULP0);
533 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
535 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
536 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
537 extern u32 at91_pm_suspend_in_sram_sz;
539 static int at91_suspend_finish(unsigned long val)
541 unsigned char modified_gray_code[] = {
542 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
543 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
544 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
547 unsigned int tmp, index;
550 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
552 * Bootloader will perform DDR recalibration and will try to
553 * restore the ZQ0SR0 with the value saved here. But the
554 * calibration is buggy and restoring some values from ZQ0SR0
555 * is forbidden and risky thus we need to provide processed
556 * values for these (modified gray code values).
558 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
560 /* Store pull-down output impedance select. */
561 index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
562 soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
564 /* Store pull-up output impedance select. */
565 index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
566 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
568 /* Store pull-down on-die termination impedance select. */
569 index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
570 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
572 /* Store pull-up on-die termination impedance select. */
573 index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
574 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
577 * The 1st 8 words of memory might get corrupted in the process
578 * of DDR PHY recalibration; it is saved here in securam and it
579 * will be restored later, after recalibration, by bootloader
581 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
582 soc_pm.bu->ddr_phy_calibration[i] =
583 *((unsigned int *)soc_pm.memcs + (i - 1));
589 at91_suspend_sram_fn(&soc_pm.data);
594 static void at91_pm_switch_ba_to_vbat(void)
596 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
599 /* Just for safety. */
600 if (!soc_pm.data.sfrbu)
603 val = readl(soc_pm.data.sfrbu + offset);
605 /* Already on VBAT. */
606 if (!(val & soc_pm.sfrbu_regs.pswbu.state))
609 val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
610 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
611 writel(val, soc_pm.data.sfrbu + offset);
613 /* Wait for update. */
614 val = readl(soc_pm.data.sfrbu + offset);
615 while (val & soc_pm.sfrbu_regs.pswbu.state)
616 val = readl(soc_pm.data.sfrbu + offset);
619 static void at91_pm_suspend(suspend_state_t state)
621 if (soc_pm.data.mode == AT91_PM_BACKUP) {
622 at91_pm_switch_ba_to_vbat();
624 cpu_suspend(0, at91_suspend_finish);
626 /* The SRAM is lost between suspend cycles */
627 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
628 &at91_pm_suspend_in_sram,
629 at91_pm_suspend_in_sram_sz);
631 at91_suspend_finish(0);
638 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
639 * event sources; and reduces DRAM power. But otherwise it's identical to
640 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
642 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
643 * suspend more deeply, the master clock switches to the clk32k and turns off
644 * the main oscillator
646 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
648 static int at91_pm_enter(suspend_state_t state)
652 ret = at91_pm_config_quirks(true);
658 case PM_SUSPEND_STANDBY:
660 * Ensure that clocks are in a valid state.
662 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
663 !at91_pm_verify_clocks())
666 at91_pm_suspend(state);
675 pr_debug("AT91: PM - bogus suspend state %d\n", state);
680 at91_pm_config_quirks(false);
685 * Called right prior to thawing processes.
687 static void at91_pm_end(void)
689 at91_pm_config_ws(soc_pm.data.mode, false);
693 static const struct platform_suspend_ops at91_pm_ops = {
694 .valid = at91_pm_valid_state,
695 .begin = at91_pm_begin,
696 .enter = at91_pm_enter,
700 static struct platform_device at91_cpuidle_device = {
701 .name = "cpuidle-at91",
705 * The AT91RM9200 goes into self-refresh mode with this command, and will
706 * terminate self-refresh automatically on the next SDRAM access.
708 * Self-refresh mode is exited as soon as a memory access is made, but we don't
709 * know for sure when that happens. However, we need to restore the low-power
710 * mode if it was enabled before going idle. Restoring low-power mode while
711 * still in self-refresh is "not recommended", but seems to work.
713 static void at91rm9200_standby(void)
718 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
719 " str %2, [%1, %3]\n\t"
720 " mcr p15, 0, %0, c7, c0, 4\n\t"
722 : "r" (0), "r" (soc_pm.data.ramc[0]),
723 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
726 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
729 static void at91_ddr_standby(void)
731 /* Those two values allow us to delay self-refresh activation
734 u32 mdr, saved_mdr0, saved_mdr1 = 0;
735 u32 saved_lpr0, saved_lpr1 = 0;
737 /* LPDDR1 --> force DDR2 mode during self-refresh */
738 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
739 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
740 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
741 mdr |= AT91_DDRSDRC_MD_DDR2;
742 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
745 if (soc_pm.data.ramc[1]) {
746 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
747 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
748 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
749 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
750 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
751 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
752 mdr |= AT91_DDRSDRC_MD_DDR2;
753 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
757 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
758 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
759 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
761 /* self-refresh mode now */
762 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
763 if (soc_pm.data.ramc[1])
764 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
768 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
769 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
770 if (soc_pm.data.ramc[1]) {
771 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
772 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
776 static void sama5d3_ddr_standby(void)
781 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
782 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
783 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
785 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
789 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
792 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
795 static void at91sam9_sdram_standby(void)
798 u32 saved_lpr0, saved_lpr1 = 0;
800 if (soc_pm.data.ramc[1]) {
801 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
802 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
803 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
806 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
807 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
808 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
810 /* self-refresh mode now */
811 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
812 if (soc_pm.data.ramc[1])
813 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
817 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
818 if (soc_pm.data.ramc[1])
819 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
822 static void sama7g5_standby(void)
826 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
827 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
830 * Place RAM into self-refresh after a maximum idle clocks. The maximum
831 * idle clocks is configured by bootloader in
832 * UDDRC_PWRMGT.SELFREF_TO_X32.
834 writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
835 soc_pm.data.ramc[0] + UDDRC_PWRCTL);
836 /* Divide CPU clock by 16. */
837 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
841 /* Restore previous configuration. */
842 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
843 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
848 unsigned int memctrl;
851 static const struct ramc_info ramc_infos[] __initconst = {
852 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
853 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
854 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
855 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
856 { .idle = sama7g5_standby, },
859 static const struct of_device_id ramc_ids[] __initconst = {
860 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
861 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
862 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
863 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
864 { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
868 static const struct of_device_id ramc_phy_ids[] __initconst = {
869 { .compatible = "microchip,sama7g5-ddr3phy", },
873 static __init int at91_dt_ramc(bool phy_mandatory)
875 struct device_node *np;
876 const struct of_device_id *of_id;
878 void *standby = NULL;
879 const struct ramc_info *ramc;
882 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
883 soc_pm.data.ramc[idx] = of_iomap(np, 0);
884 if (!soc_pm.data.ramc[idx]) {
885 pr_err("unable to map ramc[%d] cpu registers\n", idx);
894 standby = ramc->idle;
895 soc_pm.data.memctrl = ramc->memctrl;
902 pr_err("unable to find compatible ram controller node in dtb\n");
907 /* Lookup for DDR PHY node, if any. */
908 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
909 soc_pm.data.ramc_phy = of_iomap(np, 0);
910 if (!soc_pm.data.ramc_phy) {
911 pr_err("unable to map ramc phy cpu registers\n");
918 if (phy_mandatory && !soc_pm.data.ramc_phy) {
919 pr_err("DDR PHY is mandatory!\n");
925 pr_warn("ramc no standby function available\n");
929 at91_cpuidle_device.dev.platform_data = standby;
935 iounmap(soc_pm.data.ramc[--idx]);
940 static void at91rm9200_idle(void)
943 * Disable the processor clock. The processor will be automatically
944 * re-enabled by an interrupt or by a reset.
946 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
949 static void at91sam9_idle(void)
951 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
955 static void __init at91_pm_sram_init(void)
957 struct gen_pool *sram_pool;
958 phys_addr_t sram_pbase;
959 unsigned long sram_base;
960 struct device_node *node;
961 struct platform_device *pdev = NULL;
963 for_each_compatible_node(node, NULL, "mmio-sram") {
964 pdev = of_find_device_by_node(node);
972 pr_warn("%s: failed to find sram device!\n", __func__);
976 sram_pool = gen_pool_get(&pdev->dev, NULL);
978 pr_warn("%s: sram pool unavailable!\n", __func__);
982 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
984 pr_warn("%s: unable to alloc sram!\n", __func__);
988 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
989 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
990 at91_pm_suspend_in_sram_sz, false);
991 if (!at91_suspend_sram_fn) {
992 pr_warn("SRAM: Could not map\n");
996 /* Copy the pm suspend handler to SRAM */
997 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
998 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
1002 put_device(&pdev->dev);
1006 static bool __init at91_is_pm_mode_active(int pm_mode)
1008 return (soc_pm.data.standby_mode == pm_mode ||
1009 soc_pm.data.suspend_mode == pm_mode);
1012 static int __init at91_pm_backup_scan_memcs(unsigned long node,
1013 const char *uname, int depth,
1018 int *located = data;
1021 /* Memory node already located. */
1025 type = of_get_flat_dt_prop(node, "device_type", NULL);
1027 /* We are scanning "memory" nodes only. */
1028 if (!type || strcmp(type, "memory"))
1031 reg = of_get_flat_dt_prop(node, "reg", &size);
1033 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
1040 static int __init at91_pm_backup_init(void)
1042 struct gen_pool *sram_pool;
1043 struct device_node *np;
1044 struct platform_device *pdev;
1045 int ret = -ENODEV, located = 0;
1047 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
1048 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
1051 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
1054 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
1058 pdev = of_find_device_by_node(np);
1061 pr_warn("%s: failed to find securam device!\n", __func__);
1065 sram_pool = gen_pool_get(&pdev->dev, NULL);
1067 pr_warn("%s: securam pool unavailable!\n", __func__);
1071 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
1073 pr_warn("%s: unable to alloc securam!\n", __func__);
1078 soc_pm.bu->suspended = 0;
1079 soc_pm.bu->canary = __pa_symbol(&canary);
1080 soc_pm.bu->resume = __pa_symbol(cpu_resume);
1081 if (soc_pm.data.ramc_phy) {
1082 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
1090 put_device(&pdev->dev);
1094 static void __init at91_pm_secure_init(void)
1097 struct arm_smccc_res res;
1099 suspend_mode = soc_pm.data.suspend_mode;
1101 res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE,
1104 pr_info("AT91: Secure PM: suspend mode set to %s\n",
1105 pm_modes[suspend_mode].pattern);
1106 soc_pm.data.mode = suspend_mode;
1110 pr_warn("AT91: Secure PM: %s mode not supported !\n",
1111 pm_modes[suspend_mode].pattern);
1113 res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
1115 pr_warn("AT91: Secure PM: failed to get default mode\n");
1116 soc_pm.data.mode = -1;
1120 pr_info("AT91: Secure PM: using default suspend mode %s\n",
1121 pm_modes[suspend_mode].pattern);
1123 soc_pm.data.suspend_mode = res.a1;
1124 soc_pm.data.mode = soc_pm.data.suspend_mode;
1126 static const struct of_device_id atmel_shdwc_ids[] = {
1127 { .compatible = "atmel,sama5d2-shdwc" },
1128 { .compatible = "microchip,sam9x60-shdwc" },
1129 { .compatible = "microchip,sama7g5-shdwc" },
1133 static const struct of_device_id gmac_ids[] __initconst = {
1134 { .compatible = "atmel,sama5d3-gem" },
1135 { .compatible = "atmel,sama5d2-gem" },
1136 { .compatible = "atmel,sama5d29-gem" },
1137 { .compatible = "microchip,sama7g5-gem" },
1141 static const struct of_device_id emac_ids[] __initconst = {
1142 { .compatible = "atmel,sama5d3-macb" },
1143 { .compatible = "microchip,sama7g5-emac" },
1148 * Replaces _mode_to_replace with a supported mode that doesn't depend
1149 * on controller pointed by _map_bitmask
1150 * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91
1152 * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on
1153 * controller represented by _map_bitmask, _mode_to_replace needs to be
1155 * @_mode_to_replace: standby_mode or suspend_mode that need to be
1157 * @_mode_to_check: standby_mode or suspend_mode; this is needed here
1158 * to avoid having standby_mode and suspend_mode set with the same AT91
1161 #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \
1164 if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \
1165 int _mode_to_use, _mode_complementary; \
1166 /* Use ULP0 if it doesn't need _map_bitmask. */ \
1167 if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\
1168 _mode_to_use = AT91_PM_ULP0; \
1169 _mode_complementary = AT91_PM_STANDBY; \
1171 _mode_to_use = AT91_PM_STANDBY; \
1172 _mode_complementary = AT91_PM_STANDBY; \
1175 if ((_mode_to_check) != _mode_to_use) \
1176 (_mode_to_replace) = _mode_to_use; \
1178 (_mode_to_replace) = _mode_complementary;\
1183 * Replaces standby and suspend modes with default supported modes:
1185 * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP()
1187 * @_map: controller specific name; standby and suspend mode need to be
1188 * replaced in order to not depend on this controller
1190 #define AT91_PM_REPLACE_MODES(_maps, _map) \
1192 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
1193 (soc_pm.data.standby_mode), \
1194 (soc_pm.data.suspend_mode)); \
1195 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
1196 (soc_pm.data.suspend_mode), \
1197 (soc_pm.data.standby_mode)); \
1200 static int __init at91_pm_get_eth_clks(struct device_node *np,
1201 struct clk_bulk_data *clks)
1203 clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk");
1204 if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk))
1205 return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk);
1207 clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk");
1208 if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk))
1209 return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk);
1214 static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks)
1216 return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) ||
1217 IS_ERR(clks[AT91_PM_ETH_HCLK].clk);
1220 static void __init at91_pm_modes_init(const u32 *maps, int len)
1222 struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
1223 struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
1224 struct device_node *np;
1227 ret = at91_pm_backup_init();
1229 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
1230 soc_pm.data.standby_mode = AT91_PM_ULP0;
1231 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
1232 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1235 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1236 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
1237 np = of_find_matching_node(NULL, atmel_shdwc_ids);
1239 pr_warn("%s: failed to find shdwc!\n", __func__);
1240 AT91_PM_REPLACE_MODES(maps, SHDWC);
1242 soc_pm.data.shdwc = of_iomap(np, 0);
1247 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1248 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
1249 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
1251 pr_warn("%s: failed to find sfrbu!\n", __func__);
1252 AT91_PM_REPLACE_MODES(maps, SFRBU);
1254 soc_pm.data.sfrbu = of_iomap(np, 0);
1259 if ((at91_is_pm_mode_active(AT91_PM_ULP1) ||
1260 at91_is_pm_mode_active(AT91_PM_ULP0) ||
1261 at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) &&
1262 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
1263 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
1264 np = of_find_matching_node(NULL, gmac_ids);
1266 np = of_find_matching_node(NULL, emac_ids);
1269 AT91_PM_REPLACE_MODES(maps, ETHC);
1270 goto unmap_unused_nodes;
1273 at91_pm_get_eth_clks(np, gmac->clks);
1276 np = of_find_matching_node(NULL, emac_ids);
1278 if (at91_pm_eth_clks_empty(gmac->clks))
1279 AT91_PM_REPLACE_MODES(maps, ETHC);
1283 ret = at91_pm_get_eth_clks(np, emac->clks);
1284 if (ret && at91_pm_eth_clks_empty(gmac->clks)) {
1285 of_node_put(gmac->np);
1286 of_node_put(emac->np);
1294 /* Unmap all unnecessary. */
1295 if (soc_pm.data.shdwc &&
1296 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1297 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
1298 iounmap(soc_pm.data.shdwc);
1299 soc_pm.data.shdwc = NULL;
1302 if (soc_pm.data.sfrbu &&
1303 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1304 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
1305 iounmap(soc_pm.data.sfrbu);
1306 soc_pm.data.sfrbu = NULL;
1313 unsigned long uhp_udp_mask;
1315 unsigned long version;
1318 static const struct pmc_info pmc_infos[] __initconst = {
1320 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
1322 .version = AT91_PMC_V1,
1326 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1328 .version = AT91_PMC_V1,
1331 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
1333 .version = AT91_PMC_V1,
1335 { .uhp_udp_mask = 0,
1337 .version = AT91_PMC_V1,
1340 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1342 .version = AT91_PMC_V2,
1346 .version = AT91_PMC_V2,
1351 static const struct of_device_id atmel_pmc_ids[] __initconst = {
1352 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
1353 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
1354 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
1355 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
1356 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
1357 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
1358 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
1359 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
1360 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
1361 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
1362 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
1363 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
1364 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
1368 static void __init at91_pm_modes_validate(const int *modes, int len)
1370 u8 i, standby = 0, suspend = 0;
1373 for (i = 0; i < len; i++) {
1374 if (standby && suspend)
1377 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1382 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1389 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1390 mode = AT91_PM_ULP0;
1392 mode = AT91_PM_STANDBY;
1394 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1395 pm_modes[soc_pm.data.standby_mode].pattern,
1396 pm_modes[mode].pattern);
1397 soc_pm.data.standby_mode = mode;
1401 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1402 mode = AT91_PM_STANDBY;
1404 mode = AT91_PM_ULP0;
1406 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1407 pm_modes[soc_pm.data.suspend_mode].pattern,
1408 pm_modes[mode].pattern);
1409 soc_pm.data.suspend_mode = mode;
1413 static void __init at91_pm_init(void (*pm_idle)(void))
1415 struct device_node *pmc_np;
1416 const struct of_device_id *of_id;
1417 const struct pmc_info *pmc;
1419 if (at91_cpuidle_device.dev.platform_data)
1420 platform_device_register(&at91_cpuidle_device);
1422 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
1423 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1424 of_node_put(pmc_np);
1425 if (!soc_pm.data.pmc) {
1426 pr_err("AT91: PM not supported, PMC not found\n");
1431 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1432 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1433 soc_pm.data.pmc_version = pmc->version;
1436 arm_pm_idle = pm_idle;
1438 at91_pm_sram_init();
1440 if (at91_suspend_sram_fn) {
1441 suspend_set_ops(&at91_pm_ops);
1442 pr_info("AT91: PM: standby: %s, suspend: %s\n",
1443 pm_modes[soc_pm.data.standby_mode].pattern,
1444 pm_modes[soc_pm.data.suspend_mode].pattern);
1446 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1450 void __init at91rm9200_pm_init(void)
1454 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1458 * Force STANDBY and ULP0 mode to avoid calling
1459 * at91_pm_modes_validate() which may increase booting time.
1460 * Platform supports anyway only STANDBY and ULP0 modes.
1462 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1463 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1465 ret = at91_dt_ramc(false);
1470 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1472 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1474 at91_pm_init(at91rm9200_idle);
1477 void __init sam9x60_pm_init(void)
1479 static const int modes[] __initconst = {
1480 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1482 static const int iomaps[] __initconst = {
1483 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1487 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1490 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1491 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1492 ret = at91_dt_ramc(false);
1498 soc_pm.ws_ids = sam9x60_ws_ids;
1499 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1502 void __init at91sam9_pm_init(void)
1506 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1510 * Force STANDBY and ULP0 mode to avoid calling
1511 * at91_pm_modes_validate() which may increase booting time.
1512 * Platform supports anyway only STANDBY and ULP0 modes.
1514 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1515 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1517 ret = at91_dt_ramc(false);
1521 at91_pm_init(at91sam9_idle);
1524 void __init sama5_pm_init(void)
1526 static const int modes[] __initconst = {
1527 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1529 static const u32 iomaps[] __initconst = {
1530 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
1531 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
1535 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1538 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1539 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1540 ret = at91_dt_ramc(false);
1546 /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */
1547 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1548 BIT(AT91_PM_ULP0_FAST) |
1550 /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */
1551 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1552 BIT(AT91_PM_ULP0_FAST);
1555 void __init sama5d2_pm_init(void)
1557 static const int modes[] __initconst = {
1558 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1561 static const u32 iomaps[] __initconst = {
1562 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
1563 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
1564 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) |
1565 AT91_PM_IOMAP(ETHC),
1566 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1567 AT91_PM_IOMAP(SFRBU),
1571 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1574 if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) {
1575 pr_warn("AT91: Secure PM: ignoring standby mode\n");
1576 at91_pm_secure_init();
1580 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1581 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1582 ret = at91_dt_ramc(false);
1588 soc_pm.ws_ids = sama5d2_ws_ids;
1589 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1590 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1592 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1593 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1594 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1595 soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1597 /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */
1598 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1599 BIT(AT91_PM_ULP0_FAST) |
1602 * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup
1605 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1606 BIT(AT91_PM_ULP0_FAST);
1609 void __init sama7_pm_init(void)
1611 static const int modes[] __initconst = {
1612 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1614 static const u32 iomaps[] __initconst = {
1615 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
1616 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
1617 AT91_PM_IOMAP(SHDWC) |
1618 AT91_PM_IOMAP(ETHC),
1619 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
1620 AT91_PM_IOMAP(SHDWC),
1624 if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1627 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1629 ret = at91_dt_ramc(true);
1633 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1636 soc_pm.ws_ids = sama7g5_ws_ids;
1637 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1639 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1640 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1641 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1642 soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1644 /* Quirks applies to ULP1 for both Ethernet interfaces. */
1645 soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
1646 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
1649 static int __init at91_pm_modes_select(char *str)
1652 substring_t args[MAX_OPT_ARGS];
1653 int standby, suspend;
1658 s = strsep(&str, ",");
1659 standby = match_token(s, pm_modes, args);
1663 suspend = match_token(str, pm_modes, args);
1667 soc_pm.data.standby_mode = standby;
1668 soc_pm.data.suspend_mode = suspend;
1672 early_param("atmel.pm_modes", at91_pm_modes_select);