1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* ld script to make ARM Linux kernel
3 * taken from the i386 version by Russell King
4 * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
7 /* No __ro_after_init data in the .rodata section - which will always be ro */
8 #define RO_AFTER_INIT_DATA
10 #include <linux/sizes.h>
12 #include <asm-generic/vmlinux.lds.h>
13 #include <asm/cache.h>
14 #include <asm/thread_info.h>
15 #include <asm/memory.h>
19 #include "vmlinux.lds.h"
27 jiffies = jiffies_64 + 4;
33 * XXX: The linker does not define how output sections are
34 * assigned to input sections when there are multiple statements
35 * matching the same input section name. There is no documented
38 * unwind exit sections must be discarded before the rest of the
39 * unwind sections get included.
47 . = XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR);
48 _xiprom = .; /* XIP ROM area to be mapped */
55 .text : { /* Real text segment */
56 _stext = .; /* Text and read-only data */
63 __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
64 __start___ex_table = .;
65 ARM_MMU_KEEP(*(__ex_table))
66 __stop___ex_table = .;
69 #ifdef CONFIG_ARM_UNWIND
75 _etext = .; /* End of text and rodata section */
80 ARM_EXIT_KEEP(EXIT_TEXT)
83 ARM_CPU_DISCARD(PROC_INFO)
86 __arch_info_begin = .;
103 #ifdef CONFIG_ARM_MPU
106 _exiprom = .; /* End of XIP ROM area */
109 * From this point, stuff is considered writable and will be copied to RAM
111 __data_loc = ALIGN(4); /* location in file */
112 . = PAGE_OFFSET + TEXT_OFFSET; /* location in memory */
114 #define LOAD_OFFSET (PAGE_OFFSET + TEXT_OFFSET - __data_loc)
116 . = ALIGN(THREAD_SIZE);
118 RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
119 .data.ro_after_init : AT(ADDR(.data.ro_after_init) - LOAD_OFFSET) {
120 *(.data..ro_after_init)
124 . = ALIGN(PAGE_SIZE);
126 .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
129 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
130 ARM_EXIT_KEEP(EXIT_DATA)
133 PERCPU_SECTION(L1_CACHE_BYTES)
136 #ifdef CONFIG_HAVE_TCM
141 * End of copied data. We need a dummy section to get its LMA.
142 * Also located before final ALIGN() as trailing padding is not stored
143 * in the resulting binary file and useless to copy.
145 .data.endmark : AT(ADDR(.data.endmark) - LOAD_OFFSET) { }
146 _edata_loc = LOADADDR(.data.endmark);
148 . = ALIGN(PAGE_SIZE);
152 #ifdef CONFIG_ARM_MPU
153 . = ALIGN(PMSAv8_MINALIGN);
161 * These must never be empty
162 * If you have to comment these two assert statements out, your
163 * binutils is too old (for other reasons as well)
165 ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
166 ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
169 * The HYP init code can't be more than a page long,
170 * and should not cross a page boundary.
171 * The above comment applies as well.
173 ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & PAGE_MASK) <= PAGE_SIZE,
174 "HYP init code too big or misaligned")
176 #ifdef CONFIG_XIP_DEFLATED_DATA
178 * The .bss is used as a stack area for __inflate_kernel_data() whose stack
179 * frame is 9568 bytes. Make sure it has extra room left.
181 ASSERT((_end - __bss_start) >= 12288, ".bss too small for CONFIG_XIP_DEFLATED_DATA")
184 #if defined(CONFIG_ARM_MPU) && !defined(CONFIG_COMPILE_TEST)
186 * Due to PMSAv7 restriction on base address and size we have to
187 * enforce minimal alignment restrictions. It was seen that weaker
188 * alignment restriction on _xiprom will likely force XIP address
189 * space spawns multiple MPU regions thus it is likely we run in
190 * situation when we are reprogramming MPU region we run on with
191 * something which doesn't cover reprogramming code itself, so as soon
192 * as we update MPU settings we'd immediately try to execute straight
193 * from background region which is XN.
194 * It seem that alignment in 1M should suit most users.
195 * _exiprom is aligned as 1/8 of 1M so can be covered by subregion
198 ASSERT(!(_xiprom & (SZ_1M - 1)), "XIP start address may cause MPU programming issues")
199 ASSERT(!(_exiprom & (SZ_128K - 1)), "XIP end address may cause MPU programming issues")