1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/kernel/setup.c
5 * Copyright (C) 1995-2001 Russell King
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/stddef.h>
11 #include <linux/ioport.h>
12 #include <linux/delay.h>
13 #include <linux/utsname.h>
14 #include <linux/initrd.h>
15 #include <linux/console.h>
16 #include <linux/seq_file.h>
17 #include <linux/screen_info.h>
18 #include <linux/of_platform.h>
19 #include <linux/init.h>
20 #include <linux/kexec.h>
21 #include <linux/libfdt.h>
22 #include <linux/of_fdt.h>
23 #include <linux/cpu.h>
24 #include <linux/interrupt.h>
25 #include <linux/smp.h>
26 #include <linux/proc_fs.h>
27 #include <linux/memblock.h>
28 #include <linux/bug.h>
29 #include <linux/compiler.h>
30 #include <linux/sort.h>
31 #include <linux/psci.h>
33 #include <asm/unified.h>
36 #include <asm/cputype.h>
39 #include <asm/early_ioremap.h>
40 #include <asm/fixmap.h>
41 #include <asm/procinfo.h>
43 #include <asm/sections.h>
44 #include <asm/setup.h>
45 #include <asm/smp_plat.h>
46 #include <asm/mach-types.h>
47 #include <asm/cacheflush.h>
48 #include <asm/cachetype.h>
49 #include <asm/tlbflush.h>
50 #include <asm/xen/hypervisor.h>
53 #include <asm/mach/arch.h>
54 #include <asm/mach/irq.h>
55 #include <asm/mach/time.h>
56 #include <asm/system_info.h>
57 #include <asm/system_misc.h>
58 #include <asm/traps.h>
59 #include <asm/unwind.h>
60 #include <asm/memblock.h>
62 #include <asm/kasan.h>
67 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
70 static int __init fpe_setup(char *line)
72 memcpy(fpe_type, line, 8);
76 __setup("fpe=", fpe_setup);
79 extern void init_default_cache_policy(unsigned long);
80 extern void paging_init(const struct machine_desc *desc);
81 extern void early_mm_init(const struct machine_desc *);
82 extern void adjust_lowmem_bounds(void);
83 extern enum reboot_mode reboot_mode;
84 extern void setup_dma_zone(const struct machine_desc *desc);
86 unsigned int processor_id;
87 EXPORT_SYMBOL(processor_id);
88 unsigned int __machine_arch_type __read_mostly;
89 EXPORT_SYMBOL(__machine_arch_type);
90 unsigned int cacheid __read_mostly;
91 EXPORT_SYMBOL(cacheid);
93 unsigned int __atags_pointer __initdata;
95 unsigned int system_rev;
96 EXPORT_SYMBOL(system_rev);
98 const char *system_serial;
99 EXPORT_SYMBOL(system_serial);
101 unsigned int system_serial_low;
102 EXPORT_SYMBOL(system_serial_low);
104 unsigned int system_serial_high;
105 EXPORT_SYMBOL(system_serial_high);
107 unsigned int elf_hwcap __read_mostly;
108 EXPORT_SYMBOL(elf_hwcap);
110 unsigned int elf_hwcap2 __read_mostly;
111 EXPORT_SYMBOL(elf_hwcap2);
115 struct processor processor __ro_after_init;
116 #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
117 struct processor *cpu_vtable[NR_CPUS] = {
123 struct cpu_tlb_fns cpu_tlb __ro_after_init;
126 struct cpu_user_fns cpu_user __ro_after_init;
129 struct cpu_cache_fns cpu_cache __ro_after_init;
131 #ifdef CONFIG_OUTER_CACHE
132 struct outer_cache_fns outer_cache __ro_after_init;
133 EXPORT_SYMBOL(outer_cache);
137 * Cached cpu_architecture() result for use by assembler code.
138 * C code should use the cpu_architecture() function instead of accessing this
141 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
148 } ____cacheline_aligned;
150 #ifndef CONFIG_CPU_V7M
151 static struct stack stacks[NR_CPUS];
154 char elf_platform[ELF_PLATFORM_SIZE];
155 EXPORT_SYMBOL(elf_platform);
157 static const char *cpu_name;
158 static const char *machine_name;
159 static char __initdata cmd_line[COMMAND_LINE_SIZE];
160 const struct machine_desc *machine_desc __initdata;
162 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
163 #define ENDIANNESS ((char)endian_test.l)
165 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
168 * Standard memory resources
170 static struct resource mem_res[] = {
175 .flags = IORESOURCE_MEM
178 .name = "Kernel code",
181 .flags = IORESOURCE_SYSTEM_RAM
184 .name = "Kernel data",
187 .flags = IORESOURCE_SYSTEM_RAM
191 #define video_ram mem_res[0]
192 #define kernel_code mem_res[1]
193 #define kernel_data mem_res[2]
195 static struct resource io_res[] = {
200 .flags = IORESOURCE_IO | IORESOURCE_BUSY
206 .flags = IORESOURCE_IO | IORESOURCE_BUSY
212 .flags = IORESOURCE_IO | IORESOURCE_BUSY
216 #define lp0 io_res[0]
217 #define lp1 io_res[1]
218 #define lp2 io_res[2]
220 static const char *proc_arch[] = {
240 #ifdef CONFIG_CPU_V7M
241 static int __get_cpu_architecture(void)
243 return CPU_ARCH_ARMv7M;
246 static int __get_cpu_architecture(void)
250 if ((read_cpuid_id() & 0x0008f000) == 0) {
251 cpu_arch = CPU_ARCH_UNKNOWN;
252 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
253 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
254 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
255 cpu_arch = (read_cpuid_id() >> 16) & 7;
257 cpu_arch += CPU_ARCH_ARMv3;
258 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
259 /* Revised CPUID format. Read the Memory Model Feature
260 * Register 0 and check for VMSAv7 or PMSAv7 */
261 unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
262 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
263 (mmfr0 & 0x000000f0) >= 0x00000030)
264 cpu_arch = CPU_ARCH_ARMv7;
265 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
266 (mmfr0 & 0x000000f0) == 0x00000020)
267 cpu_arch = CPU_ARCH_ARMv6;
269 cpu_arch = CPU_ARCH_UNKNOWN;
271 cpu_arch = CPU_ARCH_UNKNOWN;
277 int __pure cpu_architecture(void)
279 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
281 return __cpu_architecture;
284 static int cpu_has_aliasing_icache(unsigned int arch)
287 unsigned int id_reg, num_sets, line_size;
289 /* PIPT caches never alias. */
290 if (icache_is_pipt())
293 /* arch specifies the register format */
296 set_csselr(CSSELR_ICACHE | CSSELR_L1);
298 id_reg = read_ccsidr();
299 line_size = 4 << ((id_reg & 0x7) + 2);
300 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
301 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
304 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
307 /* I-cache aliases will be handled by D-cache aliasing code */
311 return aliasing_icache;
314 static void __init cacheid_init(void)
316 unsigned int arch = cpu_architecture();
318 if (arch >= CPU_ARCH_ARMv6) {
319 unsigned int cachetype = read_cpuid_cachetype();
321 if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
323 } else if ((cachetype & (7 << 29)) == 4 << 29) {
324 /* ARMv7 register format */
325 arch = CPU_ARCH_ARMv7;
326 cacheid = CACHEID_VIPT_NONALIASING;
327 switch (cachetype & (3 << 14)) {
329 cacheid |= CACHEID_ASID_TAGGED;
332 cacheid |= CACHEID_PIPT;
336 arch = CPU_ARCH_ARMv6;
337 if (cachetype & (1 << 23))
338 cacheid = CACHEID_VIPT_ALIASING;
340 cacheid = CACHEID_VIPT_NONALIASING;
342 if (cpu_has_aliasing_icache(arch))
343 cacheid |= CACHEID_VIPT_I_ALIASING;
345 cacheid = CACHEID_VIVT;
348 pr_info("CPU: %s data cache, %s instruction cache\n",
349 cache_is_vivt() ? "VIVT" :
350 cache_is_vipt_aliasing() ? "VIPT aliasing" :
351 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
352 cache_is_vivt() ? "VIVT" :
353 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
354 icache_is_vipt_aliasing() ? "VIPT aliasing" :
355 icache_is_pipt() ? "PIPT" :
356 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
360 * These functions re-use the assembly code in head.S, which
361 * already provide the required functionality.
363 extern struct proc_info_list *lookup_processor_type(unsigned int);
365 void __init early_print(const char *str, ...)
367 extern void printascii(const char *);
372 vsnprintf(buf, sizeof(buf), str, ap);
375 #ifdef CONFIG_DEBUG_LL
381 #ifdef CONFIG_ARM_PATCH_IDIV
383 static inline u32 __attribute_const__ sdiv_instruction(void)
385 if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
386 /* "sdiv r0, r0, r1" */
387 u32 insn = __opcode_thumb32_compose(0xfb90, 0xf0f1);
388 return __opcode_to_mem_thumb32(insn);
391 /* "sdiv r0, r0, r1" */
392 return __opcode_to_mem_arm(0xe710f110);
395 static inline u32 __attribute_const__ udiv_instruction(void)
397 if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
398 /* "udiv r0, r0, r1" */
399 u32 insn = __opcode_thumb32_compose(0xfbb0, 0xf0f1);
400 return __opcode_to_mem_thumb32(insn);
403 /* "udiv r0, r0, r1" */
404 return __opcode_to_mem_arm(0xe730f110);
407 static inline u32 __attribute_const__ bx_lr_instruction(void)
409 if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
411 u32 insn = __opcode_thumb32_compose(0x4770, 0x46c0);
412 return __opcode_to_mem_thumb32(insn);
416 return __opcode_to_mem_arm(0xe12fff1e);
419 static void __init patch_aeabi_idiv(void)
421 extern void __aeabi_uidiv(void);
422 extern void __aeabi_idiv(void);
426 mask = IS_ENABLED(CONFIG_THUMB2_KERNEL) ? HWCAP_IDIVT : HWCAP_IDIVA;
427 if (!(elf_hwcap & mask))
430 pr_info("CPU: div instructions available: patching division code\n");
432 fn_addr = ((uintptr_t)&__aeabi_uidiv) & ~1;
433 asm ("" : "+g" (fn_addr));
434 ((u32 *)fn_addr)[0] = udiv_instruction();
435 ((u32 *)fn_addr)[1] = bx_lr_instruction();
436 flush_icache_range(fn_addr, fn_addr + 8);
438 fn_addr = ((uintptr_t)&__aeabi_idiv) & ~1;
439 asm ("" : "+g" (fn_addr));
440 ((u32 *)fn_addr)[0] = sdiv_instruction();
441 ((u32 *)fn_addr)[1] = bx_lr_instruction();
442 flush_icache_range(fn_addr, fn_addr + 8);
446 static inline void patch_aeabi_idiv(void) { }
449 static void __init cpuid_init_hwcaps(void)
454 if (cpu_architecture() < CPU_ARCH_ARMv7)
457 block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
459 elf_hwcap |= HWCAP_IDIVA;
461 elf_hwcap |= HWCAP_IDIVT;
463 /* LPAE implies atomic ldrd/strd instructions */
464 block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
466 elf_hwcap |= HWCAP_LPAE;
468 /* check for supported v8 Crypto instructions */
469 isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
471 block = cpuid_feature_extract_field(isar5, 4);
473 elf_hwcap2 |= HWCAP2_PMULL;
475 elf_hwcap2 |= HWCAP2_AES;
477 block = cpuid_feature_extract_field(isar5, 8);
479 elf_hwcap2 |= HWCAP2_SHA1;
481 block = cpuid_feature_extract_field(isar5, 12);
483 elf_hwcap2 |= HWCAP2_SHA2;
485 block = cpuid_feature_extract_field(isar5, 16);
487 elf_hwcap2 |= HWCAP2_CRC32;
490 static void __init elf_hwcap_fixup(void)
492 unsigned id = read_cpuid_id();
495 * HWCAP_TLS is available only on 1136 r1p0 and later,
496 * see also kuser_get_tls_init.
498 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
499 ((id >> 20) & 3) == 0) {
500 elf_hwcap &= ~HWCAP_TLS;
504 /* Verify if CPUID scheme is implemented */
505 if ((id & 0x000f0000) != 0x000f0000)
509 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
510 * avoid advertising SWP; it may not be atomic with
511 * multiprocessing cores.
513 if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
514 (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
515 cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
516 elf_hwcap &= ~HWCAP_SWP;
520 * cpu_init - initialise one CPU.
522 * cpu_init sets up the per-CPU stacks.
524 void notrace cpu_init(void)
526 #ifndef CONFIG_CPU_V7M
527 unsigned int cpu = smp_processor_id();
528 struct stack *stk = &stacks[cpu];
530 if (cpu >= NR_CPUS) {
531 pr_crit("CPU%u: bad primary CPU number\n", cpu);
536 * This only works on resume and secondary cores. For booting on the
537 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
539 set_my_cpu_offset(per_cpu_offset(cpu));
544 * Define the placement constraint for the inline asm directive below.
545 * In Thumb-2, msr with an immediate value is not allowed.
547 #ifdef CONFIG_THUMB2_KERNEL
556 * setup stacks for re-entrant exception handlers
560 "add r14, %0, %2\n\t"
563 "add r14, %0, %4\n\t"
566 "add r14, %0, %6\n\t"
569 "add r14, %0, %8\n\t"
574 PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
575 "I" (offsetof(struct stack, irq[0])),
576 PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
577 "I" (offsetof(struct stack, abt[0])),
578 PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
579 "I" (offsetof(struct stack, und[0])),
580 PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
581 "I" (offsetof(struct stack, fiq[0])),
582 PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
587 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
589 void __init smp_setup_processor_id(void)
592 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
593 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
595 cpu_logical_map(0) = cpu;
596 for (i = 1; i < nr_cpu_ids; ++i)
597 cpu_logical_map(i) = i == cpu ? 0 : i;
600 * clear __my_cpu_offset on boot CPU to avoid hang caused by
601 * using percpu variable early, for example, lockdep will
602 * access percpu variable inside lock_release
604 set_my_cpu_offset(0);
606 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
609 struct mpidr_hash mpidr_hash;
612 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
613 * level in order to build a linear index from an
614 * MPIDR value. Resulting algorithm is a collision
615 * free hash carried out through shifting and ORing
617 static void __init smp_build_mpidr_hash(void)
620 u32 fs[3], bits[3], ls, mask = 0;
622 * Pre-scan the list of MPIDRS and filter out bits that do
623 * not contribute to affinity levels, ie they never toggle.
625 for_each_possible_cpu(i)
626 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
627 pr_debug("mask of set bits 0x%x\n", mask);
629 * Find and stash the last and first bit set at all affinity levels to
630 * check how many bits are required to represent them.
632 for (i = 0; i < 3; i++) {
633 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
635 * Find the MSB bit and LSB bits position
636 * to determine how many bits are required
637 * to express the affinity level.
640 fs[i] = affinity ? ffs(affinity) - 1 : 0;
641 bits[i] = ls - fs[i];
644 * An index can be created from the MPIDR by isolating the
645 * significant bits at each affinity level and by shifting
646 * them in order to compress the 24 bits values space to a
647 * compressed set of values. This is equivalent to hashing
648 * the MPIDR through shifting and ORing. It is a collision free
649 * hash though not minimal since some levels might contain a number
650 * of CPUs that is not an exact power of 2 and their bit
651 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
653 mpidr_hash.shift_aff[0] = fs[0];
654 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
655 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
657 mpidr_hash.mask = mask;
658 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
659 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
660 mpidr_hash.shift_aff[0],
661 mpidr_hash.shift_aff[1],
662 mpidr_hash.shift_aff[2],
666 * 4x is an arbitrary value used to warn on a hash table much bigger
667 * than expected on most systems.
669 if (mpidr_hash_size() > 4 * num_possible_cpus())
670 pr_warn("Large number of MPIDR hash buckets detected\n");
671 sync_cache_w(&mpidr_hash);
676 * locate processor in the list of supported processor types. The linker
677 * builds this table for us from the entries in arch/arm/mm/proc-*.S
679 struct proc_info_list *lookup_processor(u32 midr)
681 struct proc_info_list *list = lookup_processor_type(midr);
684 pr_err("CPU%u: configuration botched (ID %08x), CPU halted\n",
685 smp_processor_id(), midr);
687 /* can't use cpu_relax() here as it may require MMU setup */;
693 static void __init setup_processor(void)
695 unsigned int midr = read_cpuid_id();
696 struct proc_info_list *list = lookup_processor(midr);
698 cpu_name = list->cpu_name;
699 __cpu_architecture = __get_cpu_architecture();
701 init_proc_vtable(list->proc);
703 cpu_tlb = *list->tlb;
706 cpu_user = *list->user;
709 cpu_cache = *list->cache;
712 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
713 list->cpu_name, midr, midr & 15,
714 proc_arch[cpu_architecture()], get_cr());
716 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
717 list->arch_name, ENDIANNESS);
718 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
719 list->elf_name, ENDIANNESS);
720 elf_hwcap = list->elf_hwcap;
725 #ifndef CONFIG_ARM_THUMB
726 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
729 init_default_cache_policy(list->__cpu_mm_mmu_flags);
731 erratum_a15_798181_init();
739 void __init dump_machine_table(void)
741 const struct machine_desc *p;
743 early_print("Available machine support:\n\nID (hex)\tNAME\n");
744 for_each_machine_desc(p)
745 early_print("%08x\t%s\n", p->nr, p->name);
747 early_print("\nPlease check your kernel config and/or bootloader.\n");
750 /* can't use cpu_relax() here as it may require MMU setup */;
753 int __init arm_add_memory(u64 start, u64 size)
758 * Ensure that start/size are aligned to a page boundary.
759 * Size is rounded down, start is rounded up.
761 aligned_start = PAGE_ALIGN(start);
762 if (aligned_start > start + size)
765 size -= aligned_start - start;
767 #ifndef CONFIG_PHYS_ADDR_T_64BIT
768 if (aligned_start > ULONG_MAX) {
769 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
774 if (aligned_start + size > ULONG_MAX) {
775 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
778 * To ensure bank->start + bank->size is representable in
779 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
780 * This means we lose a page after masking.
782 size = ULONG_MAX - aligned_start;
786 if (aligned_start < PHYS_OFFSET) {
787 if (aligned_start + size <= PHYS_OFFSET) {
788 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
789 aligned_start, aligned_start + size);
793 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
794 aligned_start, (u64)PHYS_OFFSET);
796 size -= PHYS_OFFSET - aligned_start;
797 aligned_start = PHYS_OFFSET;
800 start = aligned_start;
801 size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
804 * Check whether this memory region has non-zero size or
805 * invalid node number.
810 memblock_add(start, size);
815 * Pick out the memory size. We look for mem=size@start,
816 * where start and size are "size[KkMm]"
819 static int __init early_mem(char *p)
821 static int usermem __initdata = 0;
827 * If the user specifies memory size, we
828 * blow away any automatically generated
833 memblock_remove(memblock_start_of_DRAM(),
834 memblock_end_of_DRAM() - memblock_start_of_DRAM());
838 size = memparse(p, &endp);
840 start = memparse(endp + 1, NULL);
842 arm_add_memory(start, size);
846 early_param("mem", early_mem);
848 static void __init request_standard_resources(const struct machine_desc *mdesc)
850 phys_addr_t start, end, res_end;
851 struct resource *res;
854 kernel_code.start = virt_to_phys(_text);
855 kernel_code.end = virt_to_phys(__init_begin - 1);
856 kernel_data.start = virt_to_phys(_sdata);
857 kernel_data.end = virt_to_phys(_end - 1);
859 for_each_mem_range(i, &start, &end) {
860 unsigned long boot_alias_start;
863 * In memblock, end points to the first byte after the
864 * range while in resourses, end points to the last byte in
870 * Some systems have a special memory alias which is only
871 * used for booting. We need to advertise this region to
872 * kexec-tools so they know where bootable RAM is located.
874 boot_alias_start = phys_to_idmap(start);
875 if (arm_has_idmap_alias() && boot_alias_start != IDMAP_INVALID_ADDR) {
876 res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
878 panic("%s: Failed to allocate %zu bytes\n",
879 __func__, sizeof(*res));
880 res->name = "System RAM (boot alias)";
881 res->start = boot_alias_start;
882 res->end = phys_to_idmap(res_end);
883 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
884 request_resource(&iomem_resource, res);
887 res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
889 panic("%s: Failed to allocate %zu bytes\n", __func__,
891 res->name = "System RAM";
894 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
896 request_resource(&iomem_resource, res);
898 if (kernel_code.start >= res->start &&
899 kernel_code.end <= res->end)
900 request_resource(res, &kernel_code);
901 if (kernel_data.start >= res->start &&
902 kernel_data.end <= res->end)
903 request_resource(res, &kernel_data);
906 if (mdesc->video_start) {
907 video_ram.start = mdesc->video_start;
908 video_ram.end = mdesc->video_end;
909 request_resource(&iomem_resource, &video_ram);
913 * Some machines don't have the possibility of ever
914 * possessing lp0, lp1 or lp2
916 if (mdesc->reserve_lp0)
917 request_resource(&ioport_resource, &lp0);
918 if (mdesc->reserve_lp1)
919 request_resource(&ioport_resource, &lp1);
920 if (mdesc->reserve_lp2)
921 request_resource(&ioport_resource, &lp2);
924 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) || \
926 struct screen_info screen_info = {
927 .orig_video_lines = 30,
928 .orig_video_cols = 80,
929 .orig_video_mode = 0,
930 .orig_video_ega_bx = 0,
931 .orig_video_isVGA = 1,
932 .orig_video_points = 8
936 static int __init customize_machine(void)
939 * customizes platform devices, or adds new ones
940 * On DT based machines, we fall back to populating the
941 * machine from the device tree, if no callback is provided,
942 * otherwise we would always need an init_machine callback.
944 if (machine_desc->init_machine)
945 machine_desc->init_machine();
949 arch_initcall(customize_machine);
951 static int __init init_machine_late(void)
953 struct device_node *root;
956 if (machine_desc->init_late)
957 machine_desc->init_late();
959 root = of_find_node_by_path("/");
961 ret = of_property_read_string(root, "serial-number",
964 system_serial = NULL;
968 system_serial = kasprintf(GFP_KERNEL, "%08x%08x",
974 late_initcall(init_machine_late);
978 * The crash region must be aligned to 128MB to avoid
979 * zImage relocating below the reserved region.
981 #define CRASH_ALIGN (128 << 20)
983 static inline unsigned long long get_total_mem(void)
987 total = max_low_pfn - min_low_pfn;
988 return total << PAGE_SHIFT;
992 * reserve_crashkernel() - reserves memory are for crash kernel
994 * This function reserves memory area given in "crashkernel=" kernel command
995 * line parameter. The memory reserved is used by a dump capture kernel when
996 * primary kernel is crashing.
998 static void __init reserve_crashkernel(void)
1000 unsigned long long crash_size, crash_base;
1001 unsigned long long total_mem;
1004 total_mem = get_total_mem();
1005 ret = parse_crashkernel(boot_command_line, total_mem,
1006 &crash_size, &crash_base);
1007 /* invalid value specified or crashkernel=0 */
1008 if (ret || !crash_size)
1011 if (crash_base <= 0) {
1012 unsigned long long crash_max = idmap_to_phys((u32)~0);
1013 unsigned long long lowmem_max = __pa(high_memory - 1) + 1;
1014 if (crash_max > lowmem_max)
1015 crash_max = lowmem_max;
1017 crash_base = memblock_phys_alloc_range(crash_size, CRASH_ALIGN,
1018 CRASH_ALIGN, crash_max);
1020 pr_err("crashkernel reservation failed - No suitable area found.\n");
1024 unsigned long long crash_max = crash_base + crash_size;
1025 unsigned long long start;
1027 start = memblock_phys_alloc_range(crash_size, SECTION_SIZE,
1028 crash_base, crash_max);
1030 pr_err("crashkernel reservation failed - memory is in use.\n");
1035 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
1036 (unsigned long)(crash_size >> 20),
1037 (unsigned long)(crash_base >> 20),
1038 (unsigned long)(total_mem >> 20));
1040 /* The crashk resource must always be located in normal mem */
1041 crashk_res.start = crash_base;
1042 crashk_res.end = crash_base + crash_size - 1;
1043 insert_resource(&iomem_resource, &crashk_res);
1045 if (arm_has_idmap_alias()) {
1047 * If we have a special RAM alias for use at boot, we
1048 * need to advertise to kexec tools where the alias is.
1050 static struct resource crashk_boot_res = {
1051 .name = "Crash kernel (boot alias)",
1052 .flags = IORESOURCE_BUSY | IORESOURCE_MEM,
1055 crashk_boot_res.start = phys_to_idmap(crash_base);
1056 crashk_boot_res.end = crashk_boot_res.start + crash_size - 1;
1057 insert_resource(&iomem_resource, &crashk_boot_res);
1061 static inline void reserve_crashkernel(void) {}
1062 #endif /* CONFIG_KEXEC */
1064 void __init hyp_mode_check(void)
1066 #ifdef CONFIG_ARM_VIRT_EXT
1069 if (is_hyp_mode_available()) {
1070 pr_info("CPU: All CPU(s) started in HYP mode.\n");
1071 pr_info("CPU: Virtualization extensions available.\n");
1072 } else if (is_hyp_mode_mismatched()) {
1073 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
1074 __boot_cpu_mode & MODE_MASK);
1075 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
1077 pr_info("CPU: All CPU(s) started in SVC mode.\n");
1081 static void (*__arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
1083 static int arm_restart(struct notifier_block *nb, unsigned long action,
1086 __arm_pm_restart(action, data);
1090 static struct notifier_block arm_restart_nb = {
1091 .notifier_call = arm_restart,
1095 void __init setup_arch(char **cmdline_p)
1097 const struct machine_desc *mdesc = NULL;
1098 void *atags_vaddr = NULL;
1100 if (__atags_pointer)
1101 atags_vaddr = FDT_VIRT_BASE(__atags_pointer);
1105 mdesc = setup_machine_fdt(atags_vaddr);
1107 memblock_reserve(__atags_pointer,
1108 fdt_totalsize(atags_vaddr));
1111 mdesc = setup_machine_tags(atags_vaddr, __machine_arch_type);
1113 early_print("\nError: invalid dtb and unrecognized/unsupported machine ID\n");
1114 early_print(" r1=0x%08x, r2=0x%08x\n", __machine_arch_type,
1116 if (__atags_pointer)
1117 early_print(" r2[]=%*ph\n", 16, atags_vaddr);
1118 dump_machine_table();
1121 machine_desc = mdesc;
1122 machine_name = mdesc->name;
1123 dump_stack_set_arch_desc("%s", mdesc->name);
1125 if (mdesc->reboot_mode != REBOOT_HARD)
1126 reboot_mode = mdesc->reboot_mode;
1128 setup_initial_init_mm(_text, _etext, _edata, _end);
1130 /* populate cmd_line too for later use, preserving boot_command_line */
1131 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
1132 *cmdline_p = cmd_line;
1134 early_fixmap_init();
1135 early_ioremap_init();
1137 parse_early_param();
1140 early_mm_init(mdesc);
1142 setup_dma_zone(mdesc);
1146 * Make sure the calculation for lowmem/highmem is set appropriately
1147 * before reserving/allocating any memory
1149 adjust_lowmem_bounds();
1150 arm_memblock_init(mdesc);
1151 /* Memory may have been removed so recalculate the bounds. */
1152 adjust_lowmem_bounds();
1154 early_ioremap_reset();
1158 request_standard_resources(mdesc);
1160 if (mdesc->restart) {
1161 __arm_pm_restart = mdesc->restart;
1162 register_restart_handler(&arm_restart_nb);
1165 unflatten_device_tree();
1167 arm_dt_init_cpu_maps();
1171 if (!mdesc->smp_init || !mdesc->smp_init()) {
1172 if (psci_smp_available())
1173 smp_set_ops(&psci_smp_ops);
1174 else if (mdesc->smp)
1175 smp_set_ops(mdesc->smp);
1178 smp_build_mpidr_hash();
1185 reserve_crashkernel();
1187 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1188 handle_arch_irq = mdesc->handle_irq;
1192 #if defined(CONFIG_VGA_CONSOLE)
1193 conswitchp = &vga_con;
1197 if (mdesc->init_early)
1198 mdesc->init_early();
1202 static int __init topology_init(void)
1206 for_each_possible_cpu(cpu) {
1207 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
1208 cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu);
1209 register_cpu(&cpuinfo->cpu, cpu);
1214 subsys_initcall(topology_init);
1216 #ifdef CONFIG_HAVE_PROC_CPU
1217 static int __init proc_cpu_init(void)
1219 struct proc_dir_entry *res;
1221 res = proc_mkdir("cpu", NULL);
1226 fs_initcall(proc_cpu_init);
1229 static const char *hwcap_str[] = {
1255 static const char *hwcap2_str[] = {
1264 static int c_show(struct seq_file *m, void *v)
1269 for_each_online_cpu(i) {
1271 * glibc reads /proc/cpuinfo to determine the number of
1272 * online processors, looking for lines beginning with
1273 * "processor". Give glibc what it expects.
1275 seq_printf(m, "processor\t: %d\n", i);
1276 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1277 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1278 cpu_name, cpuid & 15, elf_platform);
1280 #if defined(CONFIG_SMP)
1281 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1282 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1283 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1285 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1286 loops_per_jiffy / (500000/HZ),
1287 (loops_per_jiffy / (5000/HZ)) % 100);
1289 /* dump out the processor features */
1290 seq_puts(m, "Features\t: ");
1292 for (j = 0; hwcap_str[j]; j++)
1293 if (elf_hwcap & (1 << j))
1294 seq_printf(m, "%s ", hwcap_str[j]);
1296 for (j = 0; hwcap2_str[j]; j++)
1297 if (elf_hwcap2 & (1 << j))
1298 seq_printf(m, "%s ", hwcap2_str[j]);
1300 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1301 seq_printf(m, "CPU architecture: %s\n",
1302 proc_arch[cpu_architecture()]);
1304 if ((cpuid & 0x0008f000) == 0x00000000) {
1306 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1308 if ((cpuid & 0x0008f000) == 0x00007000) {
1310 seq_printf(m, "CPU variant\t: 0x%02x\n",
1311 (cpuid >> 16) & 127);
1314 seq_printf(m, "CPU variant\t: 0x%x\n",
1315 (cpuid >> 20) & 15);
1317 seq_printf(m, "CPU part\t: 0x%03x\n",
1318 (cpuid >> 4) & 0xfff);
1320 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1323 seq_printf(m, "Hardware\t: %s\n", machine_name);
1324 seq_printf(m, "Revision\t: %04x\n", system_rev);
1325 seq_printf(m, "Serial\t\t: %s\n", system_serial);
1330 static void *c_start(struct seq_file *m, loff_t *pos)
1332 return *pos < 1 ? (void *)1 : NULL;
1335 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1341 static void c_stop(struct seq_file *m, void *v)
1345 const struct seq_operations cpuinfo_op = {