2 * linux/arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/export.h>
11 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/ioport.h>
14 #include <linux/delay.h>
15 #include <linux/utsname.h>
16 #include <linux/initrd.h>
17 #include <linux/console.h>
18 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/screen_info.h>
21 #include <linux/of_iommu.h>
22 #include <linux/of_platform.h>
23 #include <linux/init.h>
24 #include <linux/kexec.h>
25 #include <linux/of_fdt.h>
26 #include <linux/cpu.h>
27 #include <linux/interrupt.h>
28 #include <linux/smp.h>
29 #include <linux/proc_fs.h>
30 #include <linux/memblock.h>
31 #include <linux/bug.h>
32 #include <linux/compiler.h>
33 #include <linux/sort.h>
34 #include <linux/psci.h>
36 #include <asm/unified.h>
39 #include <asm/cputype.h>
41 #include <asm/fixmap.h>
42 #include <asm/procinfo.h>
44 #include <asm/sections.h>
45 #include <asm/setup.h>
46 #include <asm/smp_plat.h>
47 #include <asm/mach-types.h>
48 #include <asm/cacheflush.h>
49 #include <asm/cachetype.h>
50 #include <asm/tlbflush.h>
51 #include <asm/xen/hypervisor.h>
54 #include <asm/mach/arch.h>
55 #include <asm/mach/irq.h>
56 #include <asm/mach/time.h>
57 #include <asm/system_info.h>
58 #include <asm/system_misc.h>
59 #include <asm/traps.h>
60 #include <asm/unwind.h>
61 #include <asm/memblock.h>
67 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
70 static int __init fpe_setup(char *line)
72 memcpy(fpe_type, line, 8);
76 __setup("fpe=", fpe_setup);
79 extern void init_default_cache_policy(unsigned long);
80 extern void paging_init(const struct machine_desc *desc);
81 extern void early_paging_init(const struct machine_desc *);
82 extern void sanity_check_meminfo(void);
83 extern enum reboot_mode reboot_mode;
84 extern void setup_dma_zone(const struct machine_desc *desc);
86 unsigned int processor_id;
87 EXPORT_SYMBOL(processor_id);
88 unsigned int __machine_arch_type __read_mostly;
89 EXPORT_SYMBOL(__machine_arch_type);
90 unsigned int cacheid __read_mostly;
91 EXPORT_SYMBOL(cacheid);
93 unsigned int __atags_pointer __initdata;
95 unsigned int system_rev;
96 EXPORT_SYMBOL(system_rev);
98 const char *system_serial;
99 EXPORT_SYMBOL(system_serial);
101 unsigned int system_serial_low;
102 EXPORT_SYMBOL(system_serial_low);
104 unsigned int system_serial_high;
105 EXPORT_SYMBOL(system_serial_high);
107 unsigned int elf_hwcap __read_mostly;
108 EXPORT_SYMBOL(elf_hwcap);
110 unsigned int elf_hwcap2 __read_mostly;
111 EXPORT_SYMBOL(elf_hwcap2);
115 struct processor processor __read_mostly;
116 #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
117 struct processor *cpu_vtable[NR_CPUS] = {
123 struct cpu_tlb_fns cpu_tlb __read_mostly;
126 struct cpu_user_fns cpu_user __read_mostly;
129 struct cpu_cache_fns cpu_cache __read_mostly;
131 #ifdef CONFIG_OUTER_CACHE
132 struct outer_cache_fns outer_cache __read_mostly;
133 EXPORT_SYMBOL(outer_cache);
137 * Cached cpu_architecture() result for use by assembler code.
138 * C code should use the cpu_architecture() function instead of accessing this
141 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
148 } ____cacheline_aligned;
150 #ifndef CONFIG_CPU_V7M
151 static struct stack stacks[NR_CPUS];
154 char elf_platform[ELF_PLATFORM_SIZE];
155 EXPORT_SYMBOL(elf_platform);
157 static const char *cpu_name;
158 static const char *machine_name;
159 static char __initdata cmd_line[COMMAND_LINE_SIZE];
160 const struct machine_desc *machine_desc __initdata;
162 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
163 #define ENDIANNESS ((char)endian_test.l)
165 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
168 * Standard memory resources
170 static struct resource mem_res[] = {
175 .flags = IORESOURCE_MEM
178 .name = "Kernel code",
181 .flags = IORESOURCE_MEM
184 .name = "Kernel data",
187 .flags = IORESOURCE_MEM
191 #define video_ram mem_res[0]
192 #define kernel_code mem_res[1]
193 #define kernel_data mem_res[2]
195 static struct resource io_res[] = {
200 .flags = IORESOURCE_IO | IORESOURCE_BUSY
206 .flags = IORESOURCE_IO | IORESOURCE_BUSY
212 .flags = IORESOURCE_IO | IORESOURCE_BUSY
216 #define lp0 io_res[0]
217 #define lp1 io_res[1]
218 #define lp2 io_res[2]
220 static const char *proc_arch[] = {
240 #ifdef CONFIG_CPU_V7M
241 static int __get_cpu_architecture(void)
243 return CPU_ARCH_ARMv7M;
246 static int __get_cpu_architecture(void)
250 if ((read_cpuid_id() & 0x0008f000) == 0) {
251 cpu_arch = CPU_ARCH_UNKNOWN;
252 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
253 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
254 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
255 cpu_arch = (read_cpuid_id() >> 16) & 7;
257 cpu_arch += CPU_ARCH_ARMv3;
258 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
259 /* Revised CPUID format. Read the Memory Model Feature
260 * Register 0 and check for VMSAv7 or PMSAv7 */
261 unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
262 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
263 (mmfr0 & 0x000000f0) >= 0x00000030)
264 cpu_arch = CPU_ARCH_ARMv7;
265 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
266 (mmfr0 & 0x000000f0) == 0x00000020)
267 cpu_arch = CPU_ARCH_ARMv6;
269 cpu_arch = CPU_ARCH_UNKNOWN;
271 cpu_arch = CPU_ARCH_UNKNOWN;
277 int __pure cpu_architecture(void)
279 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
281 return __cpu_architecture;
284 static int cpu_has_aliasing_icache(unsigned int arch)
287 unsigned int id_reg, num_sets, line_size;
289 /* PIPT caches never alias. */
290 if (icache_is_pipt())
293 /* arch specifies the register format */
296 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
297 : /* No output operands */
300 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
302 line_size = 4 << ((id_reg & 0x7) + 2);
303 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
304 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
307 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
310 /* I-cache aliases will be handled by D-cache aliasing code */
314 return aliasing_icache;
317 static void __init cacheid_init(void)
319 unsigned int arch = cpu_architecture();
321 if (arch == CPU_ARCH_ARMv7M) {
323 } else if (arch >= CPU_ARCH_ARMv6) {
324 unsigned int cachetype = read_cpuid_cachetype();
325 if ((cachetype & (7 << 29)) == 4 << 29) {
326 /* ARMv7 register format */
327 arch = CPU_ARCH_ARMv7;
328 cacheid = CACHEID_VIPT_NONALIASING;
329 switch (cachetype & (3 << 14)) {
331 cacheid |= CACHEID_ASID_TAGGED;
334 cacheid |= CACHEID_PIPT;
338 arch = CPU_ARCH_ARMv6;
339 if (cachetype & (1 << 23))
340 cacheid = CACHEID_VIPT_ALIASING;
342 cacheid = CACHEID_VIPT_NONALIASING;
344 if (cpu_has_aliasing_icache(arch))
345 cacheid |= CACHEID_VIPT_I_ALIASING;
347 cacheid = CACHEID_VIVT;
350 pr_info("CPU: %s data cache, %s instruction cache\n",
351 cache_is_vivt() ? "VIVT" :
352 cache_is_vipt_aliasing() ? "VIPT aliasing" :
353 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
354 cache_is_vivt() ? "VIVT" :
355 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
356 icache_is_vipt_aliasing() ? "VIPT aliasing" :
357 icache_is_pipt() ? "PIPT" :
358 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
362 * These functions re-use the assembly code in head.S, which
363 * already provide the required functionality.
365 extern struct proc_info_list *lookup_processor_type(unsigned int);
367 void __init early_print(const char *str, ...)
369 extern void printascii(const char *);
374 vsnprintf(buf, sizeof(buf), str, ap);
377 #ifdef CONFIG_DEBUG_LL
383 static void __init cpuid_init_hwcaps(void)
388 if (cpu_architecture() < CPU_ARCH_ARMv7)
391 block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
393 elf_hwcap |= HWCAP_IDIVA;
395 elf_hwcap |= HWCAP_IDIVT;
397 /* LPAE implies atomic ldrd/strd instructions */
398 block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
400 elf_hwcap |= HWCAP_LPAE;
402 /* check for supported v8 Crypto instructions */
403 isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
405 block = cpuid_feature_extract_field(isar5, 4);
407 elf_hwcap2 |= HWCAP2_PMULL;
409 elf_hwcap2 |= HWCAP2_AES;
411 block = cpuid_feature_extract_field(isar5, 8);
413 elf_hwcap2 |= HWCAP2_SHA1;
415 block = cpuid_feature_extract_field(isar5, 12);
417 elf_hwcap2 |= HWCAP2_SHA2;
419 block = cpuid_feature_extract_field(isar5, 16);
421 elf_hwcap2 |= HWCAP2_CRC32;
424 static void __init elf_hwcap_fixup(void)
426 unsigned id = read_cpuid_id();
429 * HWCAP_TLS is available only on 1136 r1p0 and later,
430 * see also kuser_get_tls_init.
432 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
433 ((id >> 20) & 3) == 0) {
434 elf_hwcap &= ~HWCAP_TLS;
438 /* Verify if CPUID scheme is implemented */
439 if ((id & 0x000f0000) != 0x000f0000)
443 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
444 * avoid advertising SWP; it may not be atomic with
445 * multiprocessing cores.
447 if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
448 (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
449 cpuid_feature_extract(CPUID_EXT_ISAR3, 20) >= 3))
450 elf_hwcap &= ~HWCAP_SWP;
454 * cpu_init - initialise one CPU.
456 * cpu_init sets up the per-CPU stacks.
458 void notrace cpu_init(void)
460 #ifndef CONFIG_CPU_V7M
461 unsigned int cpu = smp_processor_id();
462 struct stack *stk = &stacks[cpu];
464 if (cpu >= NR_CPUS) {
465 pr_crit("CPU%u: bad primary CPU number\n", cpu);
470 * This only works on resume and secondary cores. For booting on the
471 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
473 set_my_cpu_offset(per_cpu_offset(cpu));
478 * Define the placement constraint for the inline asm directive below.
479 * In Thumb-2, msr with an immediate value is not allowed.
481 #ifdef CONFIG_THUMB2_KERNEL
490 * setup stacks for re-entrant exception handlers
494 "add r14, %0, %2\n\t"
497 "add r14, %0, %4\n\t"
500 "add r14, %0, %6\n\t"
503 "add r14, %0, %8\n\t"
508 PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
509 "I" (offsetof(struct stack, irq[0])),
510 PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
511 "I" (offsetof(struct stack, abt[0])),
512 PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE),
513 "I" (offsetof(struct stack, und[0])),
514 PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
515 "I" (offsetof(struct stack, fiq[0])),
516 PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
521 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
523 void __init smp_setup_processor_id(void)
526 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
527 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
529 cpu_logical_map(0) = cpu;
530 for (i = 1; i < nr_cpu_ids; ++i)
531 cpu_logical_map(i) = i == cpu ? 0 : i;
534 * clear __my_cpu_offset on boot CPU to avoid hang caused by
535 * using percpu variable early, for example, lockdep will
536 * access percpu variable inside lock_release
538 set_my_cpu_offset(0);
540 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
543 struct mpidr_hash mpidr_hash;
546 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
547 * level in order to build a linear index from an
548 * MPIDR value. Resulting algorithm is a collision
549 * free hash carried out through shifting and ORing
551 static void __init smp_build_mpidr_hash(void)
554 u32 fs[3], bits[3], ls, mask = 0;
556 * Pre-scan the list of MPIDRS and filter out bits that do
557 * not contribute to affinity levels, ie they never toggle.
559 for_each_possible_cpu(i)
560 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
561 pr_debug("mask of set bits 0x%x\n", mask);
563 * Find and stash the last and first bit set at all affinity levels to
564 * check how many bits are required to represent them.
566 for (i = 0; i < 3; i++) {
567 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
569 * Find the MSB bit and LSB bits position
570 * to determine how many bits are required
571 * to express the affinity level.
574 fs[i] = affinity ? ffs(affinity) - 1 : 0;
575 bits[i] = ls - fs[i];
578 * An index can be created from the MPIDR by isolating the
579 * significant bits at each affinity level and by shifting
580 * them in order to compress the 24 bits values space to a
581 * compressed set of values. This is equivalent to hashing
582 * the MPIDR through shifting and ORing. It is a collision free
583 * hash though not minimal since some levels might contain a number
584 * of CPUs that is not an exact power of 2 and their bit
585 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
587 mpidr_hash.shift_aff[0] = fs[0];
588 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
589 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
591 mpidr_hash.mask = mask;
592 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
593 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
594 mpidr_hash.shift_aff[0],
595 mpidr_hash.shift_aff[1],
596 mpidr_hash.shift_aff[2],
600 * 4x is an arbitrary value used to warn on a hash table much bigger
601 * than expected on most systems.
603 if (mpidr_hash_size() > 4 * num_possible_cpus())
604 pr_warn("Large number of MPIDR hash buckets detected\n");
605 sync_cache_w(&mpidr_hash);
610 * locate processor in the list of supported processor types. The linker
611 * builds this table for us from the entries in arch/arm/mm/proc-*.S
613 struct proc_info_list *lookup_processor(u32 midr)
615 struct proc_info_list *list = lookup_processor_type(midr);
618 pr_err("CPU%u: configuration botched (ID %08x), CPU halted\n",
619 smp_processor_id(), midr);
621 /* can't use cpu_relax() here as it may require MMU setup */;
627 static void __init setup_processor(void)
629 unsigned int midr = read_cpuid_id();
630 struct proc_info_list *list = lookup_processor(midr);
632 cpu_name = list->cpu_name;
633 __cpu_architecture = __get_cpu_architecture();
635 init_proc_vtable(list->proc);
637 cpu_tlb = *list->tlb;
640 cpu_user = *list->user;
643 cpu_cache = *list->cache;
646 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
647 list->cpu_name, midr, midr & 15,
648 proc_arch[cpu_architecture()], get_cr());
650 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
651 list->arch_name, ENDIANNESS);
652 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
653 list->elf_name, ENDIANNESS);
654 elf_hwcap = list->elf_hwcap;
658 #ifndef CONFIG_ARM_THUMB
659 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
662 init_default_cache_policy(list->__cpu_mm_mmu_flags);
664 erratum_a15_798181_init();
672 void __init dump_machine_table(void)
674 const struct machine_desc *p;
676 early_print("Available machine support:\n\nID (hex)\tNAME\n");
677 for_each_machine_desc(p)
678 early_print("%08x\t%s\n", p->nr, p->name);
680 early_print("\nPlease check your kernel config and/or bootloader.\n");
683 /* can't use cpu_relax() here as it may require MMU setup */;
686 int __init arm_add_memory(u64 start, u64 size)
691 * Ensure that start/size are aligned to a page boundary.
692 * Size is rounded down, start is rounded up.
694 aligned_start = PAGE_ALIGN(start);
695 if (aligned_start > start + size)
698 size -= aligned_start - start;
700 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
701 if (aligned_start > ULONG_MAX) {
702 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
707 if (aligned_start + size > ULONG_MAX) {
708 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
711 * To ensure bank->start + bank->size is representable in
712 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
713 * This means we lose a page after masking.
715 size = ULONG_MAX - aligned_start;
719 if (aligned_start < PHYS_OFFSET) {
720 if (aligned_start + size <= PHYS_OFFSET) {
721 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
722 aligned_start, aligned_start + size);
726 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
727 aligned_start, (u64)PHYS_OFFSET);
729 size -= PHYS_OFFSET - aligned_start;
730 aligned_start = PHYS_OFFSET;
733 start = aligned_start;
734 size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
737 * Check whether this memory region has non-zero size or
738 * invalid node number.
743 memblock_add(start, size);
748 * Pick out the memory size. We look for mem=size@start,
749 * where start and size are "size[KkMm]"
752 static int __init early_mem(char *p)
754 static int usermem __initdata = 0;
760 * If the user specifies memory size, we
761 * blow away any automatically generated
766 memblock_remove(memblock_start_of_DRAM(),
767 memblock_end_of_DRAM() - memblock_start_of_DRAM());
771 size = memparse(p, &endp);
773 start = memparse(endp + 1, NULL);
775 arm_add_memory(start, size);
779 early_param("mem", early_mem);
781 static void __init request_standard_resources(const struct machine_desc *mdesc)
783 struct memblock_region *region;
784 struct resource *res;
786 kernel_code.start = virt_to_phys(_text);
787 kernel_code.end = virt_to_phys(_etext - 1);
788 kernel_data.start = virt_to_phys(_sdata);
789 kernel_data.end = virt_to_phys(_end - 1);
791 for_each_memblock(memory, region) {
792 res = memblock_virt_alloc(sizeof(*res), 0);
793 res->name = "System RAM";
794 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
795 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
796 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
798 request_resource(&iomem_resource, res);
800 if (kernel_code.start >= res->start &&
801 kernel_code.end <= res->end)
802 request_resource(res, &kernel_code);
803 if (kernel_data.start >= res->start &&
804 kernel_data.end <= res->end)
805 request_resource(res, &kernel_data);
808 if (mdesc->video_start) {
809 video_ram.start = mdesc->video_start;
810 video_ram.end = mdesc->video_end;
811 request_resource(&iomem_resource, &video_ram);
815 * Some machines don't have the possibility of ever
816 * possessing lp0, lp1 or lp2
818 if (mdesc->reserve_lp0)
819 request_resource(&ioport_resource, &lp0);
820 if (mdesc->reserve_lp1)
821 request_resource(&ioport_resource, &lp1);
822 if (mdesc->reserve_lp2)
823 request_resource(&ioport_resource, &lp2);
826 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
827 struct screen_info screen_info = {
828 .orig_video_lines = 30,
829 .orig_video_cols = 80,
830 .orig_video_mode = 0,
831 .orig_video_ega_bx = 0,
832 .orig_video_isVGA = 1,
833 .orig_video_points = 8
837 static int __init customize_machine(void)
840 * customizes platform devices, or adds new ones
841 * On DT based machines, we fall back to populating the
842 * machine from the device tree, if no callback is provided,
843 * otherwise we would always need an init_machine callback.
846 if (machine_desc->init_machine)
847 machine_desc->init_machine();
850 of_platform_populate(NULL, of_default_bus_match_table,
855 arch_initcall(customize_machine);
857 static int __init init_machine_late(void)
859 struct device_node *root;
862 if (machine_desc->init_late)
863 machine_desc->init_late();
865 root = of_find_node_by_path("/");
867 ret = of_property_read_string(root, "serial-number",
870 system_serial = NULL;
874 system_serial = kasprintf(GFP_KERNEL, "%08x%08x",
880 late_initcall(init_machine_late);
883 static inline unsigned long long get_total_mem(void)
887 total = max_low_pfn - min_low_pfn;
888 return total << PAGE_SHIFT;
892 * reserve_crashkernel() - reserves memory are for crash kernel
894 * This function reserves memory area given in "crashkernel=" kernel command
895 * line parameter. The memory reserved is used by a dump capture kernel when
896 * primary kernel is crashing.
898 static void __init reserve_crashkernel(void)
900 unsigned long long crash_size, crash_base;
901 unsigned long long total_mem;
904 total_mem = get_total_mem();
905 ret = parse_crashkernel(boot_command_line, total_mem,
906 &crash_size, &crash_base);
910 ret = memblock_reserve(crash_base, crash_size);
912 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
913 (unsigned long)crash_base);
917 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
918 (unsigned long)(crash_size >> 20),
919 (unsigned long)(crash_base >> 20),
920 (unsigned long)(total_mem >> 20));
922 crashk_res.start = crash_base;
923 crashk_res.end = crash_base + crash_size - 1;
924 insert_resource(&iomem_resource, &crashk_res);
927 static inline void reserve_crashkernel(void) {}
928 #endif /* CONFIG_KEXEC */
930 void __init hyp_mode_check(void)
932 #ifdef CONFIG_ARM_VIRT_EXT
935 if (is_hyp_mode_available()) {
936 pr_info("CPU: All CPU(s) started in HYP mode.\n");
937 pr_info("CPU: Virtualization extensions available.\n");
938 } else if (is_hyp_mode_mismatched()) {
939 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
940 __boot_cpu_mode & MODE_MASK);
941 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
943 pr_info("CPU: All CPU(s) started in SVC mode.\n");
947 void __init setup_arch(char **cmdline_p)
949 const struct machine_desc *mdesc;
952 mdesc = setup_machine_fdt(__atags_pointer);
954 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
955 machine_desc = mdesc;
956 machine_name = mdesc->name;
957 dump_stack_set_arch_desc("%s", mdesc->name);
959 if (mdesc->reboot_mode != REBOOT_HARD)
960 reboot_mode = mdesc->reboot_mode;
962 init_mm.start_code = (unsigned long) _text;
963 init_mm.end_code = (unsigned long) _etext;
964 init_mm.end_data = (unsigned long) _edata;
965 init_mm.brk = (unsigned long) _end;
967 /* populate cmd_line too for later use, preserving boot_command_line */
968 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
969 *cmdline_p = cmd_line;
971 if (IS_ENABLED(CONFIG_FIX_EARLYCON_MEM))
977 early_paging_init(mdesc);
979 setup_dma_zone(mdesc);
980 sanity_check_meminfo();
981 arm_memblock_init(mdesc);
984 request_standard_resources(mdesc);
987 arm_pm_restart = mdesc->restart;
989 unflatten_device_tree();
991 arm_dt_init_cpu_maps();
996 if (!mdesc->smp_init || !mdesc->smp_init()) {
997 if (psci_smp_available())
998 smp_set_ops(&psci_smp_ops);
1000 smp_set_ops(mdesc->smp);
1003 smp_build_mpidr_hash();
1010 reserve_crashkernel();
1012 #ifdef CONFIG_MULTI_IRQ_HANDLER
1013 handle_arch_irq = mdesc->handle_irq;
1017 #if defined(CONFIG_VGA_CONSOLE)
1018 conswitchp = &vga_con;
1019 #elif defined(CONFIG_DUMMY_CONSOLE)
1020 conswitchp = &dummy_con;
1024 if (mdesc->init_early)
1025 mdesc->init_early();
1029 static int __init topology_init(void)
1033 for_each_possible_cpu(cpu) {
1034 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
1035 cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu);
1036 register_cpu(&cpuinfo->cpu, cpu);
1041 subsys_initcall(topology_init);
1043 #ifdef CONFIG_HAVE_PROC_CPU
1044 static int __init proc_cpu_init(void)
1046 struct proc_dir_entry *res;
1048 res = proc_mkdir("cpu", NULL);
1053 fs_initcall(proc_cpu_init);
1056 static const char *hwcap_str[] = {
1082 static const char *hwcap2_str[] = {
1091 static int c_show(struct seq_file *m, void *v)
1096 for_each_online_cpu(i) {
1098 * glibc reads /proc/cpuinfo to determine the number of
1099 * online processors, looking for lines beginning with
1100 * "processor". Give glibc what it expects.
1102 seq_printf(m, "processor\t: %d\n", i);
1103 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1104 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1105 cpu_name, cpuid & 15, elf_platform);
1107 #if defined(CONFIG_SMP)
1108 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1109 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1110 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1112 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1113 loops_per_jiffy / (500000/HZ),
1114 (loops_per_jiffy / (5000/HZ)) % 100);
1116 /* dump out the processor features */
1117 seq_puts(m, "Features\t: ");
1119 for (j = 0; hwcap_str[j]; j++)
1120 if (elf_hwcap & (1 << j))
1121 seq_printf(m, "%s ", hwcap_str[j]);
1123 for (j = 0; hwcap2_str[j]; j++)
1124 if (elf_hwcap2 & (1 << j))
1125 seq_printf(m, "%s ", hwcap2_str[j]);
1127 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1128 seq_printf(m, "CPU architecture: %s\n",
1129 proc_arch[cpu_architecture()]);
1131 if ((cpuid & 0x0008f000) == 0x00000000) {
1133 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1135 if ((cpuid & 0x0008f000) == 0x00007000) {
1137 seq_printf(m, "CPU variant\t: 0x%02x\n",
1138 (cpuid >> 16) & 127);
1141 seq_printf(m, "CPU variant\t: 0x%x\n",
1142 (cpuid >> 20) & 15);
1144 seq_printf(m, "CPU part\t: 0x%03x\n",
1145 (cpuid >> 4) & 0xfff);
1147 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1150 seq_printf(m, "Hardware\t: %s\n", machine_name);
1151 seq_printf(m, "Revision\t: %04x\n", system_rev);
1152 seq_printf(m, "Serial\t\t: %s\n", system_serial);
1157 static void *c_start(struct seq_file *m, loff_t *pos)
1159 return *pos < 1 ? (void *)1 : NULL;
1162 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1168 static void c_stop(struct seq_file *m, void *v)
1172 const struct seq_operations cpuinfo_op = {