1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv5 [xscale] Performance counter handling code.
5 * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com>
7 * Based on the previous xscale OProfile code.
9 * There are two variants of the xscale PMU that we support:
10 * - xscale1pmu: 2 event counters and a cycle counter
11 * - xscale2pmu: 4 event counters and a cycle counter
12 * The two variants share event definitions, but have different
16 #ifdef CONFIG_CPU_XSCALE
18 #include <asm/cputype.h>
19 #include <asm/irq_regs.h>
22 #include <linux/perf/arm_pmu.h>
23 #include <linux/platform_device.h>
25 enum xscale_perf_types {
26 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
27 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
28 XSCALE_PERFCTR_DATA_STALL = 0x02,
29 XSCALE_PERFCTR_ITLB_MISS = 0x03,
30 XSCALE_PERFCTR_DTLB_MISS = 0x04,
31 XSCALE_PERFCTR_BRANCH = 0x05,
32 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
33 XSCALE_PERFCTR_INSTRUCTION = 0x07,
34 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
35 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
36 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
37 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
38 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
39 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
40 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
41 XSCALE_PERFCTR_BCU_FULL = 0x11,
42 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
43 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
44 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
45 XSCALE_PERFCTR_RMW = 0x16,
46 /* XSCALE_PERFCTR_CCNT is not hardware defined */
47 XSCALE_PERFCTR_CCNT = 0xFE,
48 XSCALE_PERFCTR_UNUSED = 0xFF,
51 enum xscale_counters {
52 XSCALE_CYCLE_COUNTER = 0,
59 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
60 PERF_MAP_ALL_UNSUPPORTED,
61 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
62 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
63 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
64 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
65 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
68 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
69 [PERF_COUNT_HW_CACHE_OP_MAX]
70 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
71 PERF_CACHE_MAP_ALL_UNSUPPORTED,
73 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
74 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
75 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
76 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
78 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
80 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
81 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
83 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
84 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
87 #define XSCALE_PMU_ENABLE 0x001
88 #define XSCALE_PMN_RESET 0x002
89 #define XSCALE_CCNT_RESET 0x004
90 #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
91 #define XSCALE_PMU_CNT64 0x008
93 #define XSCALE1_OVERFLOWED_MASK 0x700
94 #define XSCALE1_CCOUNT_OVERFLOW 0x400
95 #define XSCALE1_COUNT0_OVERFLOW 0x100
96 #define XSCALE1_COUNT1_OVERFLOW 0x200
97 #define XSCALE1_CCOUNT_INT_EN 0x040
98 #define XSCALE1_COUNT0_INT_EN 0x010
99 #define XSCALE1_COUNT1_INT_EN 0x020
100 #define XSCALE1_COUNT0_EVT_SHFT 12
101 #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
102 #define XSCALE1_COUNT1_EVT_SHFT 20
103 #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
106 xscale1pmu_read_pmnc(void)
109 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
114 xscale1pmu_write_pmnc(u32 val)
116 /* upper 4bits and 7, 11 are write-as-0 */
118 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
122 xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
123 enum xscale_counters counter)
128 case XSCALE_CYCLE_COUNTER:
129 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
131 case XSCALE_COUNTER0:
132 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
134 case XSCALE_COUNTER1:
135 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
138 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
145 xscale1pmu_handle_irq(int irq_num, void *dev)
148 struct perf_sample_data data;
149 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
150 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
151 struct pt_regs *regs;
155 * NOTE: there's an A stepping erratum that states if an overflow
156 * bit already exists and another occurs, the previous
157 * Overflow bit gets cleared. There's no workaround.
158 * Fixed in B stepping or later.
160 pmnc = xscale1pmu_read_pmnc();
163 * Write the value back to clear the overflow flags. Overflow
164 * flags remain in pmnc for use below. We also disable the PMU
165 * while we process the interrupt.
167 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
169 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
172 regs = get_irq_regs();
174 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
175 struct perf_event *event = cpuc->events[idx];
176 struct hw_perf_event *hwc;
181 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
185 armpmu_event_update(event);
186 perf_sample_data_init(&data, 0, hwc->last_period);
187 if (!armpmu_event_set_period(event))
190 if (perf_event_overflow(event, &data, regs))
191 cpu_pmu->disable(event);
199 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
200 xscale1pmu_write_pmnc(pmnc);
205 static void xscale1pmu_enable_event(struct perf_event *event)
207 unsigned long val, mask, evt, flags;
208 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
209 struct hw_perf_event *hwc = &event->hw;
210 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
214 case XSCALE_CYCLE_COUNTER:
216 evt = XSCALE1_CCOUNT_INT_EN;
218 case XSCALE_COUNTER0:
219 mask = XSCALE1_COUNT0_EVT_MASK;
220 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
221 XSCALE1_COUNT0_INT_EN;
223 case XSCALE_COUNTER1:
224 mask = XSCALE1_COUNT1_EVT_MASK;
225 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
226 XSCALE1_COUNT1_INT_EN;
229 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
233 raw_spin_lock_irqsave(&events->pmu_lock, flags);
234 val = xscale1pmu_read_pmnc();
237 xscale1pmu_write_pmnc(val);
238 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
241 static void xscale1pmu_disable_event(struct perf_event *event)
243 unsigned long val, mask, evt, flags;
244 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
245 struct hw_perf_event *hwc = &event->hw;
246 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
250 case XSCALE_CYCLE_COUNTER:
251 mask = XSCALE1_CCOUNT_INT_EN;
254 case XSCALE_COUNTER0:
255 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
256 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
258 case XSCALE_COUNTER1:
259 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
260 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
263 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
267 raw_spin_lock_irqsave(&events->pmu_lock, flags);
268 val = xscale1pmu_read_pmnc();
271 xscale1pmu_write_pmnc(val);
272 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
276 xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
277 struct perf_event *event)
279 struct hw_perf_event *hwc = &event->hw;
280 if (XSCALE_PERFCTR_CCNT == hwc->config_base) {
281 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
284 return XSCALE_CYCLE_COUNTER;
286 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask))
287 return XSCALE_COUNTER1;
289 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask))
290 return XSCALE_COUNTER0;
296 static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
298 unsigned long flags, val;
299 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
301 raw_spin_lock_irqsave(&events->pmu_lock, flags);
302 val = xscale1pmu_read_pmnc();
303 val |= XSCALE_PMU_ENABLE;
304 xscale1pmu_write_pmnc(val);
305 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
308 static void xscale1pmu_stop(struct arm_pmu *cpu_pmu)
310 unsigned long flags, val;
311 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
313 raw_spin_lock_irqsave(&events->pmu_lock, flags);
314 val = xscale1pmu_read_pmnc();
315 val &= ~XSCALE_PMU_ENABLE;
316 xscale1pmu_write_pmnc(val);
317 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
320 static inline u32 xscale1pmu_read_counter(struct perf_event *event)
322 struct hw_perf_event *hwc = &event->hw;
323 int counter = hwc->idx;
327 case XSCALE_CYCLE_COUNTER:
328 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
330 case XSCALE_COUNTER0:
331 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
333 case XSCALE_COUNTER1:
334 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
341 static inline void xscale1pmu_write_counter(struct perf_event *event, u32 val)
343 struct hw_perf_event *hwc = &event->hw;
344 int counter = hwc->idx;
347 case XSCALE_CYCLE_COUNTER:
348 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
350 case XSCALE_COUNTER0:
351 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
353 case XSCALE_COUNTER1:
354 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
359 static int xscale_map_event(struct perf_event *event)
361 return armpmu_map_event(event, &xscale_perf_map,
362 &xscale_perf_cache_map, 0xFF);
365 static int xscale1pmu_init(struct arm_pmu *cpu_pmu)
367 cpu_pmu->name = "armv5_xscale1";
368 cpu_pmu->handle_irq = xscale1pmu_handle_irq;
369 cpu_pmu->enable = xscale1pmu_enable_event;
370 cpu_pmu->disable = xscale1pmu_disable_event;
371 cpu_pmu->read_counter = xscale1pmu_read_counter;
372 cpu_pmu->write_counter = xscale1pmu_write_counter;
373 cpu_pmu->get_event_idx = xscale1pmu_get_event_idx;
374 cpu_pmu->start = xscale1pmu_start;
375 cpu_pmu->stop = xscale1pmu_stop;
376 cpu_pmu->map_event = xscale_map_event;
377 cpu_pmu->num_events = 3;
378 cpu_pmu->max_period = (1LLU << 32) - 1;
383 #define XSCALE2_OVERFLOWED_MASK 0x01f
384 #define XSCALE2_CCOUNT_OVERFLOW 0x001
385 #define XSCALE2_COUNT0_OVERFLOW 0x002
386 #define XSCALE2_COUNT1_OVERFLOW 0x004
387 #define XSCALE2_COUNT2_OVERFLOW 0x008
388 #define XSCALE2_COUNT3_OVERFLOW 0x010
389 #define XSCALE2_CCOUNT_INT_EN 0x001
390 #define XSCALE2_COUNT0_INT_EN 0x002
391 #define XSCALE2_COUNT1_INT_EN 0x004
392 #define XSCALE2_COUNT2_INT_EN 0x008
393 #define XSCALE2_COUNT3_INT_EN 0x010
394 #define XSCALE2_COUNT0_EVT_SHFT 0
395 #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
396 #define XSCALE2_COUNT1_EVT_SHFT 8
397 #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
398 #define XSCALE2_COUNT2_EVT_SHFT 16
399 #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
400 #define XSCALE2_COUNT3_EVT_SHFT 24
401 #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
404 xscale2pmu_read_pmnc(void)
407 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
408 /* bits 1-2 and 4-23 are read-unpredictable */
409 return val & 0xff000009;
413 xscale2pmu_write_pmnc(u32 val)
415 /* bits 4-23 are write-as-0, 24-31 are write ignored */
417 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
421 xscale2pmu_read_overflow_flags(void)
424 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
429 xscale2pmu_write_overflow_flags(u32 val)
431 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
435 xscale2pmu_read_event_select(void)
438 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
443 xscale2pmu_write_event_select(u32 val)
445 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
449 xscale2pmu_read_int_enable(void)
452 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
457 xscale2pmu_write_int_enable(u32 val)
459 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
463 xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
464 enum xscale_counters counter)
469 case XSCALE_CYCLE_COUNTER:
470 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
472 case XSCALE_COUNTER0:
473 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
475 case XSCALE_COUNTER1:
476 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
478 case XSCALE_COUNTER2:
479 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
481 case XSCALE_COUNTER3:
482 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
485 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
492 xscale2pmu_handle_irq(int irq_num, void *dev)
494 unsigned long pmnc, of_flags;
495 struct perf_sample_data data;
496 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
497 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
498 struct pt_regs *regs;
501 /* Disable the PMU. */
502 pmnc = xscale2pmu_read_pmnc();
503 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
505 /* Check the overflow flag register. */
506 of_flags = xscale2pmu_read_overflow_flags();
507 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
510 /* Clear the overflow bits. */
511 xscale2pmu_write_overflow_flags(of_flags);
513 regs = get_irq_regs();
515 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
516 struct perf_event *event = cpuc->events[idx];
517 struct hw_perf_event *hwc;
522 if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx))
526 armpmu_event_update(event);
527 perf_sample_data_init(&data, 0, hwc->last_period);
528 if (!armpmu_event_set_period(event))
531 if (perf_event_overflow(event, &data, regs))
532 cpu_pmu->disable(event);
540 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
541 xscale2pmu_write_pmnc(pmnc);
546 static void xscale2pmu_enable_event(struct perf_event *event)
548 unsigned long flags, ien, evtsel;
549 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
550 struct hw_perf_event *hwc = &event->hw;
551 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
554 ien = xscale2pmu_read_int_enable();
555 evtsel = xscale2pmu_read_event_select();
558 case XSCALE_CYCLE_COUNTER:
559 ien |= XSCALE2_CCOUNT_INT_EN;
561 case XSCALE_COUNTER0:
562 ien |= XSCALE2_COUNT0_INT_EN;
563 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
564 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
566 case XSCALE_COUNTER1:
567 ien |= XSCALE2_COUNT1_INT_EN;
568 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
569 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
571 case XSCALE_COUNTER2:
572 ien |= XSCALE2_COUNT2_INT_EN;
573 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
574 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
576 case XSCALE_COUNTER3:
577 ien |= XSCALE2_COUNT3_INT_EN;
578 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
579 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
582 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
586 raw_spin_lock_irqsave(&events->pmu_lock, flags);
587 xscale2pmu_write_event_select(evtsel);
588 xscale2pmu_write_int_enable(ien);
589 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
592 static void xscale2pmu_disable_event(struct perf_event *event)
594 unsigned long flags, ien, evtsel, of_flags;
595 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
596 struct hw_perf_event *hwc = &event->hw;
597 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
600 ien = xscale2pmu_read_int_enable();
601 evtsel = xscale2pmu_read_event_select();
604 case XSCALE_CYCLE_COUNTER:
605 ien &= ~XSCALE2_CCOUNT_INT_EN;
606 of_flags = XSCALE2_CCOUNT_OVERFLOW;
608 case XSCALE_COUNTER0:
609 ien &= ~XSCALE2_COUNT0_INT_EN;
610 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
611 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
612 of_flags = XSCALE2_COUNT0_OVERFLOW;
614 case XSCALE_COUNTER1:
615 ien &= ~XSCALE2_COUNT1_INT_EN;
616 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
617 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
618 of_flags = XSCALE2_COUNT1_OVERFLOW;
620 case XSCALE_COUNTER2:
621 ien &= ~XSCALE2_COUNT2_INT_EN;
622 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
623 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
624 of_flags = XSCALE2_COUNT2_OVERFLOW;
626 case XSCALE_COUNTER3:
627 ien &= ~XSCALE2_COUNT3_INT_EN;
628 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
629 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
630 of_flags = XSCALE2_COUNT3_OVERFLOW;
633 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
637 raw_spin_lock_irqsave(&events->pmu_lock, flags);
638 xscale2pmu_write_event_select(evtsel);
639 xscale2pmu_write_int_enable(ien);
640 xscale2pmu_write_overflow_flags(of_flags);
641 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
645 xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
646 struct perf_event *event)
648 int idx = xscale1pmu_get_event_idx(cpuc, event);
652 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
653 idx = XSCALE_COUNTER3;
654 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
655 idx = XSCALE_COUNTER2;
660 static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
662 unsigned long flags, val;
663 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
665 raw_spin_lock_irqsave(&events->pmu_lock, flags);
666 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
667 val |= XSCALE_PMU_ENABLE;
668 xscale2pmu_write_pmnc(val);
669 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
672 static void xscale2pmu_stop(struct arm_pmu *cpu_pmu)
674 unsigned long flags, val;
675 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
677 raw_spin_lock_irqsave(&events->pmu_lock, flags);
678 val = xscale2pmu_read_pmnc();
679 val &= ~XSCALE_PMU_ENABLE;
680 xscale2pmu_write_pmnc(val);
681 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
684 static inline u32 xscale2pmu_read_counter(struct perf_event *event)
686 struct hw_perf_event *hwc = &event->hw;
687 int counter = hwc->idx;
691 case XSCALE_CYCLE_COUNTER:
692 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
694 case XSCALE_COUNTER0:
695 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
697 case XSCALE_COUNTER1:
698 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
700 case XSCALE_COUNTER2:
701 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
703 case XSCALE_COUNTER3:
704 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
711 static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
713 struct hw_perf_event *hwc = &event->hw;
714 int counter = hwc->idx;
717 case XSCALE_CYCLE_COUNTER:
718 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
720 case XSCALE_COUNTER0:
721 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
723 case XSCALE_COUNTER1:
724 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
726 case XSCALE_COUNTER2:
727 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
729 case XSCALE_COUNTER3:
730 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
735 static int xscale2pmu_init(struct arm_pmu *cpu_pmu)
737 cpu_pmu->name = "armv5_xscale2";
738 cpu_pmu->handle_irq = xscale2pmu_handle_irq;
739 cpu_pmu->enable = xscale2pmu_enable_event;
740 cpu_pmu->disable = xscale2pmu_disable_event;
741 cpu_pmu->read_counter = xscale2pmu_read_counter;
742 cpu_pmu->write_counter = xscale2pmu_write_counter;
743 cpu_pmu->get_event_idx = xscale2pmu_get_event_idx;
744 cpu_pmu->start = xscale2pmu_start;
745 cpu_pmu->stop = xscale2pmu_stop;
746 cpu_pmu->map_event = xscale_map_event;
747 cpu_pmu->num_events = 5;
748 cpu_pmu->max_period = (1LLU << 32) - 1;
753 static const struct pmu_probe_info xscale_pmu_probe_table[] = {
754 XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V1, xscale1pmu_init),
755 XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V2, xscale2pmu_init),
756 { /* sentinel value */ }
759 static int xscale_pmu_device_probe(struct platform_device *pdev)
761 return arm_pmu_device_probe(pdev, NULL, xscale_pmu_probe_table);
764 static struct platform_driver xscale_pmu_driver = {
766 .name = "xscale-pmu",
768 .probe = xscale_pmu_device_probe,
771 builtin_platform_driver(xscale_pmu_driver);
772 #endif /* CONFIG_CPU_XSCALE */