1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009, 2010 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
10 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
11 * using the CPU's debug registers.
13 #define pr_fmt(fmt) "hw-breakpoint: " fmt
15 #include <linux/errno.h>
16 #include <linux/hardirq.h>
17 #include <linux/perf_event.h>
18 #include <linux/hw_breakpoint.h>
19 #include <linux/smp.h>
20 #include <linux/cpu_pm.h>
21 #include <linux/coresight.h>
23 #include <asm/cacheflush.h>
24 #include <asm/cputype.h>
25 #include <asm/current.h>
26 #include <asm/hw_breakpoint.h>
27 #include <asm/traps.h>
29 /* Breakpoint currently in use for each BRP. */
30 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
32 /* Watchpoint currently in use for each WRP. */
33 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
35 /* Number of BRP/WRP registers on this CPU. */
36 static int core_num_brps __ro_after_init;
37 static int core_num_wrps __ro_after_init;
39 /* Debug architecture version. */
40 static u8 debug_arch __ro_after_init;
42 /* Does debug architecture support OS Save and Restore? */
43 static bool has_ossr __ro_after_init;
45 /* Maximum supported watchpoint length. */
46 static u8 max_watchpoint_len __ro_after_init;
48 #define READ_WB_REG_CASE(OP2, M, VAL) \
49 case ((OP2 << 4) + M): \
50 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
53 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
54 case ((OP2 << 4) + M): \
55 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
58 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
59 READ_WB_REG_CASE(OP2, 0, VAL); \
60 READ_WB_REG_CASE(OP2, 1, VAL); \
61 READ_WB_REG_CASE(OP2, 2, VAL); \
62 READ_WB_REG_CASE(OP2, 3, VAL); \
63 READ_WB_REG_CASE(OP2, 4, VAL); \
64 READ_WB_REG_CASE(OP2, 5, VAL); \
65 READ_WB_REG_CASE(OP2, 6, VAL); \
66 READ_WB_REG_CASE(OP2, 7, VAL); \
67 READ_WB_REG_CASE(OP2, 8, VAL); \
68 READ_WB_REG_CASE(OP2, 9, VAL); \
69 READ_WB_REG_CASE(OP2, 10, VAL); \
70 READ_WB_REG_CASE(OP2, 11, VAL); \
71 READ_WB_REG_CASE(OP2, 12, VAL); \
72 READ_WB_REG_CASE(OP2, 13, VAL); \
73 READ_WB_REG_CASE(OP2, 14, VAL); \
74 READ_WB_REG_CASE(OP2, 15, VAL)
76 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
77 WRITE_WB_REG_CASE(OP2, 0, VAL); \
78 WRITE_WB_REG_CASE(OP2, 1, VAL); \
79 WRITE_WB_REG_CASE(OP2, 2, VAL); \
80 WRITE_WB_REG_CASE(OP2, 3, VAL); \
81 WRITE_WB_REG_CASE(OP2, 4, VAL); \
82 WRITE_WB_REG_CASE(OP2, 5, VAL); \
83 WRITE_WB_REG_CASE(OP2, 6, VAL); \
84 WRITE_WB_REG_CASE(OP2, 7, VAL); \
85 WRITE_WB_REG_CASE(OP2, 8, VAL); \
86 WRITE_WB_REG_CASE(OP2, 9, VAL); \
87 WRITE_WB_REG_CASE(OP2, 10, VAL); \
88 WRITE_WB_REG_CASE(OP2, 11, VAL); \
89 WRITE_WB_REG_CASE(OP2, 12, VAL); \
90 WRITE_WB_REG_CASE(OP2, 13, VAL); \
91 WRITE_WB_REG_CASE(OP2, 14, VAL); \
92 WRITE_WB_REG_CASE(OP2, 15, VAL)
94 static u32 read_wb_reg(int n)
99 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
100 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
101 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
102 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
104 pr_warn("attempt to read from unknown breakpoint register %d\n",
111 static void write_wb_reg(int n, u32 val)
114 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
115 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
116 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
117 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
119 pr_warn("attempt to write to unknown breakpoint register %d\n",
125 /* Determine debug architecture. */
126 static u8 get_debug_arch(void)
130 /* Do we implement the extended CPUID interface? */
131 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
132 pr_warn_once("CPUID feature registers not supported. "
133 "Assuming v6 debug is present.\n");
134 return ARM_DEBUG_ARCH_V6;
137 ARM_DBG_READ(c0, c0, 0, didr);
138 return (didr >> 16) & 0xf;
141 u8 arch_get_debug_arch(void)
146 static int debug_arch_supported(void)
148 u8 arch = get_debug_arch();
150 /* We don't support the memory-mapped interface. */
151 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
152 arch >= ARM_DEBUG_ARCH_V7_1;
155 /* Can we determine the watchpoint access type from the fsr? */
156 static int debug_exception_updates_fsr(void)
158 return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
161 /* Determine number of WRP registers available. */
162 static int get_num_wrp_resources(void)
165 ARM_DBG_READ(c0, c0, 0, didr);
166 return ((didr >> 28) & 0xf) + 1;
169 /* Determine number of BRP registers available. */
170 static int get_num_brp_resources(void)
173 ARM_DBG_READ(c0, c0, 0, didr);
174 return ((didr >> 24) & 0xf) + 1;
177 /* Does this core support mismatch breakpoints? */
178 static int core_has_mismatch_brps(void)
180 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
181 get_num_brp_resources() > 1);
184 /* Determine number of usable WRPs available. */
185 static int get_num_wrps(void)
188 * On debug architectures prior to 7.1, when a watchpoint fires, the
189 * only way to work out which watchpoint it was is by disassembling
190 * the faulting instruction and working out the address of the memory
193 * Furthermore, we can only do this if the watchpoint was precise
194 * since imprecise watchpoints prevent us from calculating register
197 * Providing we have more than 1 breakpoint register, we only report
198 * a single watchpoint register for the time being. This way, we always
199 * know which watchpoint fired. In the future we can either add a
200 * disassembler and address generation emulator, or we can insert a
201 * check to see if the DFAR is set on watchpoint exception entry
202 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
203 * that it is set on some implementations].
205 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
208 return get_num_wrp_resources();
211 /* Determine number of usable BRPs available. */
212 static int get_num_brps(void)
214 int brps = get_num_brp_resources();
215 return core_has_mismatch_brps() ? brps - 1 : brps;
219 * In order to access the breakpoint/watchpoint control registers,
220 * we must be running in debug monitor mode. Unfortunately, we can
221 * be put into halting debug mode at any time by an external debugger
222 * but there is nothing we can do to prevent that.
224 static int monitor_mode_enabled(void)
227 ARM_DBG_READ(c0, c1, 0, dscr);
228 return !!(dscr & ARM_DSCR_MDBGEN);
231 static int enable_monitor_mode(void)
234 ARM_DBG_READ(c0, c1, 0, dscr);
236 /* If monitor mode is already enabled, just return. */
237 if (dscr & ARM_DSCR_MDBGEN)
240 /* Write to the corresponding DSCR. */
241 switch (get_debug_arch()) {
242 case ARM_DEBUG_ARCH_V6:
243 case ARM_DEBUG_ARCH_V6_1:
244 ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
246 case ARM_DEBUG_ARCH_V7_ECP14:
247 case ARM_DEBUG_ARCH_V7_1:
248 case ARM_DEBUG_ARCH_V8:
249 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
256 /* Check that the write made it through. */
257 ARM_DBG_READ(c0, c1, 0, dscr);
258 if (!(dscr & ARM_DSCR_MDBGEN)) {
259 pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
268 int hw_breakpoint_slots(int type)
270 if (!debug_arch_supported())
274 * We can be called early, so don't rely on
275 * our static variables being initialised.
279 return get_num_brps();
281 return get_num_wrps();
283 pr_warn("unknown slot type: %d\n", type);
289 * Check if 8-bit byte-address select is available.
290 * This clobbers WRP 0.
292 static u8 get_max_wp_len(void)
295 struct arch_hw_breakpoint_ctrl ctrl;
298 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
301 memset(&ctrl, 0, sizeof(ctrl));
302 ctrl.len = ARM_BREAKPOINT_LEN_8;
303 ctrl_reg = encode_ctrl_reg(ctrl);
305 write_wb_reg(ARM_BASE_WVR, 0);
306 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
307 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
314 u8 arch_get_max_wp_len(void)
316 return max_watchpoint_len;
320 * Install a perf counter breakpoint.
322 int arch_install_hw_breakpoint(struct perf_event *bp)
324 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
325 struct perf_event **slot, **slots;
326 int i, max_slots, ctrl_base, val_base;
329 addr = info->address;
330 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
332 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
334 ctrl_base = ARM_BASE_BCR;
335 val_base = ARM_BASE_BVR;
336 slots = this_cpu_ptr(bp_on_reg);
337 max_slots = core_num_brps;
340 ctrl_base = ARM_BASE_WCR;
341 val_base = ARM_BASE_WVR;
342 slots = this_cpu_ptr(wp_on_reg);
343 max_slots = core_num_wrps;
346 for (i = 0; i < max_slots; ++i) {
355 if (i == max_slots) {
356 pr_warn("Can't find any breakpoint slot\n");
360 /* Override the breakpoint data with the step data. */
361 if (info->step_ctrl.enabled) {
362 addr = info->trigger & ~0x3;
363 ctrl = encode_ctrl_reg(info->step_ctrl);
364 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
366 ctrl_base = ARM_BASE_BCR + core_num_brps;
367 val_base = ARM_BASE_BVR + core_num_brps;
371 /* Setup the address register. */
372 write_wb_reg(val_base + i, addr);
374 /* Setup the control register. */
375 write_wb_reg(ctrl_base + i, ctrl);
379 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
381 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
382 struct perf_event **slot, **slots;
383 int i, max_slots, base;
385 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
388 slots = this_cpu_ptr(bp_on_reg);
389 max_slots = core_num_brps;
393 slots = this_cpu_ptr(wp_on_reg);
394 max_slots = core_num_wrps;
397 /* Remove the breakpoint. */
398 for (i = 0; i < max_slots; ++i) {
407 if (i == max_slots) {
408 pr_warn("Can't find any breakpoint slot\n");
412 /* Ensure that we disable the mismatch breakpoint. */
413 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
414 info->step_ctrl.enabled) {
416 base = ARM_BASE_BCR + core_num_brps;
419 /* Reset the control register. */
420 write_wb_reg(base + i, 0);
423 static int get_hbp_len(u8 hbp_len)
425 unsigned int len_in_bytes = 0;
428 case ARM_BREAKPOINT_LEN_1:
431 case ARM_BREAKPOINT_LEN_2:
434 case ARM_BREAKPOINT_LEN_4:
437 case ARM_BREAKPOINT_LEN_8:
446 * Check whether bp virtual address is in kernel space.
448 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
454 len = get_hbp_len(hw->ctrl.len);
456 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
460 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
461 * Hopefully this will disappear when ptrace can bypass the conversion
462 * to generic breakpoint descriptions.
464 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
465 int *gen_len, int *gen_type)
469 case ARM_BREAKPOINT_EXECUTE:
470 *gen_type = HW_BREAKPOINT_X;
472 case ARM_BREAKPOINT_LOAD:
473 *gen_type = HW_BREAKPOINT_R;
475 case ARM_BREAKPOINT_STORE:
476 *gen_type = HW_BREAKPOINT_W;
478 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
479 *gen_type = HW_BREAKPOINT_RW;
487 case ARM_BREAKPOINT_LEN_1:
488 *gen_len = HW_BREAKPOINT_LEN_1;
490 case ARM_BREAKPOINT_LEN_2:
491 *gen_len = HW_BREAKPOINT_LEN_2;
493 case ARM_BREAKPOINT_LEN_4:
494 *gen_len = HW_BREAKPOINT_LEN_4;
496 case ARM_BREAKPOINT_LEN_8:
497 *gen_len = HW_BREAKPOINT_LEN_8;
507 * Construct an arch_hw_breakpoint from a perf_event.
509 static int arch_build_bp_info(struct perf_event *bp,
510 const struct perf_event_attr *attr,
511 struct arch_hw_breakpoint *hw)
514 switch (attr->bp_type) {
515 case HW_BREAKPOINT_X:
516 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE;
518 case HW_BREAKPOINT_R:
519 hw->ctrl.type = ARM_BREAKPOINT_LOAD;
521 case HW_BREAKPOINT_W:
522 hw->ctrl.type = ARM_BREAKPOINT_STORE;
524 case HW_BREAKPOINT_RW:
525 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
532 switch (attr->bp_len) {
533 case HW_BREAKPOINT_LEN_1:
534 hw->ctrl.len = ARM_BREAKPOINT_LEN_1;
536 case HW_BREAKPOINT_LEN_2:
537 hw->ctrl.len = ARM_BREAKPOINT_LEN_2;
539 case HW_BREAKPOINT_LEN_4:
540 hw->ctrl.len = ARM_BREAKPOINT_LEN_4;
542 case HW_BREAKPOINT_LEN_8:
543 hw->ctrl.len = ARM_BREAKPOINT_LEN_8;
544 if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
545 && max_watchpoint_len >= 8)
547 /* Else, fall through */
553 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
554 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
555 * by the hardware and must be aligned to the appropriate number of
558 if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
559 hw->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
560 hw->ctrl.len != ARM_BREAKPOINT_LEN_4)
564 hw->address = attr->bp_addr;
567 hw->ctrl.privilege = ARM_BREAKPOINT_USER;
568 if (arch_check_bp_in_kernelspace(hw))
569 hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
572 hw->ctrl.enabled = !attr->disabled;
575 hw->ctrl.mismatch = 0;
581 * Validate the arch-specific HW Breakpoint register settings.
583 int hw_breakpoint_arch_parse(struct perf_event *bp,
584 const struct perf_event_attr *attr,
585 struct arch_hw_breakpoint *hw)
588 u32 offset, alignment_mask = 0x3;
590 /* Ensure that we are in monitor debug mode. */
591 if (!monitor_mode_enabled())
594 /* Build the arch_hw_breakpoint. */
595 ret = arch_build_bp_info(bp, attr, hw);
599 /* Check address alignment. */
600 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8)
601 alignment_mask = 0x7;
602 offset = hw->address & alignment_mask;
609 /* Allow halfword watchpoints and breakpoints. */
610 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
612 /* Else, fall through */
614 /* Allow single byte watchpoint. */
615 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
617 /* Else, fall through */
623 hw->address &= ~alignment_mask;
624 hw->ctrl.len <<= offset;
626 if (uses_default_overflow_handler(bp)) {
628 * Mismatch breakpoints are required for single-stepping
631 if (!core_has_mismatch_brps())
634 /* We don't allow mismatch breakpoints in kernel space. */
635 if (arch_check_bp_in_kernelspace(hw))
639 * Per-cpu breakpoints are not supported by our stepping
646 * We only support specific access types if the fsr
649 if (!debug_exception_updates_fsr() &&
650 (hw->ctrl.type == ARM_BREAKPOINT_LOAD ||
651 hw->ctrl.type == ARM_BREAKPOINT_STORE))
660 * Enable/disable single-stepping over the breakpoint bp at address addr.
662 static void enable_single_step(struct perf_event *bp, u32 addr)
664 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
666 arch_uninstall_hw_breakpoint(bp);
667 info->step_ctrl.mismatch = 1;
668 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
669 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
670 info->step_ctrl.privilege = info->ctrl.privilege;
671 info->step_ctrl.enabled = 1;
672 info->trigger = addr;
673 arch_install_hw_breakpoint(bp);
676 static void disable_single_step(struct perf_event *bp)
678 arch_uninstall_hw_breakpoint(bp);
679 counter_arch_bp(bp)->step_ctrl.enabled = 0;
680 arch_install_hw_breakpoint(bp);
684 * Arm32 hardware does not always report a watchpoint hit address that matches
685 * one of the watchpoints set. It can also report an address "near" the
686 * watchpoint if a single instruction access both watched and unwatched
687 * addresses. There is no straight-forward way, short of disassembling the
688 * offending instruction, to map that address back to the watchpoint. This
689 * function computes the distance of the memory access from the watchpoint as a
690 * heuristic for the likelyhood that a given access triggered the watchpoint.
692 * See this same function in the arm64 platform code, which has the same
695 * The function returns the distance of the address from the bytes watched by
696 * the watchpoint. In case of an exact match, it returns 0.
698 static u32 get_distance_from_watchpoint(unsigned long addr, u32 val,
699 struct arch_hw_breakpoint_ctrl *ctrl)
704 lens = __ffs(ctrl->len);
705 lene = __fls(ctrl->len);
708 wp_high = val + lene;
710 return wp_low - addr;
711 else if (addr > wp_high)
712 return addr - wp_high;
717 static int watchpoint_fault_on_uaccess(struct pt_regs *regs,
718 struct arch_hw_breakpoint *info)
720 return !user_mode(regs) && info->ctrl.privilege == ARM_BREAKPOINT_USER;
723 static void watchpoint_handler(unsigned long addr, unsigned int fsr,
724 struct pt_regs *regs)
726 int i, access, closest_match = 0;
727 u32 min_dist = -1, dist;
729 struct perf_event *wp, **slots;
730 struct arch_hw_breakpoint *info;
731 struct arch_hw_breakpoint_ctrl ctrl;
733 slots = this_cpu_ptr(wp_on_reg);
736 * Find all watchpoints that match the reported address. If no exact
737 * match is found. Attribute the hit to the closest watchpoint.
740 for (i = 0; i < core_num_wrps; ++i) {
746 * The DFAR is an unknown value on debug architectures prior
747 * to 7.1. Since we only allow a single watchpoint on these
748 * older CPUs, we can set the trigger to the lowest possible
751 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
753 info = counter_arch_bp(wp);
754 info->trigger = wp->attr.bp_addr;
756 /* Check that the access type matches. */
757 if (debug_exception_updates_fsr()) {
758 access = (fsr & ARM_FSR_ACCESS_MASK) ?
759 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
760 if (!(access & hw_breakpoint_type(wp)))
764 val = read_wb_reg(ARM_BASE_WVR + i);
765 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
766 decode_ctrl_reg(ctrl_reg, &ctrl);
767 dist = get_distance_from_watchpoint(addr, val, &ctrl);
768 if (dist < min_dist) {
772 /* Is this an exact match? */
776 /* We have a winner. */
777 info = counter_arch_bp(wp);
778 info->trigger = addr;
781 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
784 * If we triggered a user watchpoint from a uaccess routine,
785 * then handle the stepping ourselves since userspace really
786 * can't help us with this.
788 if (watchpoint_fault_on_uaccess(regs, info))
791 perf_bp_event(wp, regs);
794 * Defer stepping to the overflow handler if one is installed.
795 * Otherwise, insert a temporary mismatch breakpoint so that
796 * we can single-step over the watchpoint trigger.
798 if (!uses_default_overflow_handler(wp))
801 enable_single_step(wp, instruction_pointer(regs));
804 if (min_dist > 0 && min_dist != -1) {
805 /* No exact match found. */
806 wp = slots[closest_match];
807 info = counter_arch_bp(wp);
808 info->trigger = addr;
809 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
810 perf_bp_event(wp, regs);
811 if (uses_default_overflow_handler(wp))
812 enable_single_step(wp, instruction_pointer(regs));
818 static void watchpoint_single_step_handler(unsigned long pc)
821 struct perf_event *wp, **slots;
822 struct arch_hw_breakpoint *info;
824 slots = this_cpu_ptr(wp_on_reg);
826 for (i = 0; i < core_num_wrps; ++i) {
834 info = counter_arch_bp(wp);
835 if (!info->step_ctrl.enabled)
839 * Restore the original watchpoint if we've completed the
842 if (info->trigger != pc)
843 disable_single_step(wp);
850 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
853 u32 ctrl_reg, val, addr;
854 struct perf_event *bp, **slots;
855 struct arch_hw_breakpoint *info;
856 struct arch_hw_breakpoint_ctrl ctrl;
858 slots = this_cpu_ptr(bp_on_reg);
860 /* The exception entry code places the amended lr in the PC. */
863 /* Check the currently installed breakpoints first. */
864 for (i = 0; i < core_num_brps; ++i) {
872 info = counter_arch_bp(bp);
874 /* Check if the breakpoint value matches. */
875 val = read_wb_reg(ARM_BASE_BVR + i);
876 if (val != (addr & ~0x3))
879 /* Possible match, check the byte address select to confirm. */
880 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
881 decode_ctrl_reg(ctrl_reg, &ctrl);
882 if ((1 << (addr & 0x3)) & ctrl.len) {
883 info->trigger = addr;
884 pr_debug("breakpoint fired: address = 0x%x\n", addr);
885 perf_bp_event(bp, regs);
886 if (uses_default_overflow_handler(bp))
887 enable_single_step(bp, addr);
892 /* If we're stepping a breakpoint, it can now be restored. */
893 if (info->step_ctrl.enabled)
894 disable_single_step(bp);
899 /* Handle any pending watchpoint single-step breakpoints. */
900 watchpoint_single_step_handler(addr);
904 * Called from either the Data Abort Handler [watchpoint] or the
905 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
907 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
908 struct pt_regs *regs)
915 if (interrupts_enabled(regs))
918 /* We only handle watchpoints and hardware breakpoints. */
919 ARM_DBG_READ(c0, c1, 0, dscr);
921 /* Perform perf callbacks. */
922 switch (ARM_DSCR_MOE(dscr)) {
923 case ARM_ENTRY_BREAKPOINT:
924 breakpoint_handler(addr, regs);
926 case ARM_ENTRY_ASYNC_WATCHPOINT:
927 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
929 case ARM_ENTRY_SYNC_WATCHPOINT:
930 watchpoint_handler(addr, fsr, regs);
933 ret = 1; /* Unhandled fault. */
942 * One-time initialisation.
944 static cpumask_t debug_err_mask;
946 static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
948 int cpu = smp_processor_id();
950 pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
953 /* Set the error flag for this CPU and skip the faulting instruction. */
954 cpumask_set_cpu(cpu, &debug_err_mask);
955 instruction_pointer(regs) += 4;
959 static struct undef_hook debug_reg_hook = {
960 .instr_mask = 0x0fe80f10,
961 .instr_val = 0x0e000e10,
962 .fn = debug_reg_trap,
965 /* Does this core support OS Save and Restore? */
966 static bool core_has_os_save_restore(void)
970 switch (get_debug_arch()) {
971 case ARM_DEBUG_ARCH_V7_1:
973 case ARM_DEBUG_ARCH_V7_ECP14:
974 ARM_DBG_READ(c1, c1, 4, oslsr);
975 if (oslsr & ARM_OSLSR_OSLM0)
977 /* Else, fall through */
983 static void reset_ctrl_regs(unsigned int cpu)
985 int i, raw_num_brps, err = 0;
989 * v7 debug contains save and restore registers so that debug state
990 * can be maintained across low-power modes without leaving the debug
991 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
992 * the debug registers out of reset, so we must unlock the OS Lock
993 * Access Register to avoid taking undefined instruction exceptions
996 switch (debug_arch) {
997 case ARM_DEBUG_ARCH_V6:
998 case ARM_DEBUG_ARCH_V6_1:
999 /* ARMv6 cores clear the registers out of reset. */
1001 case ARM_DEBUG_ARCH_V7_ECP14:
1003 * Ensure sticky power-down is clear (i.e. debug logic is
1006 ARM_DBG_READ(c1, c5, 4, val);
1007 if ((val & 0x1) == 0)
1013 case ARM_DEBUG_ARCH_V7_1:
1015 * Ensure the OS double lock is clear.
1017 ARM_DBG_READ(c1, c3, 4, val);
1018 if ((val & 0x1) == 1)
1024 pr_warn_once("CPU %d debug is powered down!\n", cpu);
1025 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1030 * Unconditionally clear the OS lock by writing a value
1031 * other than CS_LAR_KEY to the access register.
1033 ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK);
1037 * Clear any configured vector-catch events before
1038 * enabling monitor mode.
1041 ARM_DBG_WRITE(c0, c7, 0, 0);
1044 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1045 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
1050 * The control/value register pairs are UNKNOWN out of reset so
1051 * clear them to avoid spurious debug events.
1053 raw_num_brps = get_num_brp_resources();
1054 for (i = 0; i < raw_num_brps; ++i) {
1055 write_wb_reg(ARM_BASE_BCR + i, 0UL);
1056 write_wb_reg(ARM_BASE_BVR + i, 0UL);
1059 for (i = 0; i < core_num_wrps; ++i) {
1060 write_wb_reg(ARM_BASE_WCR + i, 0UL);
1061 write_wb_reg(ARM_BASE_WVR + i, 0UL);
1064 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1065 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1070 * Have a crack at enabling monitor mode. We don't actually need
1071 * it yet, but reporting an error early is useful if it fails.
1074 if (enable_monitor_mode())
1075 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1078 static int dbg_reset_online(unsigned int cpu)
1080 local_irq_disable();
1081 reset_ctrl_regs(cpu);
1086 #ifdef CONFIG_CPU_PM
1087 static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
1090 if (action == CPU_PM_EXIT)
1091 reset_ctrl_regs(smp_processor_id());
1096 static struct notifier_block dbg_cpu_pm_nb = {
1097 .notifier_call = dbg_cpu_pm_notify,
1100 static void __init pm_init(void)
1102 cpu_pm_register_notifier(&dbg_cpu_pm_nb);
1105 static inline void pm_init(void)
1110 static int __init arch_hw_breakpoint_init(void)
1114 debug_arch = get_debug_arch();
1116 if (!debug_arch_supported()) {
1117 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1122 * Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD
1123 * whenever a WFI is issued, even if the core is not powered down, in
1124 * violation of the architecture. When DBGPRSR.SPD is set, accesses to
1125 * breakpoint and watchpoint registers are treated as undefined, so
1126 * this results in boot time and runtime failures when these are
1127 * accessed and we unexpectedly take a trap.
1129 * It's not clear if/how this can be worked around, so we blacklist
1130 * Scorpion CPUs to avoid these issues.
1132 if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
1133 pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
1137 has_ossr = core_has_os_save_restore();
1139 /* Determine how many BRPs/WRPs are available. */
1140 core_num_brps = get_num_brps();
1141 core_num_wrps = get_num_wrps();
1144 * We need to tread carefully here because DBGSWENABLE may be
1145 * driven low on this core and there isn't an architected way to
1149 register_undef_hook(&debug_reg_hook);
1152 * Register CPU notifier which resets the breakpoint resources. We
1153 * assume that a halting debugger will leave the world in a nice state
1156 ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN,
1157 "arm/hw_breakpoint:online",
1158 dbg_reset_online, NULL);
1159 unregister_undef_hook(&debug_reg_hook);
1160 if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) {
1164 cpuhp_remove_state_nocalls_cpuslocked(ret);
1169 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1170 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1173 /* Work out the maximum supported watchpoint length. */
1174 max_watchpoint_len = get_max_wp_len();
1175 pr_info("maximum watchpoint size is %u bytes.\n",
1176 max_watchpoint_len);
1178 /* Register debug fault handler. */
1179 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1180 TRAP_HWBKPT, "watchpoint debug exception");
1181 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1182 TRAP_HWBKPT, "breakpoint debug exception");
1185 /* Register PM notifiers. */
1189 arch_initcall(arch_hw_breakpoint_init);
1191 void hw_breakpoint_pmu_read(struct perf_event *bp)
1196 * Dummy function to register with die_notifier.
1198 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1199 unsigned long val, void *data)