2 * arch/arm/include/asm/pgtable-3level.h
4 * Copyright (C) 2011 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _ASM_PGTABLE_3LEVEL_H
21 #define _ASM_PGTABLE_3LEVEL_H
24 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
25 * 8 bytes each, occupying a 4K page. The first level table covers a range of
26 * 512GB, each entry representing 1GB. Since we are limited to 4GB input
27 * address range, only 4 entries in the PGD are used.
29 * There are enough spare bits in a page table entry for the kernel specific
32 #define PTRS_PER_PTE 512
33 #define PTRS_PER_PMD 512
34 #define PTRS_PER_PGD 4
36 #define PTE_HWTABLE_PTRS (0)
37 #define PTE_HWTABLE_OFF (0)
38 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
40 #define MAX_POSSIBLE_PHYSMEM_BITS 40
43 * PGDIR_SHIFT determines the size a top-level page table entry can map.
45 #define PGDIR_SHIFT 30
48 * PMD_SHIFT determines the size a middle-level page table entry can map.
52 #define PMD_SIZE (1UL << PMD_SHIFT)
53 #define PMD_MASK (~((1 << PMD_SHIFT) - 1))
54 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
55 #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1))
58 * section address mask and size definitions.
60 #define SECTION_SHIFT 21
61 #define SECTION_SIZE (1UL << SECTION_SHIFT)
62 #define SECTION_MASK (~((1 << SECTION_SHIFT) - 1))
64 #define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
67 * Hugetlb definitions.
69 #define HPAGE_SHIFT PMD_SHIFT
70 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
71 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
72 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
75 * "Linux" PTE definitions for LPAE.
77 * These bits overlap with the hardware bits but the naming is preserved for
78 * consistency with the classic page table format.
80 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
81 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
82 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
83 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
84 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
85 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
86 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 55)
87 #define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56)
88 #define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
89 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 58) /* READ ONLY */
91 #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
92 #define L_PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
93 #define L_PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
94 #define L_PMD_SECT_RDONLY (_AT(pteval_t, 1) << 58)
97 * To be used in assembly code with the upper page attributes.
99 #define L_PTE_XN_HIGH (1 << (54 - 32))
100 #define L_PTE_DIRTY_HIGH (1 << (55 - 32))
103 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
105 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
106 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
107 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
108 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
109 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
110 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
111 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
112 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
113 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
114 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
117 * Software PGD flags.
119 #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
122 * 2nd stage PTE definitions for LPAE.
124 #define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
125 #define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
126 #define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
127 #define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
128 #define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
130 #define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
131 #define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
133 #define L_PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[1] */
134 #define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
137 * Hyp-mode PL2 PTE definitions for LPAE.
139 #define L_PTE_HYP L_PTE_USER
143 #define pud_none(pud) (!pud_val(pud))
144 #define pud_bad(pud) (!(pud_val(pud) & 2))
145 #define pud_present(pud) (pud_val(pud))
146 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
148 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
150 #define pmd_large(pmd) pmd_sect(pmd)
152 #define pud_clear(pudp) \
155 clean_pmd_entry(pudp); \
158 #define set_pud(pudp, pud) \
161 flush_pmd_entry(pudp); \
164 static inline pmd_t *pud_page_vaddr(pud_t pud)
166 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
169 /* Find an entry in the second-level page table.. */
170 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
171 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
173 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
176 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
178 #define copy_pmd(pmdpd,pmdps) \
181 flush_pmd_entry(pmdpd); \
184 #define pmd_clear(pmdp) \
187 clean_pmd_entry(pmdp); \
191 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
192 * that are written to a page table but not for ptes created with mk_pte.
194 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
195 * hugetlb_cow, where it is compared with an entry in a page table.
196 * This comparison test fails erroneously leading ultimately to a memory leak.
198 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
199 * present before running the comparison.
201 #define __HAVE_ARCH_PTE_SAME
202 #define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
204 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
207 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
209 #define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
210 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
212 #define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \
213 : !!(pmd_val(pmd) & (val)))
214 #define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val)))
216 #define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID))
217 #define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
218 #define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
219 static inline pte_t pte_mkspecial(pte_t pte)
221 pte_val(pte) |= L_PTE_SPECIAL;
224 #define __HAVE_ARCH_PTE_SPECIAL
226 #define __HAVE_ARCH_PMD_WRITE
227 #define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
228 #define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY))
229 #define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
230 #define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
232 #define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd))
233 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
235 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
236 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd))
239 #define PMD_BIT_FUNC(fn,op) \
240 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
242 PMD_BIT_FUNC(wrprotect, |= L_PMD_SECT_RDONLY);
243 PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
244 PMD_BIT_FUNC(mkwrite, &= ~L_PMD_SECT_RDONLY);
245 PMD_BIT_FUNC(mkdirty, |= L_PMD_SECT_DIRTY);
246 PMD_BIT_FUNC(mkclean, &= ~L_PMD_SECT_DIRTY);
247 PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
249 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
251 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
252 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
253 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
255 /* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
256 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
258 return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
261 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
263 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY |
264 L_PMD_SECT_VALID | L_PMD_SECT_NONE;
265 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
269 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
270 pmd_t *pmdp, pmd_t pmd)
272 BUG_ON(addr >= TASK_SIZE);
274 /* create a faulting entry if PROT_NONE protected */
275 if (pmd_val(pmd) & L_PMD_SECT_NONE)
276 pmd_val(pmd) &= ~L_PMD_SECT_VALID;
278 if (pmd_write(pmd) && pmd_dirty(pmd))
279 pmd_val(pmd) &= ~PMD_SECT_AP2;
281 pmd_val(pmd) |= PMD_SECT_AP2;
283 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
284 flush_pmd_entry(pmdp);
287 #endif /* __ASSEMBLY__ */
289 #endif /* _ASM_PGTABLE_3LEVEL_H */