2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/opcodes-virt.h>
25 #include <asm/asm-offsets.h>
27 #include <asm/thread_info.h>
28 #include <asm/uaccess-asm.h>
33 * Endian independent macros for shifting bytes within registers.
38 #define get_byte_0 lsl #0
39 #define get_byte_1 lsr #8
40 #define get_byte_2 lsr #16
41 #define get_byte_3 lsr #24
42 #define put_byte_0 lsl #0
43 #define put_byte_1 lsl #8
44 #define put_byte_2 lsl #16
45 #define put_byte_3 lsl #24
49 #define get_byte_0 lsr #24
50 #define get_byte_1 lsr #16
51 #define get_byte_2 lsr #8
52 #define get_byte_3 lsl #0
53 #define put_byte_0 lsl #24
54 #define put_byte_1 lsl #16
55 #define put_byte_2 lsl #8
56 #define put_byte_3 lsl #0
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
63 #define ARM_BE8(code...)
67 * Data preload for architectures that support it
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...) code
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
82 * On Feroceon there is much to gain however, regardless of cache mode.
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
87 #define CALGN(code...)
90 #define IMM12_MASK 0xfff
93 * Enable and disable interrupts
95 #if __LINUX_ARM_ARCH__ >= 6
96 .macro disable_irq_notrace
100 .macro enable_irq_notrace
104 .macro disable_irq_notrace
105 msr cpsr_c, #PSR_I_BIT | SVC_MODE
108 .macro enable_irq_notrace
109 msr cpsr_c, #SVC_MODE
113 #if __LINUX_ARM_ARCH__ < 7
115 mcr p15, 0, r0, c7, c10, 4
119 mcr p15, 0, r0, c7, c5, 4
123 .macro asm_trace_hardirqs_off, save=1
124 #if defined(CONFIG_TRACE_IRQFLAGS)
126 stmdb sp!, {r0-r3, ip, lr}
128 bl trace_hardirqs_off
130 ldmia sp!, {r0-r3, ip, lr}
135 .macro asm_trace_hardirqs_on, cond=al, save=1
136 #if defined(CONFIG_TRACE_IRQFLAGS)
138 * actually the registers should be pushed and pop'd conditionally, but
139 * after bl the flags are certainly clobbered
142 stmdb sp!, {r0-r3, ip, lr}
144 bl\cond trace_hardirqs_on
146 ldmia sp!, {r0-r3, ip, lr}
151 .macro disable_irq, save=1
153 asm_trace_hardirqs_off \save
157 asm_trace_hardirqs_on
161 * Save the current IRQ state and disable IRQs. Note that this macro
162 * assumes FIQs are enabled, and that the processor is in SVC mode.
164 .macro save_and_disable_irqs, oldcpsr
165 #ifdef CONFIG_CPU_V7M
166 mrs \oldcpsr, primask
173 .macro save_and_disable_irqs_notrace, oldcpsr
174 #ifdef CONFIG_CPU_V7M
175 mrs \oldcpsr, primask
183 * Restore interrupt state previously stored in a register. We don't
184 * guarantee that this will preserve the flags.
186 .macro restore_irqs_notrace, oldcpsr
187 #ifdef CONFIG_CPU_V7M
188 msr primask, \oldcpsr
194 .macro restore_irqs, oldcpsr
195 tst \oldcpsr, #PSR_I_BIT
196 asm_trace_hardirqs_on cond=eq
197 restore_irqs_notrace \oldcpsr
201 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
202 * reference local symbols in the same assembly file which are to be
203 * resolved by the assembler. Other usage is undefined.
205 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
206 .macro badr\c, rd, sym
207 #ifdef CONFIG_THUMB2_KERNEL
216 * Get current thread_info.
218 .macro get_thread_info, rd
219 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
221 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
222 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
226 * Increment/decrement the preempt count.
228 #ifdef CONFIG_PREEMPT_COUNT
229 .macro inc_preempt_count, ti, tmp
230 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
231 add \tmp, \tmp, #1 @ increment it
232 str \tmp, [\ti, #TI_PREEMPT]
235 .macro dec_preempt_count, ti, tmp
236 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
237 sub \tmp, \tmp, #1 @ decrement it
238 str \tmp, [\ti, #TI_PREEMPT]
241 .macro dec_preempt_count_ti, ti, tmp
243 dec_preempt_count \ti, \tmp
246 .macro inc_preempt_count, ti, tmp
249 .macro dec_preempt_count, ti, tmp
252 .macro dec_preempt_count_ti, ti, tmp
258 .pushsection __ex_table,"a"; \
264 #define ALT_SMP(instr...) \
267 * Note: if you get assembler errors from ALT_UP() when building with
268 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
269 * ALT_SMP( W(instr) ... )
271 #define ALT_UP(instr...) \
272 .pushsection ".alt.smp.init", "a" ;\
275 .if . - 9997b == 2 ;\
278 .if . - 9997b != 4 ;\
279 .error "ALT_UP() content must assemble to exactly 4 bytes";\
282 #define ALT_UP_B(label) \
283 .equ up_b_offset, label - 9998b ;\
284 .pushsection ".alt.smp.init", "a" ;\
286 W(b) . + up_b_offset ;\
289 #define ALT_SMP(instr...)
290 #define ALT_UP(instr...) instr
291 #define ALT_UP_B(label) b label
295 * Instruction barrier
298 #if __LINUX_ARM_ARCH__ >= 7
300 #elif __LINUX_ARM_ARCH__ == 6
301 mcr p15, 0, r0, c7, c5, 4
306 * SMP data memory barrier
310 #if __LINUX_ARM_ARCH__ >= 7
316 #elif __LINUX_ARM_ARCH__ == 6
317 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
319 #error Incompatible SMP platform
329 #if defined(CONFIG_CPU_V7M)
331 * setmode is used to assert to be in svc mode during boot. For v7-M
332 * this is done in __v7m_setup, so setmode can be empty here.
334 .macro setmode, mode, reg
336 #elif defined(CONFIG_THUMB2_KERNEL)
337 .macro setmode, mode, reg
342 .macro setmode, mode, reg
348 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
349 * a scratch register for the macro to overwrite.
351 * This macro is intended for forcing the CPU into SVC mode at boot time.
352 * you cannot return to the original mode.
354 .macro safe_svcmode_maskall reg:req
355 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
357 eor \reg, \reg, #HYP_MODE
359 bic \reg , \reg , #MODE_MASK
360 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
361 THUMB( orr \reg , \reg , #PSR_T_BIT )
363 orr \reg, \reg, #PSR_A_BIT
372 * workaround for possibly broken pre-v6 hardware
373 * (akita, Sharp Zaurus C-1000, PXA270-based)
375 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
380 * STRT/LDRT access macros with ARM and Thumb-2 variants
382 #ifdef CONFIG_THUMB2_KERNEL
384 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
387 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
389 \instr\t\cond\().w \reg, [\ptr, #\off]
391 .error "Unsupported inc macro argument"
394 .pushsection __ex_table,"a"
400 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
401 @ explicit IT instruction needed because of the label
402 @ introduced by the USER macro
409 .error "Unsupported rept macro argument"
413 @ Slightly optimised to avoid incrementing the pointer twice
414 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
416 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
419 add\cond \ptr, #\rept * \inc
422 #else /* !CONFIG_THUMB2_KERNEL */
424 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
428 \instr\()b\t\cond \reg, [\ptr], #\inc
430 \instr\t\cond \reg, [\ptr], #\inc
432 .error "Unsupported inc macro argument"
435 .pushsection __ex_table,"a"
442 #endif /* CONFIG_THUMB2_KERNEL */
444 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
445 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
448 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
449 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
452 /* Utility macro for declaring string literals */
453 .macro string name:req, string
454 .type \name , #object
457 .size \name , . - \name
460 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
462 #if __LINUX_ARM_ARCH__ < 6
476 #ifdef CONFIG_THUMB2_KERNEL
481 .macro bug, msg, line
482 #ifdef CONFIG_THUMB2_KERNEL
487 #ifdef CONFIG_DEBUG_BUGVERBOSE
488 .pushsection .rodata.str, "aMS", %progbits, 1
491 .pushsection __bug_table, "aw"
499 #ifdef CONFIG_KPROBES
500 #define _ASM_NOKPROBE(entry) \
501 .pushsection "_kprobe_blacklist", "aw" ; \
506 #define _ASM_NOKPROBE(entry)
509 #endif /* __ASM_ASSEMBLER_H__ */