1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/assembler.h
5 * Copyright (C) 1996-2000 Russell King
7 * This file contains arm architecture specific defines
8 * for the different processors.
10 * Do not include any C declarations in this file - it is included by
13 #ifndef __ASM_ASSEMBLER_H__
14 #define __ASM_ASSEMBLER_H__
17 #error "Only include this from assembly code"
20 #include <asm/ptrace.h>
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
24 #include <asm/thread_info.h>
25 #include <asm/uaccess-asm.h>
30 * Endian independent macros for shifting bytes within registers.
35 #define get_byte_0 lsl #0
36 #define get_byte_1 lsr #8
37 #define get_byte_2 lsr #16
38 #define get_byte_3 lsr #24
39 #define put_byte_0 lsl #0
40 #define put_byte_1 lsl #8
41 #define put_byte_2 lsl #16
42 #define put_byte_3 lsl #24
46 #define get_byte_0 lsr #24
47 #define get_byte_1 lsr #16
48 #define get_byte_2 lsr #8
49 #define get_byte_3 lsl #0
50 #define put_byte_0 lsl #24
51 #define put_byte_1 lsl #16
52 #define put_byte_2 lsl #8
53 #define put_byte_3 lsl #0
56 /* Select code for any configuration running in BE8 mode */
57 #ifdef CONFIG_CPU_ENDIAN_BE8
58 #define ARM_BE8(code...) code
60 #define ARM_BE8(code...)
64 * Data preload for architectures that support it
66 #if __LINUX_ARM_ARCH__ >= 5
67 #define PLD(code...) code
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
79 * On Feroceon there is much to gain however, regardless of cache mode.
81 #ifdef CONFIG_CPU_FEROCEON
82 #define CALGN(code...) code
84 #define CALGN(code...)
87 #define IMM12_MASK 0xfff
90 * Enable and disable interrupts
92 #if __LINUX_ARM_ARCH__ >= 6
93 .macro disable_irq_notrace
97 .macro enable_irq_notrace
101 .macro disable_irq_notrace
102 msr cpsr_c, #PSR_I_BIT | SVC_MODE
105 .macro enable_irq_notrace
106 msr cpsr_c, #SVC_MODE
110 #if __LINUX_ARM_ARCH__ < 7
112 mcr p15, 0, r0, c7, c10, 4
116 mcr p15, 0, r0, c7, c5, 4
120 .macro asm_trace_hardirqs_off, save=1
121 #if defined(CONFIG_TRACE_IRQFLAGS)
123 stmdb sp!, {r0-r3, ip, lr}
125 bl trace_hardirqs_off
127 ldmia sp!, {r0-r3, ip, lr}
132 .macro asm_trace_hardirqs_on, cond=al, save=1
133 #if defined(CONFIG_TRACE_IRQFLAGS)
135 * actually the registers should be pushed and pop'd conditionally, but
136 * after bl the flags are certainly clobbered
139 stmdb sp!, {r0-r3, ip, lr}
141 bl\cond trace_hardirqs_on
143 ldmia sp!, {r0-r3, ip, lr}
148 .macro disable_irq, save=1
150 asm_trace_hardirqs_off \save
154 asm_trace_hardirqs_on
158 * Save the current IRQ state and disable IRQs. Note that this macro
159 * assumes FIQs are enabled, and that the processor is in SVC mode.
161 .macro save_and_disable_irqs, oldcpsr
162 #ifdef CONFIG_CPU_V7M
163 mrs \oldcpsr, primask
170 .macro save_and_disable_irqs_notrace, oldcpsr
171 #ifdef CONFIG_CPU_V7M
172 mrs \oldcpsr, primask
180 * Restore interrupt state previously stored in a register. We don't
181 * guarantee that this will preserve the flags.
183 .macro restore_irqs_notrace, oldcpsr
184 #ifdef CONFIG_CPU_V7M
185 msr primask, \oldcpsr
191 .macro restore_irqs, oldcpsr
192 tst \oldcpsr, #PSR_I_BIT
193 asm_trace_hardirqs_on cond=eq
194 restore_irqs_notrace \oldcpsr
198 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
199 * reference local symbols in the same assembly file which are to be
200 * resolved by the assembler. Other usage is undefined.
202 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
203 .macro badr\c, rd, sym
204 #ifdef CONFIG_THUMB2_KERNEL
213 * Get current thread_info.
215 .macro get_thread_info, rd
216 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
218 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
219 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
223 * Increment/decrement the preempt count.
225 #ifdef CONFIG_PREEMPT_COUNT
226 .macro inc_preempt_count, ti, tmp
227 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
228 add \tmp, \tmp, #1 @ increment it
229 str \tmp, [\ti, #TI_PREEMPT]
232 .macro dec_preempt_count, ti, tmp
233 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
234 sub \tmp, \tmp, #1 @ decrement it
235 str \tmp, [\ti, #TI_PREEMPT]
238 .macro dec_preempt_count_ti, ti, tmp
240 dec_preempt_count \ti, \tmp
243 .macro inc_preempt_count, ti, tmp
246 .macro dec_preempt_count, ti, tmp
249 .macro dec_preempt_count_ti, ti, tmp
253 #define USERL(l, x...) \
255 .pushsection __ex_table,"a"; \
260 #define USER(x...) USERL(9001f, x)
263 #define ALT_SMP(instr...) \
266 * Note: if you get assembler errors from ALT_UP() when building with
267 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
268 * ALT_SMP( W(instr) ... )
270 #define ALT_UP(instr...) \
271 .pushsection ".alt.smp.init", "a" ;\
275 .if . - 9997b == 2 ;\
278 .if . - 9997b != 4 ;\
279 .error "ALT_UP() content must assemble to exactly 4 bytes";\
282 #define ALT_UP_B(label) \
283 .pushsection ".alt.smp.init", "a" ;\
286 W(b) . + (label - 9998b) ;\
289 #define ALT_SMP(instr...)
290 #define ALT_UP(instr...) instr
291 #define ALT_UP_B(label) b label
295 * Instruction barrier
298 #if __LINUX_ARM_ARCH__ >= 7
300 #elif __LINUX_ARM_ARCH__ == 6
301 mcr p15, 0, r0, c7, c5, 4
306 * SMP data memory barrier
310 #if __LINUX_ARM_ARCH__ >= 7
316 #elif __LINUX_ARM_ARCH__ == 6
317 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
319 #error Incompatible SMP platform
330 * Raw SMP data memory barrier
332 .macro __smp_dmb mode
333 #if __LINUX_ARM_ARCH__ >= 7
339 #elif __LINUX_ARM_ARCH__ == 6
340 mcr p15, 0, r0, c7, c10, 5 @ dmb
342 .error "Incompatible SMP platform"
346 #if defined(CONFIG_CPU_V7M)
348 * setmode is used to assert to be in svc mode during boot. For v7-M
349 * this is done in __v7m_setup, so setmode can be empty here.
351 .macro setmode, mode, reg
353 #elif defined(CONFIG_THUMB2_KERNEL)
354 .macro setmode, mode, reg
359 .macro setmode, mode, reg
365 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
366 * a scratch register for the macro to overwrite.
368 * This macro is intended for forcing the CPU into SVC mode at boot time.
369 * you cannot return to the original mode.
371 .macro safe_svcmode_maskall reg:req
372 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
374 eor \reg, \reg, #HYP_MODE
376 bic \reg , \reg , #MODE_MASK
377 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
378 THUMB( orr \reg , \reg , #PSR_T_BIT )
380 orr \reg, \reg, #PSR_A_BIT
389 * workaround for possibly broken pre-v6 hardware
390 * (akita, Sharp Zaurus C-1000, PXA270-based)
392 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
397 * STRT/LDRT access macros with ARM and Thumb-2 variants
399 #ifdef CONFIG_THUMB2_KERNEL
401 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
404 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
406 \instr\t\cond\().w \reg, [\ptr, #\off]
408 .error "Unsupported inc macro argument"
411 .pushsection __ex_table,"a"
417 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
418 @ explicit IT instruction needed because of the label
419 @ introduced by the USER macro
426 .error "Unsupported rept macro argument"
430 @ Slightly optimised to avoid incrementing the pointer twice
431 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
433 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
436 add\cond \ptr, #\rept * \inc
439 #else /* !CONFIG_THUMB2_KERNEL */
441 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
445 \instr\()b\t\cond \reg, [\ptr], #\inc
447 \instr\t\cond \reg, [\ptr], #\inc
449 .error "Unsupported inc macro argument"
452 .pushsection __ex_table,"a"
459 #endif /* CONFIG_THUMB2_KERNEL */
461 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
462 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
465 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
466 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
469 /* Utility macro for declaring string literals */
470 .macro string name:req, string
471 .type \name , #object
474 .size \name , . - \name
477 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
479 #if __LINUX_ARM_ARCH__ < 6
493 #ifdef CONFIG_THUMB2_KERNEL
498 .macro bug, msg, line
499 #ifdef CONFIG_THUMB2_KERNEL
504 #ifdef CONFIG_DEBUG_BUGVERBOSE
505 .pushsection .rodata.str, "aMS", %progbits, 1
508 .pushsection __bug_table, "aw"
516 #ifdef CONFIG_KPROBES
517 #define _ASM_NOKPROBE(entry) \
518 .pushsection "_kprobe_blacklist", "aw" ; \
523 #define _ASM_NOKPROBE(entry)
526 .macro __adldst_l, op, reg, sym, tmp, c
527 .if __LINUX_ARM_ARCH__ < 7
531 .La\@: .long \sym - .Lpc\@
537 movw\c \tmp, #:lower16:\sym - .Lpc\@
538 movt\c \tmp, #:upper16:\sym - .Lpc\@
541 #ifndef CONFIG_THUMB2_KERNEL
542 .set .Lpc\@, . + 8 // PC bias
546 \op\c \reg, [pc, \tmp]
549 .Lb\@: add\c \tmp, \tmp, pc
551 * In Thumb-2 builds, the PC bias depends on whether we are currently
552 * emitting into a .arm or a .thumb section. The size of the add opcode
553 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
554 * emitting in ARM mode, so let's use this to account for the bias.
556 .set .Lpc\@, . + (. - .Lb\@)
565 * mov_l - move a constant value or [relocated] address into a register
567 .macro mov_l, dst:req, imm:req
568 .if __LINUX_ARM_ARCH__ < 7
571 movw \dst, #:lower16:\imm
572 movt \dst, #:upper16:\imm
577 * adr_l - adr pseudo-op with unlimited range
579 * @dst: destination register
580 * @sym: name of the symbol
581 * @cond: conditional opcode suffix
583 .macro adr_l, dst:req, sym:req, cond
584 __adldst_l add, \dst, \sym, \dst, \cond
588 * ldr_l - ldr <literal> pseudo-op with unlimited range
590 * @dst: destination register
591 * @sym: name of the symbol
592 * @cond: conditional opcode suffix
594 .macro ldr_l, dst:req, sym:req, cond
595 __adldst_l ldr, \dst, \sym, \dst, \cond
599 * str_l - str <literal> pseudo-op with unlimited range
601 * @src: source register
602 * @sym: name of the symbol
603 * @tmp: mandatory scratch register
604 * @cond: conditional opcode suffix
606 .macro str_l, src:req, sym:req, tmp:req, cond
607 __adldst_l str, \src, \sym, \tmp, \cond
611 * rev_l - byte-swap a 32-bit value
613 * @val: source/destination register
614 * @tmp: scratch register
616 .macro rev_l, val:req, tmp:req
617 .if __LINUX_ARM_ARCH__ < 6
618 eor \tmp, \val, \val, ror #16
619 bic \tmp, \tmp, #0x00ff0000
620 mov \val, \val, ror #8
621 eor \val, \val, \tmp, lsr #8
627 #endif /* __ASM_ASSEMBLER_H__ */