2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/thread_info.h>
33 * Endian independent macros for shifting bytes within registers.
38 #define get_byte_0 lsl #0
39 #define get_byte_1 lsr #8
40 #define get_byte_2 lsr #16
41 #define get_byte_3 lsr #24
42 #define put_byte_0 lsl #0
43 #define put_byte_1 lsl #8
44 #define put_byte_2 lsl #16
45 #define put_byte_3 lsl #24
49 #define get_byte_0 lsr #24
50 #define get_byte_1 lsr #16
51 #define get_byte_2 lsr #8
52 #define get_byte_3 lsl #0
53 #define put_byte_0 lsl #24
54 #define put_byte_1 lsl #16
55 #define put_byte_2 lsl #8
56 #define put_byte_3 lsl #0
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
63 #define ARM_BE8(code...)
67 * Data preload for architectures that support it
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...) code
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
82 * On Feroceon there is much to gain however, regardless of cache mode.
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
87 #define CALGN(code...)
91 * Enable and disable interrupts
93 #if __LINUX_ARM_ARCH__ >= 6
94 .macro disable_irq_notrace
98 .macro enable_irq_notrace
102 .macro disable_irq_notrace
103 msr cpsr_c, #PSR_I_BIT | SVC_MODE
106 .macro enable_irq_notrace
107 msr cpsr_c, #SVC_MODE
111 #if __LINUX_ARM_ARCH__ < 7
113 mcr p15, 0, r0, c7, c10, 4
117 mcr p15, 0, r0, c7, c5, 4
121 .macro asm_trace_hardirqs_off, save=1
122 #if defined(CONFIG_TRACE_IRQFLAGS)
124 stmdb sp!, {r0-r3, ip, lr}
126 bl trace_hardirqs_off
128 ldmia sp!, {r0-r3, ip, lr}
133 .macro asm_trace_hardirqs_on, cond=al, save=1
134 #if defined(CONFIG_TRACE_IRQFLAGS)
136 * actually the registers should be pushed and pop'd conditionally, but
137 * after bl the flags are certainly clobbered
140 stmdb sp!, {r0-r3, ip, lr}
142 bl\cond trace_hardirqs_on
144 ldmia sp!, {r0-r3, ip, lr}
149 .macro disable_irq, save=1
151 asm_trace_hardirqs_off \save
155 asm_trace_hardirqs_on
159 * Save the current IRQ state and disable IRQs. Note that this macro
160 * assumes FIQs are enabled, and that the processor is in SVC mode.
162 .macro save_and_disable_irqs, oldcpsr
163 #ifdef CONFIG_CPU_V7M
164 mrs \oldcpsr, primask
171 .macro save_and_disable_irqs_notrace, oldcpsr
172 #ifdef CONFIG_CPU_V7M
173 mrs \oldcpsr, primask
181 * Restore interrupt state previously stored in a register. We don't
182 * guarantee that this will preserve the flags.
184 .macro restore_irqs_notrace, oldcpsr
185 #ifdef CONFIG_CPU_V7M
186 msr primask, \oldcpsr
192 .macro restore_irqs, oldcpsr
193 tst \oldcpsr, #PSR_I_BIT
194 asm_trace_hardirqs_on cond=eq
195 restore_irqs_notrace \oldcpsr
199 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
200 * reference local symbols in the same assembly file which are to be
201 * resolved by the assembler. Other usage is undefined.
203 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
204 .macro badr\c, rd, sym
205 #ifdef CONFIG_THUMB2_KERNEL
214 * Get current thread_info.
216 .macro get_thread_info, rd
217 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
219 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
220 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
224 * Increment/decrement the preempt count.
226 #ifdef CONFIG_PREEMPT_COUNT
227 .macro inc_preempt_count, ti, tmp
228 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
229 add \tmp, \tmp, #1 @ increment it
230 str \tmp, [\ti, #TI_PREEMPT]
233 .macro dec_preempt_count, ti, tmp
234 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
235 sub \tmp, \tmp, #1 @ decrement it
236 str \tmp, [\ti, #TI_PREEMPT]
239 .macro dec_preempt_count_ti, ti, tmp
241 dec_preempt_count \ti, \tmp
244 .macro inc_preempt_count, ti, tmp
247 .macro dec_preempt_count, ti, tmp
250 .macro dec_preempt_count_ti, ti, tmp
256 .pushsection __ex_table,"a"; \
262 #define ALT_SMP(instr...) \
265 * Note: if you get assembler errors from ALT_UP() when building with
266 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
267 * ALT_SMP( W(instr) ... )
269 #define ALT_UP(instr...) \
270 .pushsection ".alt.smp.init", "a" ;\
273 .if . - 9997b == 2 ;\
276 .if . - 9997b != 4 ;\
277 .error "ALT_UP() content must assemble to exactly 4 bytes";\
280 #define ALT_UP_B(label) \
281 .equ up_b_offset, label - 9998b ;\
282 .pushsection ".alt.smp.init", "a" ;\
284 W(b) . + up_b_offset ;\
287 #define ALT_SMP(instr...)
288 #define ALT_UP(instr...) instr
289 #define ALT_UP_B(label) b label
293 * Instruction barrier
296 #if __LINUX_ARM_ARCH__ >= 7
298 #elif __LINUX_ARM_ARCH__ == 6
299 mcr p15, 0, r0, c7, c5, 4
304 * SMP data memory barrier
308 #if __LINUX_ARM_ARCH__ >= 7
314 #elif __LINUX_ARM_ARCH__ == 6
315 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
317 #error Incompatible SMP platform
327 #if defined(CONFIG_CPU_V7M)
329 * setmode is used to assert to be in svc mode during boot. For v7-M
330 * this is done in __v7m_setup, so setmode can be empty here.
332 .macro setmode, mode, reg
334 #elif defined(CONFIG_THUMB2_KERNEL)
335 .macro setmode, mode, reg
340 .macro setmode, mode, reg
346 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
347 * a scratch register for the macro to overwrite.
349 * This macro is intended for forcing the CPU into SVC mode at boot time.
350 * you cannot return to the original mode.
352 .macro safe_svcmode_maskall reg:req
353 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
355 eor \reg, \reg, #HYP_MODE
357 bic \reg , \reg , #MODE_MASK
358 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
359 THUMB( orr \reg , \reg , #PSR_T_BIT )
361 orr \reg, \reg, #PSR_A_BIT
370 * workaround for possibly broken pre-v6 hardware
371 * (akita, Sharp Zaurus C-1000, PXA270-based)
373 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
378 * STRT/LDRT access macros with ARM and Thumb-2 variants
380 #ifdef CONFIG_THUMB2_KERNEL
382 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
385 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
387 \instr\cond\()\t\().w \reg, [\ptr, #\off]
389 .error "Unsupported inc macro argument"
392 .pushsection __ex_table,"a"
398 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
399 @ explicit IT instruction needed because of the label
400 @ introduced by the USER macro
407 .error "Unsupported rept macro argument"
411 @ Slightly optimised to avoid incrementing the pointer twice
412 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
414 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
417 add\cond \ptr, #\rept * \inc
420 #else /* !CONFIG_THUMB2_KERNEL */
422 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
426 \instr\cond\()b\()\t \reg, [\ptr], #\inc
428 \instr\cond\()\t \reg, [\ptr], #\inc
430 .error "Unsupported inc macro argument"
433 .pushsection __ex_table,"a"
440 #endif /* CONFIG_THUMB2_KERNEL */
442 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
443 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
446 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
447 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
450 /* Utility macro for declaring string literals */
451 .macro string name:req, string
452 .type \name , #object
455 .size \name , . - \name
459 #ifdef CONFIG_THUMB2_KERNEL
466 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
467 #ifndef CONFIG_CPU_USE_DOMAINS
468 adds \tmp, \addr, #\size - 1
469 sbcccs \tmp, \tmp, \limit
471 #ifdef CONFIG_CPU_SPECTRE
478 .macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
479 #ifdef CONFIG_CPU_SPECTRE
481 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
482 addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
483 subhss \tmp, \tmp, \size @ tmp = limit - (addr + size) }
484 movlo \addr, #0 @ if (tmp < 0) addr = NULL
489 .macro uaccess_disable, tmp, isb=1
490 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
492 * Whenever we re-enter userspace, the domains should always be
495 mov \tmp, #DACR_UACCESS_DISABLE
496 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
503 .macro uaccess_enable, tmp, isb=1
504 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
506 * Whenever we re-enter userspace, the domains should always be
509 mov \tmp, #DACR_UACCESS_ENABLE
510 mcr p15, 0, \tmp, c3, c0, 0
517 .macro uaccess_save, tmp
518 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
519 mrc p15, 0, \tmp, c3, c0, 0
520 str \tmp, [sp, #SVC_DACR]
524 .macro uaccess_restore
525 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
526 ldr r0, [sp, #SVC_DACR]
527 mcr p15, 0, r0, c3, c0, 0
531 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
533 #if __LINUX_ARM_ARCH__ < 6
547 #ifdef CONFIG_THUMB2_KERNEL
552 .macro bug, msg, line
553 #ifdef CONFIG_THUMB2_KERNEL
558 #ifdef CONFIG_DEBUG_BUGVERBOSE
559 .pushsection .rodata.str, "aMS", %progbits, 1
562 .pushsection __bug_table, "aw"
570 #ifdef CONFIG_KPROBES
571 #define _ASM_NOKPROBE(entry) \
572 .pushsection "_kprobe_blacklist", "aw" ; \
577 #define _ASM_NOKPROBE(entry)
580 #endif /* __ASM_ASSEMBLER_H__ */