arch/arm/common/it8152.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/arch/arm/common/it8152.c
   4  *
   5  * Copyright Compulab Ltd, 2002-2007
   6  * Mike Rapoport <mike@compulab.co.il>
   7  *
   8  * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
   9  * (see this file for respective copyrights)
  10  *
  11  * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
  12  * and demux code.
  13  */
  14
  15 #include <linux/sched.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/ptrace.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/mm.h>
  21 #include <linux/init.h>
  22 #include <linux/ioport.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <linux/export.h>
  26
  27 #include <asm/mach/pci.h>
  28 #include <asm/hardware/it8152.h>
  29
  30 #define MAX_SLOTS               21
  31
  32 static void it8152_mask_irq(struct irq_data *d)
  33 {
  34         unsigned int irq = d->irq;
  35
  36        if (irq >= IT8152_LD_IRQ(0)) {
  37                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
  38                             (1 << (irq - IT8152_LD_IRQ(0)))),
  39                             IT8152_INTC_LDCNIMR);
  40        } else if (irq >= IT8152_LP_IRQ(0)) {
  41                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
  42                             (1 << (irq - IT8152_LP_IRQ(0)))),
  43                             IT8152_INTC_LPCNIMR);
  44        } else if (irq >= IT8152_PD_IRQ(0)) {
  45                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
  46                             (1 << (irq - IT8152_PD_IRQ(0)))),
  47                             IT8152_INTC_PDCNIMR);
  48        }
  49 }
  50
  51 static void it8152_unmask_irq(struct irq_data *d)
  52 {
  53         unsigned int irq = d->irq;
  54
  55        if (irq >= IT8152_LD_IRQ(0)) {
  56                __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
  57                              ~(1 << (irq - IT8152_LD_IRQ(0)))),
  58                             IT8152_INTC_LDCNIMR);
  59        } else if (irq >= IT8152_LP_IRQ(0)) {
  60                __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
  61                              ~(1 << (irq - IT8152_LP_IRQ(0)))),
  62                             IT8152_INTC_LPCNIMR);
  63        } else if (irq >= IT8152_PD_IRQ(0)) {
  64                __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
  65                              ~(1 << (irq - IT8152_PD_IRQ(0)))),
  66                             IT8152_INTC_PDCNIMR);
  67        }
  68 }
  69
  70 static struct irq_chip it8152_irq_chip = {
  71         .name           = "it8152",
  72         .irq_ack        = it8152_mask_irq,
  73         .irq_mask       = it8152_mask_irq,
  74         .irq_unmask     = it8152_unmask_irq,
  75 };
  76
  77 void it8152_init_irq(void)
  78 {
  79         int irq;
  80
  81         __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
  82         __raw_writel((0), IT8152_INTC_PDCNIRR);
  83         __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
  84         __raw_writel((0), IT8152_INTC_LPCNIRR);
  85         __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
  86         __raw_writel((0), IT8152_INTC_LDCNIRR);
  87
  88         for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
  89                 irq_set_chip_and_handler(irq, &it8152_irq_chip,
  90                                          handle_level_irq);
  91                 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  92         }
  93 }
  94
  95 void it8152_irq_demux(struct irq_desc *desc)
  96 {
  97        int bits_pd, bits_lp, bits_ld;
  98        int i;
  99
 100        while (1) {
 101                /* Read all */
 102                bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
 103                bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
 104                bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
 105
 106                /* Ack */
 107                __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
 108                __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
 109                __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
 110
 111                if (!(bits_ld | bits_lp | bits_pd)) {
 112                        /* Re-read to guarantee, that there was a moment of
 113                           time, when they all three were 0. */
 114                        bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
 115                        bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
 116                        bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
 117                        if (!(bits_ld | bits_lp | bits_pd))
 118                                return;
 119                }
 120
 121                bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
 122                while (bits_pd) {
 123                        i = __ffs(bits_pd);
 124                        generic_handle_irq(IT8152_PD_IRQ(i));
 125                        bits_pd &= ~(1 << i);
 126                }
 127
 128                bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
 129                while (bits_lp) {
 130                        i = __ffs(bits_lp);
 131                        generic_handle_irq(IT8152_LP_IRQ(i));
 132                        bits_lp &= ~(1 << i);
 133                }
 134
 135                bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
 136                while (bits_ld) {
 137                        i = __ffs(bits_ld);
 138                        generic_handle_irq(IT8152_LD_IRQ(i));
 139                        bits_ld &= ~(1 << i);
 140                }
 141        }
 142 }
 143
 144 /* mapping for on-chip devices */
 145 int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 146 {
 147         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
 148             (dev->device == PCI_DEVICE_ID_ITE_8152)) {
 149                 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
 150                         return IT8152_AUDIO_INT;
 151                 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
 152                         return IT8152_USB_INT;
 153                 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
 154                         return IT8152_CDMA_INT;
 155         }
 156
 157         return 0;
 158 }
 159
 160 static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
 161                                                  unsigned int devfn)
 162 {
 163         unsigned long addr = 0;
 164
 165         if (bus->number == 0) {
 166                         if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
 167                                 addr = (devfn << 8);
 168         } else
 169                 addr = (bus->number << 16) | (devfn << 8);
 170
 171         return addr;
 172 }
 173
 174 static int it8152_pci_read_config(struct pci_bus *bus,
 175                                   unsigned int devfn, int where,
 176                                   int size, u32 *value)
 177 {
 178         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
 179         u32 v;
 180         int shift;
 181
 182         shift = (where & 3);
 183
 184         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
 185         v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));
 186
 187         *value = v;
 188
 189         return PCIBIOS_SUCCESSFUL;
 190 }
 191
 192 static int it8152_pci_write_config(struct pci_bus *bus,
 193                                    unsigned int devfn, int where,
 194                                    int size, u32 value)
 195 {
 196         unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
 197         u32 v, vtemp, mask = 0;
 198         int shift;
 199
 200         if (size == 1)
 201                 mask = 0xff;
 202         if (size == 2)
 203                 mask = 0xffff;
 204
 205         shift = (where & 3);
 206
 207         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
 208         vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
 209
 210         if (mask)
 211                 vtemp &= ~(mask << (8 * shift));
 212         else
 213                 vtemp = 0;
 214
 215         v = (value << (8 * shift));
 216         __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
 217         __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
 218
 219         return PCIBIOS_SUCCESSFUL;
 220 }
 221
 222 struct pci_ops it8152_ops = {
 223         .read = it8152_pci_read_config,
 224         .write = it8152_pci_write_config,
 225 };
 226
 227 static struct resource it8152_io = {
 228         .name   = "IT8152 PCI I/O region",
 229         .flags  = IORESOURCE_IO,
 230 };
 231
 232 static struct resource it8152_mem = {
 233         .name   = "IT8152 PCI memory region",
 234         .start  = 0x10000000,
 235         .end    = 0x13e00000,
 236         .flags  = IORESOURCE_MEM,
 237 };
 238
 239 /*
 240  * The following functions are needed for DMA bouncing.
 241  * ITE8152 chip can address up to 64MByte, so all the devices
 242  * connected to ITE8152 (PCI and USB) should have limited DMA window
 243  */
 244 static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
 245 {
 246         dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
 247                 __func__, dma_addr, size);
 248         return (dma_addr + size - PHYS_OFFSET) >= SZ_64M;
 249 }
 250
 251 /*
 252  * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
 253  * other devices.
 254  */
 255 static int it8152_pci_platform_notify(struct device *dev)
 256 {
 257         if (dev_is_pci(dev)) {
 258                 if (dev->dma_mask)
 259                         *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
 260                 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
 261                 dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
 262         }
 263         return 0;
 264 }
 265
 266 static int it8152_pci_platform_notify_remove(struct device *dev)
 267 {
 268         if (dev_is_pci(dev))
 269                 dmabounce_unregister_dev(dev);
 270
 271         return 0;
 272 }
 273
 274 int dma_set_coherent_mask(struct device *dev, u64 mask)
 275 {
 276         if (mask >= PHYS_OFFSET + SZ_64M - 1)
 277                 return 0;
 278
 279         return -EIO;
 280 }
 281
 282 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 283 {
 284         /*
 285          * FIXME: use pci_ioremap_io to remap the IO space here and
 286          * move over to the generic io.h implementation.
 287          * This requires solving the same problem for PXA PCMCIA
 288          * support.
 289          */
 290         it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
 291         it8152_io.end   = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
 292
 293         sys->mem_offset = 0x10000000;
 294         sys->io_offset  = (unsigned long)IT8152_IO_BASE;
 295
 296         if (request_resource(&ioport_resource, &it8152_io)) {
 297                 printk(KERN_ERR "PCI: unable to allocate IO region\n");
 298                 goto err0;
 299         }
 300         if (request_resource(&iomem_resource, &it8152_mem)) {
 301                 printk(KERN_ERR "PCI: unable to allocate memory region\n");
 302                 goto err1;
 303         }
 304
 305         pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
 306         pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
 307
 308         if (platform_notify || platform_notify_remove) {
 309                 printk(KERN_ERR "PCI: Can't use platform_notify\n");
 310                 goto err2;
 311         }
 312
 313         platform_notify = it8152_pci_platform_notify;
 314         platform_notify_remove = it8152_pci_platform_notify_remove;
 315
 316         return 1;
 317
 318 err2:
 319         release_resource(&it8152_io);
 320 err1:
 321         release_resource(&it8152_mem);
 322 err0:
 323         return -EBUSY;
 324 }
 325
 326 /* ITE bridge requires setting latency timer to avoid early bus access
 327    termination by PCI bus master devices
 328 */
 329 void pcibios_set_master(struct pci_dev *dev)
 330 {
 331         u8 lat;
 332
 333         /* no need to update on-chip OHCI controller */
 334         if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
 335             (dev->device == PCI_DEVICE_ID_ITE_8152) &&
 336             ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
 337                 return;
 338
 339         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 340         if (lat < 16)
 341                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 342         else if (lat > pcibios_max_latency)
 343                 lat = pcibios_max_latency;
 344         else
 345                 return;
 346         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
 347                pci_name(dev), lat);
 348         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 349 }
 350
 351
 352 EXPORT_SYMBOL(dma_set_coherent_mask);